JPH0621405A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a wiring state, in which the capacity of a semiconductor substrate is improved, by forming an interlayer film thicker than that of a gate region necessary for logical constitution in a gate region unnecessary for logical constitution. CONSTITUTION:A side holding LOCOS oxide film 6 between is a gate region 9 necessary for logical constitution and the right side is a gate region 10 unnecessary for logical constitution and used as a wiring region between cells. A new interlayer film 8 is formed in a part of the gate region 10, before a metal thin film 7 being a wiring is formed. After that, a wiring for the logical constitution of a cell is arranged in the gate region 9 by means of the metal thin film 7 and a wiring material between respective cells is arranged on the interlayer film 8 newly formed in the part of the gate region 10. This method has the effect of decreasing the capacities of a wiring material between cells and semiconductor substrate and increasing a speed for operating as IC. Also, flattening is made possible and the throwing power of the wiring material can be improved when the new interlayer film is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides a thicker inter-layer film, or one or more new inter-layer film, in a gate region which is not necessary in the logical structure than in the gate region which is necessary in the logical structure. The present invention relates to a semiconductor device.

[0002]

2. Description of the Related Art In the prior art, as shown in FIG. 4, when a gate area which is not necessary in terms of logical structure is used as a wiring area for each cell in a gate array of a gate full surface gate type. As shown in FIG. 3, the wiring material for the logical configuration in the cell and the wiring material between the cells are provided at the same distance from the semiconductor substrate and on the same multilayer thin film structure.

[0003]

In the conventional wiring material forming state, as shown in FIG. 3, an electrode on the gate region 10 used as a wiring region between cells or a metal thin film 7 which is a wiring. In the gate array which is not the gate full-gate type shown in FIG. 6, the distance from the semiconductor substrate is shorter than that of the metal thin film 7 on the wiring exclusive area 11 between cells as shown in FIG. Will end up. The distance to the semiconductor substrate is to, the facing area between the wiring material and the semiconductor substrate is So, the capacitance therebetween is Co,
As is clear from the relationship expressed by the first equation, Co ∝ So / to (Equation 1), the entire surface of the chip is covered with the gate even if the inter-cell wiring has the same length. Since the to-array wiring material has a shorter to, the parasitic capacitance between the wiring and the semiconductor substrate increases, which causes a problem that the operating speed of the integrated circuit becomes slower.

Therefore, in order to solve the above-mentioned conventional problems, the present invention covers the entire surface of the gate even when the gate area which is not necessary in the logical structure is used as the wiring area between the cells. It is an object of the present invention to provide a wiring state in which the capacitance with the semiconductor substrate is improved as well as the wiring between cells of the non-type gate array.

[0005]

In order to solve the above-mentioned problems, a semiconductor device of the present invention is provided with a thicker interlayer than before a wiring material manufacturing process between cells, as compared with a gate region which is not necessary in a logical structure. It is characterized in that a film or a new interlayer film of one or more layers is formed.

[0006]

In the semiconductor device configured as described above,
Even if a gate region which is not necessary for the logical structure is used as a wiring region between cells, whether an oxide film is selectively formed on the wiring region by a CVD technique or the like before the wiring material manufacturing process between cells is performed. Alternatively, by forming a new interlayer film with an organic solution material such as polyimide, the distance between the wiring material and the semiconductor substrate is increased, and the operation speed as an IC can be increased. Further, by providing a new interlayer film, it is possible to flatten and improve the distribution of the wiring material.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. As an example, FIG. 1 is a cross-sectional view of an interlayer film of a gate region which is not required for the logical structure formed by photolithography using a photosensitive organic material such as polyimide, and is newly added to a gate region which is not required for the logical structure. FIG. 2 shows a cross-sectional view of the one-layer interlayer film formed. LOC in Figure 1
The left side across the OS oxide film 6 is the gate required for the logical configuration.
The gate area 9 and the gate area 10 on the right side, which is not necessary in the logical configuration, is used as the inter-cell wiring area. Before forming the metal thin film 7 which is a wiring, by photolithography using a photosensitive organic material such as polyimide on the first layer interlayer film of the gate area which is not necessary in the logical configuration used as the inter-cell wiring area. A new interlayer film 8 is formed. After that, the gate region 9 necessary for the logical structure is formed by the metal thin film 7 which is the wiring.
Wiring for the logical configuration of cells is provided on the upper side, and wiring between the cells is provided on the newly formed interlayer film 8 in the gate region 10 portion which is not necessary for the logical configuration to be used as the inter-cell wiring area. The material will be placed. In FIG. 2, C is provided in the portion of the gate area 10 which is not necessary in the logical configuration and is used as the inter-cell wiring area before the metal thin film 7 which is the wiring is formed.
A new interlayer film 8 is formed by the VD technique. As an example, BPSG (Boron-Phosph) is used as a new interlayer film.
FIG. 7 shows a forming method in the case of using an silicate glass) film. FIG. 7A is a sectional view of the element before a new interlayer film is formed, and the first interlayer film is formed on the gate electrode. FIG. 7B shows a BPSG film formed on the surface of FIG.
It is sectional drawing of what was accumulated from 0Å to 3000Å. In FIG. 7C, the BPSG film is formed by a photolithography technique, and the first interlayer film and the newly formed interlayer film have chemical properties, leaving a gate region which is not necessary for the logical structure. Are selectively removed by utilizing the fact that they are different. After that, as shown in FIG. 8A, reflow is performed in a nitrogen atmosphere at 800 ° C. to 900 ° C. to flatten the surface. Finally, the metal thin film 7 which is the wiring in FIG.
As a result, the logical structure of the cells is arranged, and the wiring material between the cells is arranged on the new interlayer insulating film 12.

In the above embodiment, the gate area 10 used as the inter-cell wiring area, which is not necessary in the logical configuration, is used.
The metal thin film 7 which is the upper electrode or wiring has a longer distance from the semiconductor substrate 1 as compared with the conventional one shown in FIG.
In the meantime, the capacity can be reduced.

Even if the newly formed interlayer film is formed in the interlayer film between the first-layer metal wiring and the second-layer metal wiring, the same is true for the second-layer and subsequent metal wiring. The effect can be obtained. The same applies to the subsequent steps.

Further, with respect to a newly formed interlayer film, the same effect can be obtained when the interlayer film is formed of two layers or three layers or more.

[0011]

As described above, the semiconductor device of the present invention is, in the gate array of the entire surface of the chip gate type, as described above, the gate area necessary for the logical structure in the gate area which is not necessary for the logical structure. By a simple method of forming an interlayer film that is thicker than the area or one or more new interlayer films,
This has the effect of reducing the capacitance between the inter-cell wiring material and the semiconductor substrate and increasing the operating speed of the IC. Further, by providing a new interlayer film, it is possible to flatten and improve the distribution of the wiring material.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a gate array with a gate full-face gate spread type gate array when a new interlayer film is formed of an organic material according to the present invention.

FIG. 2 is a cross-sectional view of a gate array laid on the entire surface of a chip when a new interlayer film is formed by a CVD technique according to the present invention.

FIG. 3 is a cross-sectional view of a conventional gate array of gate full-laid gate arrays.

FIG. 4 is a plan view of a gate array with a whole surface of a gate spread type.

FIG. 5 is a cross-sectional view of a gate array which is not a chip full-face gate spread type.

FIG. 6 is a plan view of a gate array which is not a type in which the entire surface of the chip is gated.

FIG. 7 is a cross-sectional view showing a method of forming a gate entire surface gate spread type gate array having a new interlayer film according to the present invention.

FIG. 8 is a cross-sectional view showing a method for forming a gate full-face gate spread type gate array having a new interlayer film according to the present invention.

[Explanation of symbols]

1 ... Semiconductor substrate 2 ... Impurity diffusion region 3 ... Gate oxide film 4 ... Gate electrode 5 ... First interlayer insulating film 6 ... For element isolation LOCOS oxide film 7 ... Metal thin film as wiring material 8 ... Newly provided second interlayer insulating film 9 ... Gate area required for logical configuration 10 ... Used as inter-cell wiring area Gate area which is not necessary in the logic configuration 11 ... Inter-cell wiring dedicated area 12 ... Input / output cell area 13 ... Gate area in the entire chip gate spread type gate array 14 ... Gate configuration areas

Claims (2)

[Claims] 1. In a gate array (Sea Of Gate) of a whole-gate-gate-filled type, prior to a manufacturing process of a wiring material for wiring between cells, a gate region which is not necessary in the logical structure is formed in a logical structure. A semiconductor device having an interlayer film thicker than a necessary gate region or one or more new interlayer films. 2. The semiconductor device according to claim 1, wherein one or more new interlayer films to be formed have different chemical characteristics from those of the first interlayer film.