JPH0621075A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method for manufacturing a semiconductor device in which isolation of elements and formation of a collector lead electrode can be conducted with a small area by a relatively simple step in the method for forming a bipolar transistor. CONSTITUTION:The method for manufacturing a semiconductor device comprises the steps of forming an element isolation region and a silicon oxide film covering a collector electrode forming region on a first conductivity type silicon substrate 10, selectively epitaxially growing a silicon layer 24a on a collector buried layer 14a not formed with the silicon oxide film, forming a contact hole reaching the layer 14a in a silicon oxide film 26, burying the polycrystalline silicon layer in a contact hole 30, and forming a collector lead electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device forming a bipolar transistor.

[0002]

2. Description of the Related Art In recent years, demands for higher integration and miniaturization of semiconductor devices have become stronger and stronger, and demands for each manufacturing process have also become stricter. For example, in element isolation technology, LOCOS isolation (Local Oxid
ation of silicon) technology is known, but while good element isolation can be performed, the element isolation region becomes large and high integration becomes difficult.

A trench isolation technique is known as another element isolation technique, but the element isolation region can be made small and high integration is easy, but the manufacturing process is complicated. On the other hand, in the case of manufacturing a planar bipolar transistor, it is necessary to form a collector extraction electrode reaching a collector buried layer embedded in a silicon substrate. Conventionally, however, a large area is required to form the collector extraction electrode. Was required and the manufacturing process was complicated.

[0004]

In the conventional technique for manufacturing the bipolar transistor integrated circuit as described above, a large area is required for element isolation, the manufacturing process is complicated, and the collector extraction electrode is not required. There is a problem that a large area is required for forming and the manufacturing process is complicated.

An object of the present invention is to provide a method of manufacturing a semiconductor device in which element isolation and a collector extraction electrode can be formed by a relatively simple process and in a small area.

[0006]

The above object is to form a second conductive type collector buried layer in an element region isolated by an element isolation region on a first conductive type silicon substrate, and to provide the first conductive type silicon. Forming a first conductivity type channel cut region in the element isolation region on a substrate; and first silicon covering the element isolation region on the first conductivity type silicon substrate and a collector electrode formation region in the element region. Forming an oxide film; selectively epitaxially growing a silicon layer on the second conductive type collector buried layer in the device region where the first silicon oxide film is not formed; Depositing a second silicon oxide film so as to cover the first silicon oxide film, and the first silicon oxide film and the second silicon in the collector electrode region. Removing the oxide film to form a contact hole reaching the second conductive type collector buried layer of the first conductive type silicon substrate, and filling the contact hole with a polycrystalline silicon layer to form the second conductive type Forming a collector extraction electrode reaching the collector buried layer; forming a first conductivity type base region on the surface of the silicon layer on the second conductivity type collector buried layer; and forming a first conductivity type base region in the first conductivity type base region. And a step of forming a second conductivity type emitter region.

[0007]

According to the present invention, element isolation between bipolar transistors can be performed and a collector extraction electrode can be formed by a relatively simple process. Moreover, since the collector extraction electrode is formed in the oxide film for element isolation, the area required for element isolation and collector extraction electrode can be reduced, and high integration of the bipolar transistor can be achieved.

[0008]

EXAMPLE A method of manufacturing a semiconductor device according to an example of the present invention will be described with reference to FIGS. First, a patterned resist layer 12 is formed on the p-type silicon substrate 10 so as to cover the element isolation regions, and n-type impurities are ion-implanted into the p-type silicon substrate 10 using the resist layer 12 as a mask. n in the device region on the surface of the p-type silicon substrate 10
The type impurity regions 14a and 14b are formed (FIG. 1).
(A)).

Next, a patterned resist layer 16 is formed so that the center of the element isolation region of the p-type silicon substrate 10 is opened, and p is used as a mask for this resist layer 126.
A p-type impurity is ion-implanted into the p-type silicon substrate 10. p
A p + type channel cut region 18 is formed in the center of the element isolation region on the surface of the type silicon substrate 10 (FIG. 1B).

Next, CVD is performed on the entire surface of the p-type silicon substrate 10.
A silicon oxide film 20 is deposited by the method. Subsequently, a resist layer 22 is formed on the silicon oxide film 20, and the resist layer 22 is patterned so as to cover only the element isolation region and the collector electrode region in the element region adjacent thereto (FIG. 1C). Next, the silicon oxide film 20 is removed by etching using the resist layer 22 as a mask to cover the element isolation region and the collector electrode region.
Pattern 0. Then, the p-type silicon substrate 10
When silicon is epitaxially grown thereon, the silicon layer 2 is formed in the element region where the silicon oxide film 20 is not formed.
4a and 24b are selectively epitaxially grown (see FIG. 1).
(D)).

Next, CVD is performed on the entire surface of the p-type silicon substrate 10.
A silicon oxide film 26 is deposited by the method (FIG. 2
(A)). Next, the resist layer 2 is formed on the silicon oxide film 26.
8 is formed and patterned to remove the collector electrode region. Then, the silicon oxide films 20 and 26 are anisotropically etched using the resist layer 28 as a mask to form a contact hole 30 reaching the n-type impurity region 14a of the p-type silicon substrate 10 (FIG. 2B). .

Next, CVD is performed on the entire surface of the p-type silicon substrate 10.
The polycrystalline silicon layer 32 is deposited by the method (FIG. 2).
(C)). Next, the polycrystalline silicon layer 32 is polished to remove the polycrystalline silicon layer 32 in regions other than the contact holes 30, and the polycrystalline silicon layer 32 is embedded only in the contact holes 30 (FIG. 3A). Subsequently, impurities are ion-implanted into the polycrystalline silicon layer 32 buried in the contact hole 30 and then annealed to activate the impurities to lower the resistance of the polycrystalline silicon layer 32 to form a collector extraction electrode 33 (FIG. 3). (A)).

Next, the base forming region of the silicon oxide film 26 on the silicon layer 24a is removed by etching, and the silicon oxide film 26 is used as a mask to form a p-layer on the surface of the silicon layer 24.
A p-type base region 34 is formed by ion-implanting type impurities (FIG. 3B). Next, the polycrystalline silicon layer 36 is embedded on the p-type base region 34, and impurities are ion-implanted to reduce the resistance (FIG. 3C).

Next, a silicon oxide film 38 is formed on the entire surface by the CVD method, and the resist layer 4 is formed on the silicon oxide film 38.
0 is applied and patterning is performed so that the emitter formation region is opened. Then, the silicon oxide film 38 and the polycrystalline silicon layer 36 are anisotropically etched using the resist layer 40 as a mask to form a contact hole 42 on the emitter formation region (FIG. 4A). Then, the resist layer 40 is removed.

Next, a silicon oxide film is formed on the entire surface and then anisotropically etched to form sidewalls 44 on the sidewalls of the contact holes 42 (FIG. 4).
(B)). Subsequently, an impurity-doped polycrystalline silicon layer (not shown) is formed in the contact hole 42, and the impurity is diffused from the polycrystalline silicon layer to the p-type base region 34 to form the n-type emitter region 46. Yes (Fig. 4
(B)).

Next, after forming contact holes for the base electrode and the collector electrode in the silicon oxide film 38,
Base electrode 4 contacting the polycrystalline silicon layer 36
8. An npn bipolar transistor is completed by forming an emitter electrode 50 contacting the n-type emitter region 46 and a collector electrode 52 contacting the polycrystalline silicon layer 32 (FIG. 4C).

As described above, according to the present embodiment, the element is separated by the silicon oxide film and the channel cut region, and the collector extraction electrode reaching the collector buried layer is formed in the silicon oxide film for element separation, so that the area is small. It is possible to separate the elements and form a collector extraction electrode.
Moreover, a highly integrated bipolar transistor can be manufactured by a simple manufacturing process that does not require a complicated process such as the groove separation technique.

The present invention is not limited to the above embodiment, but various modifications are possible. For example, although the npn bipolar transistor is manufactured in the above embodiment, the present invention may be applied to the manufacture of the pnp bipolar transistor.

[0019]

As described above, according to the present invention, element isolation between bipolar transistors can be performed and a collector extraction electrode can be formed by a relatively simple process. Moreover, since the collector extraction electrode is formed in the oxide film for element isolation, the area required for element isolation and collector extraction electrode can be reduced, and the bipolar transistor can be highly integrated.

[Brief description of drawings]

FIG. 1 is a process sectional view (1) showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process sectional view (2) showing the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a process sectional view (3) showing the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a process sectional view (4) showing the method for manufacturing the semiconductor device according to the embodiment of the present invention.

[Explanation of symbols]

 10 ... P-type silicon substrate 12 ... Resist layers 14a, 14b ... N-type impurity region 16 ... Resist layer 18 ... P + type channel cut region 20 ... Silicon oxide film 22 ... Resist layers 24a, 24b ... Silicon layer 26 ... Silicon oxide film 28 ... Resist layer 30 ... Contact hole 32 ... Polycrystalline silicon layer 33 ... Collector extraction electrode 34 ... P-type base region 36 ... Polycrystalline silicon layer 38 ... Silicon oxide film 40 ... Resist layer 42 ... Contact hole 44 ... Sidewall 46 ... n-type emitter region 48 ... base electrode 50 ... emitter electrode 52 ... collector electrode

Claims (1)

[Claims] 1. A step of forming a second conductive type collector buried layer in an element region separated by an element isolation region on a first conductivity type silicon substrate, and a step of forming a second conductivity type collector buried layer on the element isolation region on the first conductivity type silicon substrate. Forming a first conductivity type channel cut region, forming a first silicon oxide film covering the element isolation region on the first conductivity type silicon substrate and a collector electrode formation region in the element region, Selectively epitaxially growing a silicon layer on the second conductive type collector buried layer in the device region where the first silicon oxide film is not formed; and covering the silicon layer and the first silicon oxide film. A step of depositing a second silicon oxide film, and removing the first silicon oxide film and the second silicon oxide film in the collector electrode region to remove the first silicon oxide film. Forming a contact hole reaching the second conductive type collector buried layer of the conductive type silicon substrate; and filling a polycrystalline silicon layer in the contact hole to form a collector extraction electrode reaching the second conductive type collector buried layer. Forming step, forming a first conductivity type base region on the surface of the silicon layer on the second conductivity type collector buried layer, and forming a second conductivity type emitter region in the first conductivity type base region. A method of manufacturing a semiconductor device, comprising: