JPH06205341A - Driving circuit for display device - Google Patents

Abstract

PURPOSE:To obtain the driving circuit for a display device in which degrading of display quality attended with a large sized display screen and high definition processing or the like is suppressed. CONSTITUTION:A deterioration correction circuit 8 adds signal voltages Va, Vb, Vc, Vd outputted from a signal voltage generating circuit 4 in the rising state through production of an overshoot thetaO and in the fall-down state, through production of an undershoot thetaU to obtain signal voltages VA, VB, VC,.VD respectively, which are fed to a source driver 2. The source driver 2 selects any of the plural signal voltages VA, VB, VC, VD based on digital video signals (Da, Db) and impresses the selected signal to each picture element. The converted signal voltages VA, VB, VC, VD are reached surely to an object voltage faster within the impressed period with the overshoot thetaO or the undershoot thetaU included in them.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit for a flat panel display device, and more particularly to a drive circuit for a matrix type liquid crystal display device which receives a digital video signal and performs gradation display according to the digital video signal. .

[0002]

2. Description of the Related Art Generally, a specific circuit diagram of a source driver 2 (FIG. 6) used in a matrix type liquid crystal display device will be described with reference to FIG. The source driver 2 is composed of m gradation selection circuits CL1, ..., CLi, ..., CLm equal to the number of pixels arranged on one horizontal scanning line, and m on one scanning line selected by a scanning signal. A drive voltage is supplied to each pixel. Here, for simplification, there are four types of gradation selection branches for each pixel, and four voltages Va, Vb, Vc are set.
, Vd, and in order to transmit gradation selection information for selecting this voltage, the first, ..., The i-th ,.
2-bit digital video data (Da1, Db1), ..., (Dai, Dbi), ..., (Da) corresponding to the m-th pixel
m, Dbm) are input to the decoders F1, ..., Fi, ..., Fm. These 2-bit digital video data are formed as follows.

First, a digital video signal Da is externally applied to an input terminal D of the sampling flip-flops SA1, ..., SAi, ..., SAm via a terminal t1. The sampling flip-flops SB1, ..., Through the terminal t2
A digital video signal Db is externally applied to the input terminals D of SBi, ..., SBm. The digital video signal Da includes digital video data Da1, ..., Dai, ..., Dam in time series, and the digital video signal Db includes the digital video data Db1, ..., Dbi, ..., Dbm in time series. There is.
The sampling clocks PS1, ..., PSi, ..., PSm are respectively supplied from the outside via terminals T1, ..., Ti, ..., Tm to sampling flip-flops (SA1, SB1),
..., (SAi, SBi), ..., (SAm, SBm) input terminal C
Given to K. Of these, for example, the sampling clock PSi rises during the period corresponding to the i-th pixel, so at this point the sampling flip-flop (SAi,
SBi) takes in the digital video signal (Da, Db) and holds it as the i-th digital video data (Dai, Dbi).

In other cases, this sampling operation is similarly performed in sequence, and the gradation selection circuits CL1, ..., CLi ,.
In each of CLm, sampling flip-flops (SA1, SB1), ..., (SAi, SBi) ,.
m, SBm) are digital video data (Da1, Db1), ..., (Dai, Dbi) ,.
Sampling of (Dam, Dbm) is completed.

At the end of the sampling operation, the output pulse PT is output through the terminal t3 to all hold flip-flops (HA1, HB1), ..., (HAi, HBi) ,.
Am, HBm) input terminals CK all at once. At this time, the sampling flip-flops (SA1, SB) in the previous stage
1), ..., (SAi, SBi), ..., All digital image data (Da1, Db1) held in (SAm, SBm),
, (Dai, Dbi), ..., (Dam, Dbm) are sampling flip-flops (SA1, SB1), ..., (SAi, S
Bi), ..., (SAm, SBm) output terminals Q, hold flip-flops (HA1, HB1), ..., (HAi, HB
i), ..., (HAm, HBm) are respectively transferred to the input terminals D and held. At the same time, the bit data Da1, ..., Dai, ..., Dam of the held digital video data
Hold flip-flops HA1, ..., HAi, ..., HAm
, Dbm of the digital image data held and output from the output terminal Q of the decoder F1, ..., Fi, ..., Fm to the input terminals A of the decoders F1 ,.
Hold flip-flops HB1, ..., HBi, ..., HBm
, F i, ..., F m of the decoders F 1, ..., F i ,.

On the other hand, the signal voltage generating circuit 4 shown in FIG. 6 sends four kinds of signal voltages (Va, Vb, Vc, Vd) through the terminals (t4, t5, t6, t7) to the analog switch (Xa).
1, Xb1, Xc1, Xd1), ..., (Xai, Xbi, Xci, Xd
i), ..., (Xam, Xbm, Xcm, Xdm).

Decoders F1, ..., Fi, ..., Fm are digital image data (Da1, Db1) ,.
Each bit of i, Dbi), ..., (Dam, Dbm) is decoded. Decoders F1, ..., Fi, ..., Fm are respectively connected from four output terminals (Y0, Y1, Y2, Y3) to analog switches (Xa1, Xb1, Xc1, Xd1) according to four combinations of the decoded values. ), ..., (Xai, Xbi, Xc
i, Xdi), ..., (Xam, Xbm, Xcm, Xdm) outputs signals to the switching terminals to switch only one of the four analog switches to the ON state. In this way, four kinds of signal voltages (Va, Vb, Vc) that determine the gradation are obtained.
, Vd) is selected and the output voltage O1
, ..., Oi, ..., Om as signal electrode lines Q1, ..., Qi
, ..., Qm, respectively. In addition to the method of selecting only one of the four analog switches to turn it on, it is possible to modify the circuit of FIG. 7 so as to select the on state of four digital switches in combination.

Next, FIG. 6 shows a schematic configuration diagram of a conventional matrix type liquid crystal display device which performs four kinds of gradation display according to a 2-bit digital video signal. In FIG. 6, 1 is a liquid crystal display panel in which m pixels horizontally and n pixels vertically are arranged in a matrix. A liquid crystal layer (not shown) is sandwiched between two glass substrates, and a transparent electrode film (not shown) common to all pixels is provided on the inner surface of one of the glass substrates. Voltage VCOM is applied. A transparent pixel electrode 7 is provided for each pixel on the inner surface of the other glass substrate and is connected to the drain of the TFT 6. The signal voltage generation circuit 4 has four different signal voltages Va, Vb and V.
c, Vd are generated and supplied to the source driver 2.

The source driver 2 is 4 as described above.
Any one of the different kinds of signal voltages Va, Vb, Vc, Vd is selected as the output voltage O1, ..., Oi, ..., Om as the applied voltage for each pixel electrode 7, and the signal electrode lines Q1 ,. , Qi, ..., Qm.

The gate driver 3 is provided for each scan electrode line P1,
, Pj, ..., Pn are sequentially supplied with on-pulses for one line period. As a result, all the TFTs 6 connected to the scan electrode line to which the on-pulse is applied are turned on during the pulse period. In this way, the signal electrode lines Q1, ..., Through the TFTs 6 in the ON state arranged on one scanning line,
, Qm apply output voltages O1, ..., Oi, ..., Om of the source driver 2 to the pixel electrodes 7 on the scanning lines. That is, from the source electrode Qi to the pixel electrode D
, (D, (i, 1), ..., D (i, j), ..., D (i, n) are sequentially applied with the output voltage Oi switched every one line period.

Here, for simplification, the output voltage Oi given from the gradation selection circuit CLi of the source driver 2 shown in FIG. 6 to the i-th source electrode Qi is equal to the signal voltage Vb shown in FIG. 3A. It is assumed to be a thing. Incidentally, Vx is the peak value of the signal voltage Vb.

The applied signal voltage Vb is applied to the pixel electrode D (i, 1) for one line period (1H in FIG. 5).
FIG. 5A shows a voltage waveform when the battery is charged during the period (1).
Similarly, FIGS. 5B and 5C respectively show the pixel electrode D.
6 shows voltage waveforms when (i, j) and D (i, n) are sequentially charged with the signal voltage Vb for one continuous line period.

[0013]

As can be seen from FIG. 5, when the signal voltage Vb is applied from the source driver 2 to the pixel electrode remote from the source driver 2, the impedance of the signal transmission path becomes large and the signal voltage Vb itself deteriorates. . In particular,
When applied to the farthest pixel electrode D (i, n), the signal voltage Vb itself is a voltage deterioration amount Δ as shown in FIG. 5C.
The peak value of the signal voltage that is deteriorated by V and is actually applied is VY
(VX> VY) Therefore, it is 1 for the far pixel electrode.
There is a problem that the charged voltage does not reach the peak value VX of the signal voltage Vb even after the passage of the line period (1H).

As described above, when the display panel 1 driven by the source driver 2 is increased in size and definition, the bus line resistance and the additional capacitance are increased, and the output impedance of the source driver 2, the impedance of the bus line, and the switching element. Since the impedance in the signal transmission path such as the on-resistance becomes large and the signal voltages Va, Vb, Vc, and Vd deteriorate, the required voltage cannot be applied to the display pixel and the display quality deteriorates.

The present invention has been made in view of the above problems, and provides a drive circuit of a display device capable of suppressing the deterioration of the display quality due to the increase in the size of the display screen and the increase in the definition. The purpose is to do.

[0016]

In order to achieve the above object, the drive circuit of the display device of the present invention reproduces an image by selecting a plurality of voltages prepared in advance by digital video signals and applying them to each pixel. The voltage is output in a pulse form, and means for generating an overshoot at the rising edge and an undershoot at the falling edge is provided.

Further, in this case, the level of the overshoot or the undershoot can be adjusted.

[0018]

By doing so, it is possible to reliably apply the selected signal voltage to any pixel regardless of the position of the pixel on the screen within the period in which the signal voltage is applied to each pixel without deterioration. You can

[0019]

The present invention will be described below with reference to the embodiments shown in the drawings. 1 and 2 show a driving circuit suitable for a matrix type liquid crystal display device.
It is said that four types of gradation display are performed according to a bit digital video signal. In FIG. 1, the signal voltages Va, Vb, Vc, and Vd output from the signal voltage generation circuit 4 are not directly applied to the source driver 2, but they are once applied to the deterioration correction circuit 8 and corrected respectively. The signal voltages VA, VB, VC and VD are applied to the source driver 2. Other than that point, it is the same as the conventional example shown and described in FIG. 6, and therefore those parts are denoted by the same reference numerals and the description thereof is omitted.

Next, the specific structure of the deterioration correction circuit 8 will be described by typifying the part related to the signal voltage Vb. In FIG. 2, which shows a circuit for correcting the signal voltage Vb, the + terminals (non-inverting input terminals) of the operational amplifiers 11 and 12 are grounded. One end of each of the resistors 14 and 16 has an operational amplifier 11,
12 is connected to the negative terminal (inverting input terminal) of each of the resistors 12, and the other ends of the resistors 14 and 16 are respectively connected to the operational amplifier 11 and
12 is connected to each output terminal. One end of the resistor 13 is connected to the input terminal 9, and the other end of the resistor 13 is connected to the-terminal of the operational amplifier 11. One end of the resistor 15 is connected to the output terminal of the operational amplifier 11, and the other end of the resistor 15 is connected to the-terminal of the operational amplifier 12. The output terminal of the operational amplifier 12 is connected to the output terminal 10 from which the corrected voltage VB is output. One end of the variable resistor 17 is connected to one end of the variable capacitor 18. The other end of the variable resistor 17 is connected to the connection line F between the resistor 15 and the operational amplifier 11, and the other end of the variable capacitor 18 is connected to the resistor 15
Is connected to the connection line G of the operational amplifier 12.

The signal voltage Vb from the signal voltage generating circuit 4 is applied to the input terminal 9. The resistors 13 and 14 have the same resistance value, and the resistors 15 and 16 have the same resistance value. Variable resistor 1
The resistance value of 7 and the capacitance of the variable capacitor 18 can be changed.

At this time, the waveform of the signal voltage Vb generated in the signal voltage generating circuit 4 and given to the input terminal 9 is shown in FIG.
FIG. 3B shows a waveform of the signal voltage VB shown in FIG. 2A and obtained from the output terminal 10 after being corrected by the correction circuit shown in FIG. Since the resistances of the resistors 13 and 14 are equal, the voltage VF of the connection line F is equal to (-1) times the signal voltage Vb.
It becomes Vb.

As shown in FIG. 3 (a), the signal voltage Vb rises at time a and falls at time a (the voltage VF falls at time a and rises at time a), but at this moment the variable capacitor 1
It can be considered that the impedance of 8 is absent. The resistance value of the resistors 15 and 16 is r, and the resistance value of the variable resistor 17 is r1. Since the combined resistance R of the resistance 15 and the variable resistance 17 is r.r1 / (r + r1), the voltage VF is multiplied by -r / R, that is,-(r + r1) by the operational amplifier 12.
/ R1 times amplified. Therefore, the signal voltage VB is given by the following equation. VB = VF * {-(r + r1) / r1} =-Vb * (-1-r / r1) = Vb + Vb * r / r1

Therefore, the signal voltage Vb becomes
At the moment when the voltage rises or falls, the signal voltage VB becomes a value obtained by adding the correction peak value amount VZ (= Vb × r / r1) to the signal voltage Vb as shown in FIG. 3B. Since this correction peak value amount VZ depends on the resistance value r1, it can be adjusted by changing the resistance value r1 of the variable resistor 17.

Further, θO shown as a shaded portion in FIG. 3 (b) is an overshoot in the one line period from the time a, and θU is an undershoot in the one line period from the time a. Overshoot θ
Regarding the adjustment of the correction amount Δθ (not shown) for O and the undershoot θU, the capacitance of the variable capacitor 18 can be changed.

The gate driver 3 uses the scanning electrode lines P1, ...
When the TFT 6 is turned on by the ON pulse sequentially output to Pj, ..., Pn from above, the source electrode Q
From i to the pixel electrodes D (i, 1), ..., D (i, j) ,.
The signal voltage VB is applied to D (i, n).

In the pixel electrode D (i, 1), the applied signal voltage VB is applied for one line period (1H in FIG. 4).
The voltage waveform during charging is shown in FIG. Similarly, FIGS. 4B and 4C respectively show the pixel electrode D.
(I, j) and D (i, n) show voltage waveforms when the applied signal voltage VB is charged for one line period.

As described above, when the signal voltage VB is applied from the source driver 2 to the pixel electrode remote from the source driver 2, the impedance of the signal transmission path becomes large, so that it is unavoidable that the signal voltage VB itself deteriorates. . However, in this case, the signal voltage VB has an overshoot θO added to the signal voltage Vb in the one-line period from the time A, and an undershoot θU added to the signal voltage Vb in the one-line period from the time A. ing.
Therefore, the signal voltage V is applied to the farthest pixel electrode D (i, n).
Even when B is applied, as shown in FIG. 4C, it converges to the peak value VX within one line period (1H), and charging can be performed quickly and surely.

The other signal voltages Va, Vc, and Vd are corrected by the circuit shown in FIG. 2 and supplied to the source driver 2 as the signal voltages VA, VC, and VD.

Also, in the present embodiment, an example of 4 gradations is shown as in the conventional example. However, if the number of bits of the digital video signal is n, the number of selectable gradations is given by "2 to the nth power". Therefore, the present invention can be applied even when the number of signal voltages to be supplied is increased more, as in the case of a matrix type liquid crystal display device having 8 gradations, 16 gradations, or the like.

[0031]

As described above, according to the drive circuit of the display device embodying the present invention, any pixel can be applied to any pixel within the period in which the signal voltage is applied to each pixel regardless of the position of the pixel on the screen. The selected signal voltage can be surely applied without deterioration. Therefore, it is possible to prevent the display quality from deteriorating due to the increase in the impedance of the signal transmission path accompanying the increase in size and definition of the display device, and it is possible to make the display quality uniform and high quality.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a matrix type liquid crystal display device embodying the present invention.

FIG. 2 is a circuit diagram of a deterioration correction circuit according to an embodiment of the present invention.

FIG. 3 is a waveform diagram of a signal voltage output by a signal voltage generation circuit and a deterioration correction circuit.

FIG. 4 is a diagram showing a voltage waveform when a signal voltage output from a deterioration correction circuit is applied to a pixel electrode.

FIG. 5 is a diagram showing a voltage waveform when a signal voltage output from a signal voltage generation circuit is applied to a pixel electrode.

FIG. 6 is a schematic configuration diagram of a conventional matrix type liquid crystal display device.

FIG. 7 is a circuit diagram of a source driver.

[Explanation of symbols]

1 display panel 2 source driver 3 gate driver 4 signal voltage generation circuit 5 terminal 6 TFT 7 pixel electrode 8 deterioration correction circuit 9 input terminal 10 output terminal 11 operational amplifier 12 operational amplifier 13 resistance 14 resistance 15 resistance 16 resistance 17 variable resistance 18 variable Capacitors Q1, ..., Qi, ..., Qm Source electrode lines P1, .., Pi, ..., Pn Scan electrode lines D (i, 1), ..., D (i, j), ..., D (i, n)
Pixel electrodes Da, Db Digital video signals (Da1, Db1), ..., (Dai, Dbi), ..., (Dam, D
bm) Digital video data CL1, ..., CLi, ..., CLm gradation selection circuit t1 to t7 terminals SAi, SBi sampling flip-flops (D, CK)
Input terminal Q output terminal) HAi, HBi hold flip-flop (D, CK input terminal Q output terminal) Di decoder (Ya, Yb, Yc, Yd output terminal) Xai, Xbi, Xci, Xdi Analog switch Va, Vb, Vc, Vd signal voltage O1, ..., Oi, ..., Om output voltage ΔV voltage degradation VX, VY peak value 1H 1 line period F, G connection line VF voltage VZ correction peak value amount θO overshoot θU undershooter, a time

Claims (2)

[Claims] 1. In a drive circuit of a display device for reproducing an image by selecting a plurality of voltages prepared in advance by a digital video signal and applying them to each pixel, the voltage is output in a pulse form, and when the voltage rises, an overvoltage occurs. A drive circuit for a display device, comprising a means for generating a shoot and an undershoot at the time of falling. 2. The drive circuit for a display device according to claim 1, wherein the level of the overshoot or the undershoot can be adjusted.