KR101903019B1 - Display Device for Compensating Resistance Non-Uniform in Connection Leads - Google Patents

Abstract

The present invention relates to a display device for compensating non-uniformity of wiring resistance by independently controlling output resistance for each channel in a driver chip to solve non-uniform charge problem between channels due to non-uniformity in length of a routing line connecting an active-matrix pixel array and a driver chip in a display panel. The display device includes a degeneration resistor connected in series with routing lines between a digital-to-analog converter included in a driver IC and an active-matrix column channel and compensating for different resistances of each of the routing lines to unify different resistances.

Description

[0001] The present invention relates to a display device for compensating resistance unevenness caused by channel wiring,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for compensating for uneven resistance due to a difference in length of a channel wiring of a display device, The present invention relates to a display device for compensating unevenness of wiring resistance by independently controlling an output resistance for each channel in a driver chip in order to solve the problem of non-uniform channel charging due to unevenness in length.

Flat panel displays using LCD (Liquid Crystal) or OLED (Organic Light Emitting Diode) are mainstream display technologies that play an important role in electronic devices such as smart phones, tablet computers, TVs and digital signage. One of the key technologies in the field of flat panel displays is the construction of an active-matrix pixel array comprising a matrix of large-area glass substrates. The luminance of each RGB pixel is independently determined by the analog voltage signal supplied from the driver chip of the external multi-channel column (source). Therefore, the routing line connecting the driver IC output and the active matrix column channel is located between the bonding pad of the driver IC and the active array.

)이 발생된다. 상이한 저항은 픽셀의 데이터 신호 구동의 충전 속도 오차에 상당한 영향을 미치므로 디스플레이 이미지 품질 저하를 야기한다. 충전 속도 오차는 exp[-

/

]로 정의 될 수 있으며, 여기서

는 1행 당 구동 시간이고,

은 구동 된 채널 라인의 모든 기생 RC 지연이다(

은

에도 포함됨). 서로 상이한

으로 인해 채널 간 충전 속도의 균일성을 보장 할 수 없으므로 도 1(a) 액티브 디스플레이 영역(Active Display Area)상에 나타난 바와 같이 그라데이션 패턴과 같은 고정적인 이미지 노이즈가 디스플레이 이미지에서 감지되는 경향이 발생된다.1 (a) is a schematic structure of a full-HD (1920x1080) resolution display panel. As shown, the Driver-to-Channel Routing Lines that are located at the top of the panel and that are patterned with routing lines are generally referred to as Bezel, which is the peripheral frame region. At this time, since the driver IC has a limited physical width, the distance of all the routing lines can not be the same. A routing line connecting to a channel located on a panel edge is formed to be relatively longer than a routing line connected to a column channel in the vicinity of the driver IC. Different lengths of the routing lines are clearly observed through the Full-HD display panel micrograph of FIG. 1 (b). If the lengths of the routing lines are different,

) Is generated. Different resistors significantly affect the charge rate error of driving the data signal of the pixel, resulting in display image quality degradation. The charging rate error is expressed as exp [-

/

], Where < RTI ID = 0.0 >

Is a driving time per row,

Is the total parasitic RC delay of the driven channel line (

silver

Also included). Different

The uniformity of the interchannel filling rate can not be guaranteed, so that a fixed image noise such as a gradation pattern is detected in the display image as shown in FIG. 1 (a) in the active display area (Active Display Area) .

문제를 완화하기 위해 디스플레이 프레임 속도를 줄이는 방법이 제안되었다(= 1 / [행의 수 /

]). 그러나 프레임 속도가 감소하면 빠르게 움직이는 비디오에서는 디스플레이에 운동 잔상이 발생된다.Such

A way to reduce the display frame rate to mitigate the problem has been proposed (= 1 / [number of rows /

]). However, as the frame rate decreases, fast moving video causes motion afterimage on the display.

)이 단축되고 있다. 장착 된 드라이버IC의 수를 줄이기 위해 단일 칩 드라이버의 단일 소스 출력은 기존의 1 행 선택 시간을 여러 시간 간격으로 나누어 다중 칼럼 채널(1 대 N 역 다중화)을 유도한다. 그러나 원칩 솔루션은 유효

를 단축 할뿐만 아니라 Δ

을 심각하게 악화시킨다.Also, with the recent introduction of one-chip driver solutions, the allowable driving time per row (

) Is shortened. To reduce the number of driver ICs installed, a single-chip driver's single-source output divides the existing one-row selection time into several time intervals to derive multiple column channels (one-to-N demultiplexing). However, the one-chip solution is valid

, As well as Δ

.

On the other hand, the number of driver ICs used in the one-chip driver solution is very limited, but the physical size and spatial resolution (number of columns) of the display panel is getting larger and larger. Therefore, the problem of non-uniform charging speed of flat panel displays is expected to become more serious in the future.

의 보상을 위해 지그재그(Zigzag) 배선 설계를 통해 라우팅 라인의 길이를 의도적으로 증가시키는 방법이 제안되었다. 이 지그재그형 배선은 라우팅 라인의 유효 길이를 가장 긴 라우팅 라인의 길이와 유사하도록 길게 만들어

의 불일치를 개선한다. 그러나 이 지그재그 배선 방법은 베젤 영역을 넓어지게 하는 문제가 있다. 상업용 시장에서 얇은 베젤을 갖는 디스플레이 제품에 대한 수요가 증가되고 있으므로, 베젤 두께가 증가되는 것은 바람직하지 않다. 또한, 지그재그 배선 접근법의 효과는 매우 제한 될 수 있다.2,

A method of intentionally increasing the length of the routing line through a zigzag wiring design has been proposed. This zigzag-shaped wiring makes the effective length of the routing line long so as to be similar to the length of the longest routing line

Lt; / RTI > However, this zigzag wiring method has a problem of widening the bezel area. As the demand for display products with thin bezels in the commercial market is increasing, increasing the thickness of the bezel is not desirable. Also, the effect of the zigzag wiring approach can be very limited.

32 " HD (1366 * 768) 40 " FHD (1920 * 1080) # of driver chips One chip Two chips Column (S / D layer)
라인 금속 재료 TiCu (600 nm thick) TiCu (500 nm thick) Line width of Chip-
to-kanal routing 6μm 5.2 m Bezel height
(routing-line area) 10 mm
with zigzag pattern 6 mm
with zigzag pattern

Δ1.5 kΩ
(= 1.8 kΩ - 0.3 kΩ) Δ1.6 kΩ
(= 1.8 kΩ - 0.2 kΩ) Parasitic RC
on column line 3 kΩ // 220 pF 3 kΩ // 300 pF 1-row selection period 3.6-μs (FR 120 Hz)
with 1: 3 DeMUX 2.6-μs (FR 120 Hz)
with 1: 3 DeMUX ΔCharging rate (%)
luminance difference 99% MIN - 97% MAX = 2% 93% MIN - 83% MAX = 10%

Table 1 shows some design examples of routing line and charge rate error calculations in the bezel region. The charge rate error < RTI ID = 0.0 > 1% < / RTI > was found to have a luminance error of 2.56 gray levels based on an 8 bit gray scale resolution.

)의 불일치로 인한 채널 간 불균일 충전 문제를 능동적으로 보완하기 위한 방법이 제안되어 있지 않다.Recent research on display driver ICs has shown that the routing line resistance

There is not proposed a method for actively supplementing the problem of non-uniform channel charge due to the mismatch between the channels.

Korean Patent Publication No. 10-1593099

It is therefore an object of the present invention to provide a display device for independently controlling an output resistance for each channel in a driver chip to compensate for unevenness in wiring resistance will be.

According to an aspect of the present invention, there is provided a display device for compensating resistance unevenness due to channel wiring, including a driver IC, an active matrix column channel, A display device comprising a plurality of routing lines for electrically connecting a matrix column channel, the display device comprising: a digital-to-analog converter included in the driver IC; and an active matrix column channel connected in series with the routing line, And further comprising a degeneration serial resistor for compensating for the different resistances of the plurality of transistors.

Further, the regenerative series resistance may be embedded in the output buffer amplifier of the driver IC.

In addition, the output serial buffer may include two output series buffers.

)은 수학식Further, the equivalent closed loop output resistance of the output buffer amplifier (

) ≪

는 피드백 루프 이득,

는 소형 신호 개방 루프 출력 저항,

은 트랜스컨덕턴스의 값,

는 퇴행직렬저항 값인 것을 특징으로 할 수 있다.Lt; RTI ID = 0.0 >

The feedback loop gain,

A small signal open loop output resistance,

The value of the transconductance,

Is a regression serial resistance value.

The output buffer amplifier may further include: a first MOSFET having a gate connected to the non-inverting signal input terminal and a source connected to the first regenerating series resistor, and a gate connected to the inverting signal input terminal, And a second MOSFET connected to the second degeneration series resistance.

The voltage at both ends of the first degeneration series resistor and the second degeneration series resistor may correct the unbalance of the source voltages of the first MOSFET and the second MOSFET to cancel the output offset dispersion.

According to the display device that compensates for the resistance unevenness due to the channel wiring according to the present invention,

First, each source driver channel independently compensates for variable routing line resistance to provide excellent charge rate uniformity.

Second, the RC delay on the channel-to-channel signal path becomes uniform, and the display frame rate can be greatly improved.

Thirdly, according to the driver structure of the present invention, the area of the bezel can be made smaller than that of wiring the routing lines in zigzags.

Fourth, since the amplifier of the present invention can calibrate the offset voltage dispersion between channels, the output voltage uniformity is greatly improved.

의 보상을 위해 지그재그(Zigzag) 배선 설계를 통해 라우팅 라인의 길이를 의도적으로 증가시킨 기술의 도면 및 야기된 충전 속도 오류 그래프를 나타낸 도면.
도 3은 본 발명의 실시예에 따른 출력 버퍼 증폭기를 나타낸 회로도.
도 4는 본 발명의 일 실시예에 따른 데이터를 픽셀로 제공하는 회로 모델.
도 5는 본 발명의 일 실시예가 적용되지 않은 경우(위)와 적용된 경우(아래)의 픽셀 전압을 시뮬레이션한 과도 응답 비교 그래프.
도 6는 본 발명의 일 실시예에 따른 퇴행직렬저항 및 트랜스컨덕턴스 컨트롤러가 내장된 출력 버퍼 증폭기의 회로도.
도 7은 공통 모드 입력 범위에서 일정한 트랜스컨덕턴스를 얻기 위한 트랜스컨덕턴스 제어 설계.
도 8은 본 발명의 일 실시예에 따른 N비트 디지털로 제어되는 퇴행직렬저항의 회로도.
도 9는 본 발명의 일 실시예에 따라 설계된 AM-OLED 소스 드라이버IC의 아키텍처.
도 10은 본 발명의 일 실시예에 따라 제작된 프로토타입 CMOS 소스 드라이버IC의 현미경 사진.
도 11은 본 발명의 일 실시예에 따라 제작된 프로토타입 드라이버IC 및 OLED 패널용 테스트 보드의 구성 사진.
도 12는 검정색에서 최대 밝기까지 측정 한 회색조 커브 그래프 : (a)감마 생략, (b) 비선형 감마 보정.
도 13은 5비트 퇴행직렬저항 제어 데이터를 스위핑하여 20pF 부하로 측정 한 출력 파형 그래프.
도 14는 프로토 타입 소스 드라이버IC를 사용하여 OLEO 패널에 표시된 화상 및 RGB 픽셀 사진.
도 15는 행 단위의 녹색 스트라이프를 구동하여 충전 속도에 따른 채널 간 휘도 균일도 측정 결과.
도 16은 퇴행직렬저항 제어에 의한 불균일 충전율 교정 프로세스의 순서도.
도 17은 320번째 행에서 프레임 레이트 편차를 갖는 소스 채널을 측정한 휘도 그래프.
도 18은 소스 드라이버 채널에서 측정된 출력 전압 그래프.
도 19는 240Hz의 프레임 속도로 재생된 데모 비디오의 사진.1 is a schematic structural drawing of a typical Full-HD (1920x1080) resolution display panel and a micrograph of a Full-HD display panel.
Fig.

Gt; FIG. 3 is a drawing of a technique and a diagram of a charge-rate error graph caused by intentionally increasing the length of a routing line through a zigzag wiring design for compensation of a charge of the device.
3 is a circuit diagram illustrating an output buffer amplifier according to an embodiment of the present invention.
4 is a circuit model that provides data as pixels in accordance with an embodiment of the present invention.
Figure 5 is a transient response comparison graph simulating pixel voltages when one embodiment of the present invention is not applied (above) and when applied (below).
FIG. 6 is a circuit diagram of an output buffer amplifier with built-in series resistance and transconductance controller according to an embodiment of the present invention. FIG.
7 is a transconductance control design for obtaining constant transconductance in a common mode input range.
8 is a circuit diagram of an N-bit digitally controlled retirement series resistor in accordance with one embodiment of the present invention.
Figure 9 is an architecture of an AM-OLED source driver IC designed in accordance with an embodiment of the present invention.
10 is a micrograph of a prototype CMOS source driver IC fabricated in accordance with an embodiment of the present invention.
11 is a photograph of a prototype driver IC and a test board for an OLED panel manufactured according to an embodiment of the present invention.
Figure 12 is a grayscale curve graph measured from black to full brightness: (a) Gamma omission, (b) non-linear gamma correction.
FIG. 13 is an output waveform graph measured with a 20 pF load by sweeping 5-bit regression serial resistance control data.
14 shows an image and an RGB pixel picture displayed on an OLEO panel using a prototype source driver IC.
FIG. 15 shows the result of measuring the luminance uniformity between channels according to the charging rate by driving the green stripe of each row.
16 is a flowchart of a non-uniform charge rate correction process by regression serial resistance control.
17 is a luminance graph in which a source channel having a frame rate deviation is measured in a 320 < th >
18 is a graph of the output voltage measured in the source driver channel.
Figure 19 is a photograph of a demo video played at a frame rate of 240 Hz;

A display device for compensating for resistance unevenness due to channel wiring according to embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It is to be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing. In the accompanying drawings, the dimensions of the structures are enlarged to illustrate the present invention, and are actually shown in a smaller scale than the actual dimensions in order to understand the schematic structure.

Also, the terms first and second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. On the other hand, unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

A display device for compensating for resistance unevenness due to channel wiring according to an embodiment of the present invention includes a driver IC, an active matrix column channel, a plurality of driver ICs, and a plurality of 1. A display device comprising a routing line, the display device comprising: a digital-to-analog converter (DAC) included in a driver IC; and a degeneration controller coupled in series with the routing line between the active matrix column channels to compensate for different resistances of each of the routing lines, And a series resistor.

In general, each source output channel of the driver IC is configured with serial input data, a digital-to-analog converter (DAC), and a digital circuit for processing the output buffer amplifier to drive the analog data voltage to a particular pixel of the active matrix.

) 퇴행직렬저항(degenerative series resistor;

)이 출력 버퍼 증폭기의 입력단에 내장된다. 차동 입력 쌍에

를 삽입하면 등가 트랜스컨덕턴스의 출력이

가 아닌 1/[1/

+

]가 된다. 피드백 루프 이득(

)이

/[1/

+

]와 같다고 가정하면,

는 소형 신호 개방 루프 출력 저항이 되고, 등가 폐 루프 출력 저항 (

)은 [식 1]과 같이 정의할 수 있다.Referring to Figure 3, the present invention provides a transconductance (< RTI ID = 0.0 >

) A degenerative series resistor;

) Is built into the input of the output buffer amplifier. On a differential input pair

The output of the equivalent transconductance becomes

1 / [1 /

+

]. Feedback loop gain (

)this

/[One/

+

],

Becomes a small signal open loop output resistance, and an equivalent closed loop output resistance (

) Can be defined as [Equation 1].

[Formula 1]

+

)로 등가 적으로 고려될 수 있다. 추가된

는 N비트 레지스터로 디지털 방식으로 제어가 가능하여, 이 가변직렬저항은

+

의 총 저항을 일관성 있게 유지하는 데 사용된다.Thus, the circuit resistance as an output buffer is (1/2) in the last signal path from the digital-to-

+

) Can be considered equivalently. Added

Can be digitally controlled with an N-bit register, and this variable series resistor

+

Lt; RTI ID = 0.0 > resistance. ≪ / RTI >

네트워크를 통해 대상 픽셀로 전송된다. 충전 속도의 채널 간 불균일성은 유리 베젤 영역에 패터닝 된 라우팅 라인의 유효 길이에 따른 저항(

)에서 발생된다.

보상을 하는 출력 버퍼는 등가 직렬로 연결된

[m] +

[m]이 일정한 값 (

)이 되도록 한다. 따라서, 채널별 라우팅 라인의 길이 변화에 관계없이 충전 속도를 정합시킬 수 있다.Figure 4 shows a simple circuit model in which a data signal is provided to a pixel in a digital-to-analog converter (DAC). The pixel voltage is first converted from digital data by a digital-to-analog converter (DAC) and driven by an output buffer. The voltage signal is the driver-channel routing line of the data line and the parasitic

And transmitted to the target pixel via the network. The interchannel non-uniformity of the filling rate depends on the effective length of the patterned routing line in the glass bezel region

).

The compensating output buffers are connected in an equivalent series

[m] +

[m] is a constant value (

). Therefore, the charging speed can be matched regardless of the change in the length of the routing line for each channel.

)를 [식 2]와 같이 정의할 수 있다.Using the Elmore RC delat model, the time constant of the entire signal path from the digital-to-analog converter to the pixel (

) Can be defined as [Equation 2].

[Formula 2]

는 출력 버퍼의 등가 출력 커패시턴스, N은 행의 수이다.

는

보다 매우 작다. [식 2]와 같이, 제어 가능한

를 직렬로 추가함으로써 변수

[m]이 상수 값(

)으로 대체되고, 따라서

을 차지하는 충전 속도가 칼럼 라인을 통해 신속히 안정화 된다.Where m is the source channel,

Is the equivalent output capacitance of the output buffer, and N is the number of rows.

The

Lt; / RTI > As shown in Equation 2,

Lt; RTI ID = 0.0 >

[m] is a constant value (

), And therefore

Is rapidly stabilized through the column line.

=25μS,

=0.4pF,

=93.8Ω,

=93.8fF,

=0-10kΩ,

=8μs의 조건으로 Δ4V의 단위 스텝 입력을 구동하여 픽셀 전압을 시뮬레이션한 과도 응답 비교 그래프를 나타낸다. 상측의 그래프는 본 발명이 적용되지 않은 것으로, 라우팅 라인 저항(

)으로 인해 픽셀로 구동되는 전압은 Δ30.5mV의 범위 내에서 편차가 발생된다. 반면, 본 발명의 일 실시예에 의한 출력 버퍼 증폭기가 적용된 디스플레이에서는

직렬 보상 (

=

+

)을 통해 전압 분산이 Δ0.7mV로 효과적으로 안정화 된다.Figure 5 shows N = 320 rows,

= 25 μS,

= 0.4 pF,

= 93.8?,

= 93.8fF,

= 0-10 kΩ,

= 8μs to drive a unit step input of Δ4V to simulate the pixel voltage. The graph on the upper side shows that the present invention is not applied, and the routing line resistance (

), The voltage driven by the pixel is varied within a range of? 30.5 mV. On the other hand, in the display to which the output buffer amplifier according to the embodiment of the present invention is applied

Serial compensation

=

+

), The voltage dispersion is effectively stabilized to? 0.7 mV.

Referring to FIG. 3, another advantage of the output buffer amplifier according to an embodiment of the present invention is output offset cancellation. The output buffer amplifier includes a first MOSFET having a gate connected to the noninverting signal input and a source connected to the first degenerating series resistor and a second MOSFET having a gate connected to the inverting signal input, And a second MOSFET connected thereto.

및

) 사이의 불일치는 출력 오프셋 확산과 치환된다. 일치하지 않는 제1 MOSFET(

) 및 제2 MOSFET(

) 전류에 의해 결정되는 제1퇴행직렬저항(

) 및 제2퇴행직렬저항(

) 양단의 전압은 제1 MOSFET(

) 및 제2 MOSFET(

) 소스 전압 간의 불균형을 수정한다. 따라서 차동 입력 쌍의 독립적으로 제어 가능한 제1퇴행직렬저항(

) 및 제2퇴행직렬저항(

)은 제1 MOSFET(

) 및 제2 MOSFET(

)가 일치하지 않아도 퇴행 피드백 메커니즘에 의해 평형 전류 분할을 안정화시킬 수 있게 된다. 이로 인해 채널 전반에 걸친 출력 오프셋 분산이 상쇄된다.Input-pair MOSFETs generated by process variations (

And

) Is replaced with the output offset spread. The mismatched first MOSFET (

) And the second MOSFET (

) ≪ / RTI > current) < RTI ID = 0.0 >

) And a second regression serial resistance (

) Is applied to the first MOSFET (

) And the second MOSFET (

) Correct the imbalance between source voltages. Thus, an independently controllable first degeneration serial resistor (< RTI ID = 0.0 >

) And a second regression serial resistance (

Is connected to the first MOSFET (

) And the second MOSFET (

), The balanced current division can be stabilized by the degeneration feedback mechanism. This offset the offset variance of the output across the channel.

Hereinafter, a display device according to an embodiment of the present invention will be described.

네트워크를 구동하는 데 사용된다. 또한, 출력 버퍼는 다수의 그레이 레벨(Gray-level)의 넓은 풀 스케일(Full-scale) 전압 범위를 수용하기 위해 거의 rail-to-rail 출력 전압 스윙을 제공해야한다. 본 발명의 일 실시예는 OLED 픽셀에서 P형 구동 박막 트랜지스터(TFT)의 소스 전압인

가 4.6V가 되도록 설계되었으므로 출력 버퍼는 5V의 전원 하에서 4.3V(black)에서 0.2V(full gray level)까지 구동될 수 있어야 한다.Referring to FIG. 6, the OLED output buffer is realized as an operational transconductance amplifier of unity-gain configuration, and a parasitic

Used to drive the network. In addition, the output buffer should provide near rail-to-rail output voltage swing to accommodate a large, full-scale voltage range of multiple gray-levels. One embodiment of the present invention relates to a method of driving a thin film transistor (TFT)

Is designed to be 4.6V, the output buffer must be able to drive from 4.3V (black) to 0.2V (full gray level) under a 5V supply.

)로 구성된다. 또한,

,

,

및

는 트랜스컨덕턴스 변성을 위해 각 입력 쌍 MOSFET의 소스에 삽입된다. 공통 모드 입력 전압 레벨에 관계없이 총 등가 트랜스컨덕턴스를 고정 할 수 있도록 MG1-MG8도 추가된다.The buffer amplifier circuit of this embodiment is designed based on an architecture that supports rail-to-rail operation. The amplifiers include input stages M1 to M9, folded-cascade summation stages M11 to M18, floating vias M20 to M23, output stages M24 to M25 and Miller capacitors

). Also,

,

,

And

Are inserted into the source of each input pair of MOSFETs for transconductance degeneration. MG1-MG8 is also added so that the total equivalent transconductance can be fixed regardless of the common mode input voltage level.

)가 공통 모드 입력 범위에서 2배 정도 변화되는 문제가 있다. 도 4를 참조하면, 트랜스컨덕턴스(

)의 변화는 의도된 라우팅 라인 보상에 반대된다. 도 7은 공통 모드 입력 범위에서 일정한 트랜스컨덕턴스를 얻기 위한 트랜스컨덕턴스 제어 설계이다. 공통 모드 입력 범위의 하단 및 상단 부분의 트랜스컨덕턴스(

)는 2배 증가되어야 한다. 이 설계에서는 입력 쌍 MOSFET 트랜지스터가 약한 반전 영역에서 동작하도록 설계되었으므로 테일 바이어스(tail bias) 전류를 2배 증가시킬 수 있다. 이 방법은 공통 모드 전압 검출기(MG1-MG8), 전류 스위치(M7, M10) 및 보조 테일 전류(

,

)를 통해 구현되었다. 낮은 공통 모드 입력 전압이 적용되면 P채널 입력-쌍(input-pair)(M3-M4) 만 작동한다. MG1-MG2가 이를 감지하면

신호는 보조 테일 전류

(=

)를 인가한다. 이것으로 PMOS 입력-쌍의 바이어스 전류에 두 개의 인자가 곱해진다. MG1-MG2의 낮은 공통 모드 전압 검출 점(

)은

과

사이의 비율을 설계함으로써 제어할 수 있는 점에서 유의할 수 있는데, 이는 실제로 CMOS 증폭기의 트리핑 포인트(tripping-point)를 결정한다. 공통 모드 입력 전압이 높으면 N채널 입력-쌍(M1-M2) 만 작동한다. MG5-MG6은 높은 공통 모드 전압을 감지하고 NMOS 입력-쌍의 바이어스 전류에

활성화를 곱한다. 높은 공통 모드 전압의 임계점(

)은 미리 설계된 CMOS 증폭기(MG5-MG6)의 트리핑 포인트에 의해 결정될 수 있다.N-channel and P-channel differential input pairs are placed in parallel to handle the common-mode input voltage on rail-to-rail. The N-channel input pair (M1-M2) can reach the positive supply rail while the P-channel input pair (M3-M4) reaches the ground rail. The rail-to-rail input stage uses transconductance (

) Is changed about twice in the common mode input range. Referring to Figure 4, the transconductance (

) Is contrary to the intended routing line compensation. Figure 7 is a transconductance control design for obtaining a constant transconductance in the common mode input range. Transconductance at the bottom and top of the common mode input range (

) Should be doubled. In this design, the input pair MOSFET transistors are designed to operate in the weak inversion region, which can double the tail bias current. This method includes the common mode voltage detectors (MG1-MG8), current switches (M7, M10) and auxiliary tail current

,

). When a low common-mode input voltage is applied, only the P-channel input-pair (M3-M4) operates. When MG1-MG2 detects this

The signal is an auxiliary tail current

(=

Is applied. This multiplies the bias current of the PMOS input-pair by two factors. The low common-mode voltage detection point of MG1-MG2

)silver

and

, Which in effect determines the tripping-point of the CMOS amplifier. If the common-mode input voltage is high, only the N-channel input-pair (M1-M2) will operate. The MG5-MG6 senses a high common-mode voltage and has a bias current of

Multiply activation. The critical point of the high common-mode voltage (

) Can be determined by the tripping point of the pre-designed CMOS amplifiers MG5-MG6.

-퇴행직렬저항(

) 회로의 일 실시예이다. 가변 저항 제어를 위해 바이너리 가중 저항기가 세그먼트(segment)화 되고, 스위치가 각 저항 세그먼트와 병렬로 배치된다.

의 총 저항은 MOSFET 스위치의 게이트에 연결된 N비트 디지털 데이터

<N-1:O>에 의해 제어되며, 디지털 데이터는 레지스터에서 레지스터로 직렬로 전송되며, 직렬로 연결된다.Figure 8

- Degenerate series resistance (

) Circuit. For variable resistance control, a binary weighted resistor is segmented and a switch is placed in parallel with each resistive segment.

Is the N-bit digital data connected to the gate of the MOSFET switch

<N-1: O>, and the digital data is serially transferred from the register to the register and serially connected.

)와,

및

입력을 갖는

로직 블록이 추가로 있다. 도 6의

-퇴행직렬저항(

)의 독특한 설계로 인해, 도 7의 일정한 트랜스컨덕턴스를 구현하려면 공통

를 공통 모드 입력 전압에 대응되게 조정해야 한다. 도 7에 따르면, 공통 모드 입력 전압(

)이

≤

≤

의 중간 범위 내에 있으면

에 2의 배수를 곱해야 한다. 이

조정은

논리 블록에 의해 실현되며,

=high 및

=Low 일 때 디지털 비트

를 1비트 좌방 이동(left-shifting)을 수행한다.

로직 블록을 사용함으로써 유효

는 더미 저항 세그먼트(

)의 결합으로 2배 증가될 수 있으며, 따라서 입력 공통 모드 전압 레벨에 관계없이 일정한 트랜스컨덕턴스가 실현된다.In addition, this embodiment uses a dummy resistive segment (

)Wow,

And

Having an input

There is an additional logic block. 6

- Degenerate series resistance (

), The constant transconductance of Figure 7 can be achieved by

Should be adjusted to correspond to the common mode input voltage. According to Fig. 7, the common mode input voltage (

)this

≤

≤

Is within the middle range of

Must be multiplied by a multiple of two. this

Adjustment

Realized by logic blocks,

= high and

= Low when digital bit

1-bit left-shifting.

Valid by using a logic block

Is a dummy resistor segment (

) So that a constant transconductance is realized regardless of the input common mode voltage level.

Figure 9 shows the overall architecture of an AM-OLED 240 channel source driver IC representing 16.7M color depth (8 bits per RGB signal) employing compensation for non-uniform routing line resistance. The sampling data latch receives one horizontal display data from the 24-bit RGB parallel interfacing block by a bidirectional shift register. In this design, the single-source output of the driver IC is responsible for the RGB multi-channel (1: 3 demultiplexing function), so each 24-bit pixel data is multiplexed into RGB and the multiplexed 8-bit data is stored in the RGB split holding latch. The pixel data is transferred to the digital-analog converter through the level shifter, and then the gradation voltage is selected from the 256 gradation voltages supplied from the resistor-string based on the pixel data. Finally, the analog gray voltage drives the pixels of the panel through the output buffer amplifier. The overall operation of the driver IC is under the control of the timing control signals DE, VSYNC, HSYNC and DCLK provided from the external host board.

-퇴행직렬저항(

)은

제어 레지스터에 의해 디지털 제어되며

제어 데이터 비트는

(inter-integrated circuit) 직렬 인터페이스 프로토콜을 통해 제어 레지스터로 흐른다.Built-in output buffer amplifier for compensation of non-uniform routing line resistance

- Degenerate series resistance (

)silver

Controlled by a control register

The control data bits

(inter-integrated circuit) serial interface protocol.

A prerequisite for ensuring high quality display is gamma correction. The driving voltage of the pixel is converted into the pixel current by the driving TFT of the pixel circuit, and the OLED luminance is determined by the converted pixel current. While the voltage is being converted to current, the TFT current may be a non-linear response to the driving voltage. Therefore, the gradation voltage must be adjusted to compensate for this nonlinearity before being displayed, and this process is called gamma correction. The gamma control block of the source driver IC acts as a gamma correction by providing a voltage tap on the resistor string, such as a segmented, piece-wise, linear structure.

Hereinafter, results of manufacturing and testing an embodiment of the present invention will be disclosed. Prototype AM-OLED source driver ICs with 240 output channels were fabricated with 0.18μm / 0.5μm CMOS technology and verified the functionality and performance of the proposed driver architecture using a non-uniform routing line compensator.

=4.6V 및

=-4.4V). 도 11은 프로토타입 드라이버IC 및 OLED 패널용 테스트 보드의 구성이다. 테스트 보드는 필요한 전력, 타이밍 제어 신호 및 CMOS 드라이버 칩에 대한 데이터 표시를 제공하고 OLED 패널에 행 라인 제어 신호 및 전원을 공급한다.10 is a micrograph of a CMOS chip of 15 mm (width) * 1.8 mm (height). Analog and digital circuits are designed to operate with 5V and 1.8V power supplies, respectively. The gray voltage generator uses a supply voltage of 5V and produces a source output range of 4.3V (black) to 0.2V (full-brightness), which is suitable for the voltage range of the target OLED panel

= 4.6 V and

= -4.4V). 11 shows a configuration of a prototype driver IC and a test board for an OLED panel. The test board provides the required power, timing control signals, and data display for the CMOS driver chip, and supplies line line control signals and power to the OLED panel.

An electrical test was performed to verify the functionality of the source driver. Figure 12 shows a waveform measuring 256 gray-levels based on 8-bit input data. As shown in FIG. 12 (a), the 8-bit digital-to-analog converter generates an accurate 256 gray level voltage from Black (4.3 V) to Full brightness (0.2 V) without gamma correction. With the non-linear gamma correction control, the 256 gray-voltage curve measured in Figure 12 (b) is observed to exhibit a non-linear shape, which is a nonlinear shape of the TFT in the pixel for linear control of the OLED luminance for the input data. Reflects the voltage-current conversion characteristic.

-퇴행 버퍼 증폭기(degenerative buffer amplifier)도 측정되었다. 도 13은

저항 스위프가 있는 소스 출력 채널의 측정 된 출력 파형을 나타낸다.

는 5비트 디지털 데이터인

<4:0>에 의해 제어되는 0 - 6.4kΩ 범위 내에서 가변적으로 설계되었다.

가 신호 충전 속도에 미치는 영향을 관찰하고, 전 범위 스윙 전압 출력(Δ4.1V)을 위해 흑백 입력을 교대로 적용하였다.

<4:0> = 0 조건에서 1-τ(63.2% 정확도) 안정화 시간은 20pF 부하에서 약 810ns로 측정되었다. 또한, 'Ox1F'에서

<4:0> 설정으로, 1-τ 안정화 시간은 약 945ns로 측정되었다. 이러한 측정 결과는

-퇴행 제어 기능이 있는 제안 된 버퍼 증폭기가 신호 충전 속도를 조정할 수 있는 충분한 능력을 가지고 있음을 보여 주며, 특히 고정되지 않은 라우팅 라인 저항에 의해 변동하기가 용이하다.To verify the compensation of mismatched routing line resistances

A degenerative buffer amplifier was also measured. Figure 13

Indicates the measured output waveform of the source output channel with resistive sweep.

Is a 5-bit digital data

It is designed to be variable within the range of 0 - 6.4kΩ controlled by <4: 0>.

Was observed and the black-and-white input was applied alternately for full-range swing voltage output (Δ4.1V).

The 1-τ (63.2% accuracy) stabilization time at <4: 0> = 0 conditions was measured at approximately 810 ns with a 20 pF load. Also, in 'Ox1F'

With the <4: 0> setting, the 1-τ stabilization time was measured at about 945 ns. These measurement results

- It shows that the proposed buffer amplifier with regression control has enough capacity to adjust the signal charge rate, especially it is easy to fluctuate by unfixed routing line resistance.

Display panel Active-Matrix Organic Light-Emitting Diodes
(AMOLED) with Low-Temperature Poly-Si
Thin-Film Transistors (LTPS-TFTs) Max. luminance 220 cd / m² Spatial resolution QVGA: 240 (W) * RGB * 320 (H) Panel size 2.4-inch Power supply

/

/

Driver-to-channel routing-line resistance (

) Shortest path: min. 3.1 kΩ
Longest path: max. 8.5 kΩ
(estimated values)

-퇴행 제어에 의해 Δ

=5.4kΩ을 보상해야 함을 알 수 있다. 도 14는 제조된 소스-드라이버 IC를 이용하여 OLED 패널 상에 표시된 그림(백색 패턴 및 라인 그리드 패턴)과, RGB 픽셀의 현미경 사진이다.Table 2 summarizes the technical parameters of the target OLED display panel used in the system of this embodiment. The active matrix backplane of the AM-OLED panel was fabricated on the basis of a low temperature polycrystalline silicon thin film transistor (LTPS-TFT). OLED panel size and spatial resolution are 2.4 inches and QVGA (240 x RGB columns and 320 rows) for low-cost mobile electronic devices. Through analysis of the patterned routing line design of the bezel, the effective resistances of the shortest path routing line and the longest path routing line are estimated to be 3.1 kΩ and 8.5 kΩ, respectively. Thus, the proposed source driver ICs are designed to achieve a uniform charge rate on the columns channel

- By the regression control,

= 5.4 kΩ should be compensated. Fig. 14 is a micrograph of the picture (white pattern and line grid pattern) and RGB pixels displayed on the OLED panel using the manufactured source-driver IC.

-퇴행 저항(

)의 보정 프로세스가 컬럼 채널에서 균일한 휘도로 수행된다. 도 16은 휘도 측정 및 보상 프로세스를 설명한다. 이 프로세스는 측정된 픽셀 휘도가 가장 긴 라우팅 라인을 통해 공급된 에지(Edge) 픽셀로부터 추출된 기준 휘도(

)와 같아지도록 각 소스 출력의

값을 조정한다.In order to measure the non-uniformity between channels due to the charging rate mismatch, green stripe image data was displayed in units of rows as shown in Fig. 15, and the luminance per pixel was measured at 320 rows. The reason for driving row-wise stripes is to create the most severe signal-charging conditions that are affected by the routing line resistance. After measuring the luminance,

- Degenerating resistance

) Is performed with a uniform luminance in the column channel. Figure 16 illustrates the luminance measurement and compensation process. This process is performed on the basis of the reference luminance extracted from the edge pixels supplied through the routing line having the longest measured pixel luminance

) Of each of the source outputs

Adjust the value.

시간으로 인해 휘도(충전 속도) 균일성에 대한 광범위한 왜곡이 발견되지 않았다. 국부적인 불균일은 소스 출력 오프셋의 확산, TFT 및 OLEO의 전기적 변형으로 인한 것으로 판단된다. 반면, 중간 그래프에 도시 된 바와 같이, 프레임 레이트가 240Hz로 증가 되면 휘도 균일성에 대한 광범위한 왜곡이 명확하게 관찰되었다. 휘도 편차는 σ=1.43%로 측정되었다. 높은 프레임 속도는 단축된

로 인해 충전 속도 불균일에 대해 라우팅 라인 저항 (

)의 영향이 더욱 악화되는 결과를 야기한다. 도 17의 하단 그래프는 도 16의

보정 프로세스 후의 측정 결과이다. 도시된 바와 같이, 휘도 균일성이 현저히 향상되었다. 측정된 휘도 편차는 240Hz의 높은 프레임 속도에도 불구하고 σ=1.01 %로 감소되었으며, 이 결과는 60Hz에서의 결과와 유사하다.17 shows the luminance obtained by measuring the source channel having the frame rate deviation in the 320th row. The upper graph of Figure 17 was measured under the conditions of a 60 Hz frame rate. Therefore,

No extensive distortion of luminance (charge rate) uniformity was found due to time. It is believed that the local unevenness is due to diffusion of the source output offset, electrical deformation of the TFT and OLEO. On the other hand, as shown in the middle graph, if the frame rate is increased to 240 Hz, a wide range of distortion for luminance uniformity is clearly observed. The luminance deviation was measured as σ = 1.43%. High frame rate is shortened

The routing line resistance (&lt; RTI ID = 0.0 &gt;

) Is more deteriorated. The lower graph of Fig.

And the measurement result after the correction process. As shown, the luminance uniformity is remarkably improved. The measured luminance deviation was reduced to σ = 1.01% despite the high frame rate of 240 Hz, which is similar to the result at 60 Hz.

-퇴행을 포함하는 버퍼 증폭기는 출력 오프셋 변동을 보정 할 수 있는 능력을 가지고 있다. 도 18은 프로토타입 드라이버IC의 소스 출력 채널에서 측정 된 출력 전압이다. 오프셋 보상 덕분에 측정된 출력 전압의 편차는 ±5mV에서 ±2.7mV로 크게 감소되었다.In this embodiment

Buffer amplifiers, including regression, have the ability to compensate for output offset variations. 18 is the output voltage measured at the source output channel of the prototype driver IC. Thanks to the offset compensation, the deviation of the measured output voltage was greatly reduced to ± 2.7 mV from ± 5 mV.

Figure 19 is a demo picture of video playback displayed on an OLEO panel at a frame rate of 240 Hz. This result shows that the proposed source driver IC and calibration technique successfully provided a very uniform OLEO display despite high frame rate conditions.

A 240-channel source driver IC that compensates for uneven routing line resistance has been designed and validated through chip manufacturing, measurement and display demos. Thanks to the active compensation method, the luminance uniformity and frame rate can be greatly improved.

The present invention is well suited for mobile or high capacity OLEO / LCD display applications with ultra slim bezel panels.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It is clear that the present invention can be suitably modified and applied in the same manner. Therefore, the above description does not limit the scope of the present invention, which is defined by the limitations of the following claims.

Claims (6)

1. A display device comprising a driver IC, an active matrix column channel, and a plurality of routing lines electrically connecting the driver IC to an active matrix column channel,
Further comprising a degeneration serial resistor coupled in series with the routing line between the digital-to-analog converter included in the driver IC and the active matrix column channel to compensate for different resistances of each of the routing lines to be unified,
The degenerate serial resistor is embedded in the output buffer amplifier of the driver IC,
Wherein the degenerate series resistance is comprised of two in the output buffer amplifier,
The output buffer amplifier comprising: a first MOSFET having a gate connected to a non-inverting signal input and a source connected to a first degeneration serial resistor; And a second MOSFET having a gate connected to the inverting signal input terminal and a source connected to the second regenerating series resistor. delete delete The method according to claim 1,
The equivalent closed loop output resistance of the output buffer amplifier (

) &Lt;

Lt; RTI ID = 0.0 &gt;

The feedback loop gain,

A small signal open loop output resistance,

The value of the transconductance,

Is a retrogressive series resistance value. delete The method according to claim 1,
Wherein the voltage at both ends of the first degeneration series resistor and the second degeneration series resistor corrects the imbalance of the source voltage of the first MOSFET and the second MOSFET to cancel the output offset dispersion. A display device for compensating for unevenness.

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