JP2983787B2 - Display device drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for a flat display device, and more particularly to a driving circuit for a matrix type liquid crystal display device to which a digital video signal is supplied and which performs gradation display according to the digital video signal. .

[0002]

2. Description of the Related Art Generally, a specific circuit diagram of a source driver 2 (FIG. 6) used in a matrix type liquid crystal display device will be described with reference to FIG. The source driver 2 includes m gradation selection circuits CL1,..., CLi,..., CLm equal to the number of pixels arranged on one horizontal scanning line. A driving voltage is supplied to the pixels. Here, for the sake of simplicity, there are four types of gradation selection branches of each pixel, and four voltages Va, Vb, Vc
,..., Vd, and the first,..., I-th,.
2-bit digital video data (Da1, Db1),..., (Dai, Dbi),..., (Da) corresponding to the m-th pixel.
, Dbm) are input to the decoders F1,..., Fi,. These 2-bit digital video data are formed as follows.

First, a digital video signal Da is externally supplied to input terminals D of sampling flip-flops SA1,..., SAi,. Through the terminal t2, the sampling flip-flop SB1,.
A digital video signal Db is externally supplied to input terminals D of SBi,..., SBm. The digital video signal Da includes digital video data Da1,..., Dai,..., Dam in a time series, and the digital video signal Db includes digital video data Db1,. I have.
Sampling clocks PS1,..., PSi,.
, (Sai, SBi), ..., (Sam, SBm) input terminal C
Given to K. Among them, for example, the sampling clock PSi rises during the period corresponding to the i-th pixel, and at this time, the sampling flip-flop (SAi,
SBi) takes in the digital video signal (Da, Db) and holds it as the i-th digital video data (Dai, Dbi).

In other cases, this sampling operation is similarly performed sequentially, and the gradation selection circuits CL1,..., CLi,.
In each of CLm, sampling flip-flops (SA1, SB1),..., (SAi, SBi),.
m, SBm) are digital video data (Da1, Db1),..., (Dai, Dbi),.
The sampling of (Dam, Dbm) is completed.

When the above sampling operation is completed, the output pulse PT is applied to all the hold flip-flops (HA1, HB1),..., (HAi, HBi),.
Am, HBm) at the same time. At this time, the sampling flip-flops (SA1, SB
1),..., (SAi, SBi),..., (Sam, SBm), all digital video data (Da1, Db1),
, (Dai, Dbi), ..., (Dam, Dbm) are sampling flip-flops (SA1, SB1), ..., (SAi, S
Bi),..., (Sam, SBm) from the output terminal Q, hold flip-flops (HA1, HB1),.
i),..., (HAm, HBm) are transferred to input terminals D and held. At the same time, the bit data Da1,..., Dai,.
Are the hold flip-flops HA1,..., HAi,.
, Dbi,..., Dbm are output to the input terminals A of the decoders F1,..., Fi,.
Are hold flip-flops HB1,..., HBi,.
, Fi,..., Fm are output from the output terminal Q of each of the decoders F1,.

On the other hand, the signal voltage generating circuit 4 shown in FIG. 6 applies four kinds of signal voltages (Va, Vb, Vc, Vd) via terminals (t4, t5, t6, t7) to an analog switch (Xa).
1, Xb1, Xc1, Xd1),..., (Xai, Xbi, Xci, Xd
i), ..., (Xam, Xbm, Xcm, Xdm).

The decoders F1,..., Fi,..., Fm are digital video data (Da1, Db1),.
i, Dbi),..., (Dam, Dbm). In accordance with the four combinations of the decoded values, the decoders F1,..., Fi,. ), ..., (Xai, Xbi, Xc
i, Xdi),..., (Xam, Xbm, Xcm, Xdm), and outputs a signal to switch on only one of the four analog switches. In this way, the four signal voltages (Va, Vb, Vc) for determining the gradation
, Vd) and the output voltage O1
,..., Oi,..., Om as signal electrode lines Q1,.
,..., Qm. In addition to the method in which only one of the four analog switches is selected and turned on, the circuit shown in FIG. 7 can be modified so that the on states of the four digital switches are selected in combination.

Next, FIG. 6 shows a schematic configuration diagram of a conventional matrix type liquid crystal display device which performs four types of gradation display according to a 2-bit digital video signal. In FIG. 6, reference numeral 1 denotes a liquid crystal display panel in which m pixels horizontally and n pixels vertically are arranged in a matrix. A liquid crystal layer (not shown) is sandwiched between two glass substrates, and a transparent electrode film (not shown) common to all pixels is provided on the inner surface of one of the glass substrates. Is applied. A transparent pixel electrode 7 is provided for each pixel on the inner surface of the other glass substrate, and is connected to the drain of the TFT 6. The signal voltage generation circuit 4 has four different signal voltages Va, Vb, V
c and Vd are supplied to the source driver 2.

[0009] The source driver 2
Any one of the different signal voltages Va, Vb, Vc, Vd is selected as an output voltage O1,..., Oi,..., Om as an applied voltage for each pixel electrode 7, and the signal electrode lines Q1,. , Qi,..., Qm.

The gate driver 3 is connected to each scanning electrode line P1,
, Pj,..., Pn are sequentially supplied with an ON pulse for one line period. As a result, all the TFTs 6 connected to the scan electrode lines to which the on-pulse is applied are turned on during the pulse period. Thus, the signal electrode lines Q1,...,.
The output voltages O1,..., Oi,..., Om of the source driver 2 are applied to the pixel electrodes 7 on the scanning line from Qi,. That is, from the source electrode Qi to the pixel electrode D
, D (i, j),..., D (i, n) are sequentially applied with the output voltage Oi that is switched every line period.

Here, for simplicity, the output voltage Oi applied to the i-th source electrode Qi from the gradation selection circuit CLi of the source driver 2 shown in FIG. 6 is equal to the signal voltage Vb shown in FIG. It is assumed that Vx is the peak value of the signal voltage Vb.

The applied signal voltage Vb is applied to the pixel electrode D (i, 1) for one line period (1H in FIG. 5).
FIG. 5A shows a voltage waveform when charging is performed during the period of FIG.
Similarly, FIGS. 5B and 5C respectively show the pixel electrode D
It shows a voltage waveform when (i, j) and D (i, n) are charged with the signal voltage Vb sequentially for one successive line period.

[0013]

As can be seen from FIG. 5, when the signal voltage Vb is applied from the source driver 2 to a pixel electrode remote from the source driver 2, the impedance of the signal transmission path increases, so that the signal voltage Vb itself deteriorates. . Especially,
When applied to the farthest pixel electrode D (i, n), as shown in FIG. 5C, the signal voltage Vb itself becomes the voltage degradation Δ
Degrades by V and the peak value of the actually applied signal voltage is VY
(VX> VY). Therefore, 1 in the distant pixel electrode.
Even if the line period (1H) elapses, there occurs a problem that the charged voltage does not reach the peak value VX of the signal voltage Vb.

When the display panel 1 driven by the source driver 2 is increased in size and definition as described above, the bus line resistance and additional capacitance increase, and the output impedance of the source driver 2, the impedance of the bus line, and the switching element Since the impedance in the signal transmission path such as the on-resistance increases and the signal voltages Va, Vb, Vc, and Vd deteriorate, the required voltage cannot be applied to the display pixels, thereby deteriorating the display quality.

The present invention has been made in view of such a problem, and provides a drive circuit of a display device capable of suppressing a decrease in display quality due to an increase in the size of a display screen and an increase in definition. The purpose is to do.

[0016]

In order to achieve the above object, a driving circuit for a display device according to the present invention reproduces an image by selecting a plurality of voltages prepared in advance by a digital video signal and applying the selected voltages to each pixel. Wherein the voltage is output in a pulsed form, and a means for generating an overshoot at the rise and an undershoot at the fall is provided.

Further, in this case, the level of the overshoot or the undershoot can be adjusted.

[0018]

In this manner, during the period in which the signal voltage is applied to each pixel, the selected signal voltage can be reliably applied to any pixel regardless of the position of the pixel without deteriorating. Can be.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to an embodiment shown in the drawings. FIGS. 1 and 2 show a driving circuit suitable for a matrix type liquid crystal display device.
It is described that four types of gradation display are performed according to a bit digital video signal. In FIG. 1, the signal voltages Va, Vb, Vc, and Vd output from the signal voltage generation circuit 4 are not directly applied to the source driver 2, but are applied once to the deterioration correction circuit 8 and corrected respectively. The signal voltages VA, VB, VC, VD are supplied to the source driver 2. The other points are the same as those of the conventional example shown and described with reference to FIG.

Next, a specific configuration of the deterioration correction circuit 8 will be described by exemplifying a portion relating to the signal voltage Vb. In FIG. 2 showing a circuit for correcting the signal voltage Vb, the + terminals (non-inverting input terminals) of the operational amplifiers 11 and 12 are grounded. One ends of the resistors 14 and 16 are connected to the operational amplifier 11 and
12 are connected to the respective-terminals (inverting input terminals), and the other ends of the resistors 14, 16 are connected to the operational amplifier 11,
12 are connected to respective output terminals. One end of the resistor 13 is connected to the input terminal 9, and the other end of the resistor 13 is connected to the − terminal of the operational amplifier 11. One end of the resistor 15 is connected to the output terminal of the operational amplifier 11, and the other end of the resistor 15 is connected to the − terminal of the operational amplifier 12. The output terminal of the operational amplifier 12 is connected to the output terminal 10 from which the corrected voltage VB is output. One end of the variable resistor 17 is connected to one end of the variable capacitor 18. The other end of the variable resistor 17 is connected to the connection line F between the resistor 15 and the operational amplifier 11, and the other end of the variable capacitor 18 is connected to the resistor 15
And the connection line G of the operational amplifier 12.

A signal voltage Vb is applied to the input terminal 9 from the signal voltage generation circuit 4. The resistances of the resistors 13 and 14 are equal, and the resistances of the resistors 15 and 16 are equal. Variable resistor 1
7 and the capacity of the variable capacitor 18 can be changed.

At this time, the waveform of signal voltage Vb generated in signal voltage generating circuit 4 and applied to input terminal 9 is shown in FIG.
FIG. 3A shows the waveform of the signal voltage VB obtained from the output terminal 10 corrected by the correction circuit shown in FIG. Since the resistance values of the resistor 13 and the resistor 14 are equal, the voltage VF of the connection line F is equal to (-1) times the signal voltage Vb and −
Vb.

As shown in FIG. 3A, the signal voltage Vb rises at time A and falls at time A (the voltage VF falls at time A and rises at time A).
It can be considered that there is no impedance of 8. The resistance of the resistors 15 and 16 is represented by r, and the resistance of the variable resistor 17 is represented by r1. Since the combined resistance R of the resistor 15 and the variable resistor 17 is r.r1 / (r + r1), the voltage VF is multiplied by the operational amplifier 12 by -r / R, that is,-(r + r1).
/ R1 times. Therefore, the signal voltage VB is given by the following equation. VB = VF × {− (r + r1) / r1} = − Vb × (−1−r / r1) = Vb + Vb × r / r1

Accordingly, the signal voltage Vb as shown at time A and time A
At the moment when the signal rises or falls, the signal voltage VB becomes a value obtained by further adding the correction peak value VZ (= Vb × r / r1) to the signal voltage Vb as shown in FIG. 3 (b). Since the corrected peak value VZ depends on the resistance value r1, it can be adjusted by changing the resistance value r1 of the variable resistor 17.

In FIG. 3B, .theta.O shown as a hatched portion is an overshoot in one line period from time A, and .theta.U is an undershoot in one line period from time A. Overshoot θ
O, the correction amount Δθ (not shown) of the undershoot θU can be adjusted by changing the capacitance of the variable capacitor 18.

The gate driver 3 scans the scanning electrode lines P1,.
When the TFT 6 is turned on by an on pulse sequentially output from above to Pj,..., Pn, the source electrode Q
, D (i, 1),..., D (i, j),.
The signal voltage VB is applied to D (i, n).

In the pixel electrode D (i, 1), the applied signal voltage VB is applied for one line period (1H in FIG. 4).
FIG. 4A shows a voltage waveform during charging. Similarly, FIGS. 4B and 4C respectively show the pixel electrode D
(I, j) and D (i, n) show voltage waveforms when the applied signal voltage VB is charged for one line period.

As described above, when the signal voltage VB is applied from the source driver 2 to the pixel electrode remote from the source driver 2, the impedance of the signal transmission path increases, so that it is impossible to avoid the signal voltage VB itself from deteriorating. . However, in this case, the signal voltage VB has an overshoot θO added to the signal voltage Vb in one line period from time A, and the undershoot θU has been added to the signal voltage Vb in one line period from time A. ing.
Therefore, the signal voltage V is applied to the farthest pixel electrode D (i, n).
Even when B is applied, it converges to the peak value VX within one line period (1H) as shown in FIG.

The same effect can be obtained if the other signal voltages Va, Vc and Vd are corrected by the circuit shown in FIG. 2 and supplied to the source driver 2 as the signal voltages VA, VC and VD.

In this embodiment, an example of four gradations is shown as in the conventional example. However, when the number of bits of the digital video signal is n, the number of selectable gradation types is given by "2 to the power of n". Therefore, the present invention can be applied to a case where the number of signal voltages to be supplied is increased more, such as a matrix type liquid crystal display device having 8 gradations or 16 gradations.

[0031]

As described above, according to the drive circuit of the display device embodying the present invention, any pixel can be applied to any pixel within the period of applying the signal voltage to each pixel regardless of the position of the pixel on the screen. In addition, it is possible to reliably apply the selected signal voltage without deterioration. Therefore, it is possible to prevent a decrease in display quality due to an increase in impedance of a signal transmission path due to an increase in size and definition of the display device, and it is possible to make display quality uniform and high quality.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a matrix type liquid crystal display device embodying the present invention.

FIG. 2 is a circuit diagram of a deterioration correction circuit according to the embodiment of the present invention.

FIG. 3 is a waveform diagram of a signal voltage output by a signal voltage generation circuit and a deterioration correction circuit.

FIG. 4 is a diagram illustrating a voltage waveform when a signal voltage output from a deterioration correction circuit is applied to a pixel electrode.

FIG. 5 is a diagram showing a voltage waveform when a signal voltage output from a signal voltage generation circuit is applied to a pixel electrode.

FIG. 6 is a schematic configuration diagram of a conventional matrix type liquid crystal display device.

FIG. 7 is a circuit diagram of a source driver.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Display panel 2 Source driver 3 Gate driver 4 Signal voltage generation circuit 5 Terminal 6 TFT 7 Pixel electrode 8 Deterioration correction circuit 9 Input terminal 10 Output terminal 11 Operational amplifier 12 Operational amplifier 13 Resistance 14 Resistance 15 Resistance 16 Resistance 17 Variable resistance 18 Variable Capacitors Q1, ..., Qi, ..., Qm Source electrode lines P1, ..., Pi, ..., Pn scanning electrode lines D (i, 1), ..., D (i, j), ..., D (i, n)
Pixel electrode Da, Db Digital video signal (Da1, Db1), ..., (Dai, Dbi), ..., (Dam, D
bm) Digital video data CL1,..., CLi,..., CLm gradation selection circuit t1 to t7 Terminals SAi, SBi Sampling flip-flops (D, CK)
Input terminal Q output terminal HAi, HBi Hold flip-flop (D, CK input terminal Q output terminal) Di decoder (Ya, Yb, Yc, Yd output terminal) Xai, Xbi, Xci, Xdi Analog switch Va, Vb, Vc, Vd signal voltage O1,..., Oi,..., Om Output voltage ΔV Voltage degradation VX, VY Peak value 1H 1 line period F, G connection line VF voltage VZ Correction peak value θO Overshoot θU Undershoot A, A

Claims (2)

(57) [Claims] 1. A driving circuit of a display device for reproducing an image by selecting a plurality of voltages prepared in advance by a digital video signal and applying the selected voltages to each pixel, wherein the voltages are output in a pulsed form, and the voltages are output at the rising edge. A driving circuit for a display device, comprising means for generating a shoot and generating an undershoot at the time of a fall. 2. The drive circuit according to claim 1, wherein a level of the overshoot or the undershoot can be adjusted.