JP2659553B2 - Method and system for eliminating crosstalk in thin film transistor matrix-addressed liquid crystal displays - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates generally to a method and apparatus for eliminating crosstalk in a liquid crystal display device. The method can be applied to bi-state display devices and intermediate gray level display devices. More particularly, the present invention relates to a display device provided with means for preventing crosstalk between data lines and pixels.

The present invention can be better understood by understanding the operation of liquid crystal display devices and the problem of parasitic capacitance inherent in the structure of these devices. In particular, liquid crystal display devices typically have a pair of substrates, which are fixed at a specific distance. This distance is typically about 6 microns. The liquid crystal material is disposed between the substrates. The substrate is selected so that at least one is transparent. Both substrates need to be substantially transparent if illumination is provided from the back side as a means of enhancing the display and the image. Disposed on one of these substrates is a transparent ground plane conductor, typically made of a material such as indium tin oxide (ITO). The opposing substrate is provided with individual electrode elements arranged in a rectangular shape called pixel electrodes. A semiconductor switch (preferably, a thin film transistor) is attached to each of these pixel electrodes, and is typically located on a substrate containing these electrodes. These transistor switches are usually based on amorphous silicon or polysilicon technology. At present, amorphous silicon technology is preferred due to its low processing temperature. In fact, the above-described structure becomes a circuit element such as a rectangular array of capacitors, where the liquid crystal material acts as a dielectric. By applying a voltage to the pixel electrode, an electro-optical conversion occurs in the liquid crystal material. This conversion is the basis for displaying textual or graphical information that can be viewed on a display device. Here, the present invention is described above because each pixel electrode is provided with its own semiconductor switch that can be turned on and off, and each pixel element is controlled by a signal supplied to its associated semiconductor switch. It should be noted that the present invention is particularly applicable to such a display device. These semiconductor elements essentially deposit charge on individual pixel electrodes and act as electronic valves.

Each transistor is supplied with a scanning line signal and a data line signal. Generally, there are M data lines and N data lines. Typically, each transistor switch has its gate connected to a scan line and its source or drain connected to a data line.

In operation, a signal level is set for each of the M data lines. At this point, when one of the N scanning lines is activated, the voltage appearing on the data line is supplied to the pixel electrode via the semiconductor switching element. In the configuration described above, each pixel is inevitably surrounded by the data lines on both sides. That is, the data line on one side of each pixel is the data line associated with that pixel electrode, while the other data line is associated with the adjacent pixel electrode. This latter data line carries different information signals. Also, a unique capacitance is formed in this structure. In particular, the pixel electrode and the opposing ground plane electrode portion form a capacitance structure. Further, there is a parasitic capacitance between each data line and a pixel electrode element surrounded by the data line. In addition, a parasitic capacitance exists between the source and the drain of the semiconductor switch element. Undesired signals are supplied to the pixel electrodes due to the parasitic capacitance.

In a typical operation sequence, the desired voltage levels are set on the data lines and the scan lines bring these voltages to one.
It is operated to apply to a row of pixel electrodes. After sufficient time to charge the LC capacitor, different scan lines are activated and different data voltages are applied to different pixel rows. Typically, adjacent rows of pixels are selected for writing video information. Thus, in a typical operation, lines are written one line at a time from the top to the bottom of the display device screen. When applied to a television, this write operation from top to bottom takes about one second.
Occurs at 1/30 or 1/60. Thus, in this cycle, a complete image is displayed on the screen. This image may contain both text and graphic information.

As is well known in the electrical arts, capacitance is generally proportional to area and inversely proportional to distance. In a high-resolution liquid crystal display device, the parasitic capacitance effect is not particularly preferable because the distance between lines is reduced. In a typical application, such as the television considered here, the pixel electrodes are about 100 microns on a side, separated by about 10 microns, and an area of about 10 × 10 microns is used to replace the associated semiconductor switch element. Excluded from each pixel for placement. As described above, in the thin film transistor matrix address type high resolution liquid crystal display, the parasitic capacitance between the data line and the pixel electrode is more important than the pixel capacitance. Also, note that the parasitic capacitance between the data line and the pixel electrode increases due to the parasitic capacitance between the source and the drain of the switch element itself. In operation of such a display, the voltage on a pixel is set during that row address time. The semiconductor switch is then turned off and the voltage must remain constant until the display is refreshed. However, when the voltage of the adjacent data line changes, the voltage of the pixel changes. In many drive circuits, the data line
The RMS voltage typically varies between 0 and 5 volts depending on how many switching elements in the column are turned on. As a result, the voltage on the pixel becomes indeterminate, that is, crosstalk occurs in the voltage on the pixel. The maximum value of this voltage is 2 * [(C _D + C _SD ) / C _LC ] * 5
It is a bolt. Here, C _D is the parasitic capacitance caused by proximity between the data line and the pixel electrode, C _SD is the parasitic capacitance of the source and drain of the switch, the C _LC is the capacitance associated with the liquid crystal cell structure itself . The factor of 2 is due to the presence of two data lines adjacent to each pixel electrode. In a design with about 100 pixels per inch, the maximum voltage error is about 0.2 RMS volts. This is not critical for on-off displays, but is important for gray-scale displays that have a visible RMS voltage change of 0.05 volts.

One way to reduce the above types of crosstalk is to
It is to use a storage capacitor in parallel with C _LC. This reduces the maximum error voltage. However, this method is not preferred because it usually requires extra processing steps, creates another drawback and reduces the active area of the pixel elements.

In accordance with a preferred aspect of the present invention, a matrix-addressed liquid crystal display device having means for sequentially providing an energizing signal on a scan line also has means for providing a plurality of data signals on a data line. . In the present invention, these data signals operate during a period of successively generated scan line activation signals during which a desired voltage level is applied to the data lines during a first portion. . In the second part of this period, a correction voltage level is applied to the data lines to provide a substantially constant RMS throughout these periods.
A voltage is provided to at least some of these data lines. According to another aspect of the invention, the liquid crystal display is operated to achieve this constant RMS voltage. According to another aspect of the invention, multiple scan line periods are allowed to elapse before providing a correction voltage level to re-achieve a substantially constant RMS voltage over a particular period. Operating the liquid crystal display in this manner eliminates the uncertainty of the voltage on the pixel element caused by the parasitic capacitance between the data line and the pixel electrode. Several means to achieve these results are provided here.

Accordingly, it is an object of the present invention to eliminate crosstalk caused by parasitic capacitance in a thin film transistor matrix-addressed liquid crystal display device.

It is another object of the present invention to provide a method and means for operating a liquid crystal display device to achieve a substantially constant RMS voltage data line waveform.

Yet another object of the invention is to drive a liquid crystal display such that the voltage induced on the pixel electrode by the parasitic capacitance is the same for all pixel elements, especially all pixel elements in one column. It is in.

It is yet another object of the present invention to provide a constant shift that is used to compensate by appropriately additional adjusting the data voltage to reduce uncertainties in pixel voltage levels.

It is another object of the present invention to improve the operation of gray scale and non-gray scale liquid crystal display devices.

Still another object of the present invention is to eliminate crosstalk in a liquid crystal display device.

While the subject matter of the invention is particularly pointed out in the appended claims, the invention will be best understood from the following description, taken in conjunction with the accompanying drawings, when read in connection with the structure and manner of implementation and other objects and advantages of the invention.

DETAILED DESCRIPTION OF THE INVENTION FIG. 1 shows an overall view of a liquid crystal display device 10. The main component of the device is an array 20 of individually controllable pixel elements. Typically, the array is configured in a rectangular grid, with each grid location provided with a transparent pixel electrode and its associated semiconductor switch;
This semiconductor switch has a function of supplying a voltage to an associated pixel electrode. Typically, there are as many semiconductor switches as pixel electrodes. Note, however, that this is not required for the operation of the present invention. Also, the pixel array is generally set in a rectangular grid,
The present invention is not limited to this structure. For convenience of explanation and understanding, it is assumed that the pixel array 20 is a rectangular pixel array composed of M columns and N rows. Data driver 30 is provided with serial data representing video information in analog or digital form. Appropriate timing for data driver 30 is provided using a pixel clock that typically occurs at M times the frequency of the scan line clock shown. Data driver 30 typically has M output lines. These M data lines are typically all valid at a particular point in time. That is, the scan driver 40 activates a semiconductor switch (for example, provided at the intersection of the m-th data line and the n-th scan line) under the control of the scan line clock signal, and applies a signal to one row of pixel electrodes. Data from M data lines can be supplied at one time. Therefore, it can be seen that there is a line from the scan driver for each row of the pixel array 20. Therefore, in general, scan drivers
There are 40 to N output lines (scan lines).

The particular problem caused by the configuration of the pixel and data electrodes is illustrated in more detail in FIG.

In particular, attention is paid to pixel electrodes associated with the m-th data line and the n-th scanning line. Here, the pixel electrode
Note that the capacitive circuit element _CLC is present as a result of the presence of the ground plane electrode portion (not shown) and associated liquid crystal material (not shown) opposite 21. Further, in FIG. 2 is shown in relation to the switching element 25 is a parasitic capacitance C _SD between the source and drain. Further, in FIG. 2 there is shown a parasitic capacitance C _D that exists between the pixel electrode 21 shown with the m-th data lines. (Other pixel electrodes are shown but not numbered). Further, it should be noted that the parasitic capacitance exists between the pixel electrode 21 and the data line (m + 1) shown on the right side thereof. However,
The capacity shall be taken into account in the determination of the capacitance value of its associated C _D. The capacitor C _D and the capacitor C _SD is virtually parallel, it should be noted that their capacity is added. Further, it can be seen that the data lines are indicated by reference numeral 24 and the scan lines are also indicated by reference numeral 22.

Next, the problem to be solved by the present invention will be considered by analyzing FIG. 2 more completely. In particular, considering the pixel electrode 21, the voltage signal generated on the data line (m + 1) is the voltage signal existing as a result of the pixel electrode 21 and the data line (m + 1) being necessarily very close to each other. (M +
The voltage is applied to the pixel electrode 21 by the capacitive coupling (not shown) of 1). Similarly, since the parasitic capacitance _CSD acts to couple the data line m to the pixel electrode 21, the semiconductor switch
Even if 25 is off, the signal supplied to the data line m also appears on the pixel electrode 21. For the same reason as the pixel electrode 21 is coupled to the data line (m + 1), via the C _D it is capacitively coupled to the data line m. The spurious signal remains in row n even when the information is being supplied to another row, for example the row associated with scan line (n + 1) or (n + 2).
May be applied. This is the problem that the present invention seeks to improve. In the figure, the parasitic capacitance is shown only for the cell in row n and column m, but these are also present in all the pixel cells. However, here, only one cell described above is considered for illustration.

A method for solving the above-described crosstalk problem is illustrated in FIG. In particular, the first waveform shown here illustrates two ways to solve the problem. Periods T ₁ and T ₂
Is related to one of these. Period T ₃ is related to that of the other of these methods. These are shown on the same time scale for illustrative purposes.

First, consider the operation of the present invention in the period T ₁ and T _2. The crosstalk correction method shown during period T ₁ + T ₂ applies to a binary (ie, on-off) display. In particular, the waveforms in the first two figures of FIG. 3 show signals supplied to the pixel electrodes in the n-th row and the m-th column. When the scanning line n are in the active state (during the first half of the period T _1), "1" is written into the pixel electrode. In During the second half of the period T _1, "0" is are supplied to the data lines, the writing is not performed to the pixel electrode the scanning pulse is not in the active state in the second half of the cycle. Binary to the same pixel cell in the period T ₁ when it is desired to write "0" may be generated to the opposite state. In this way, the period
Over T _1, a constant RMS voltage is supplied to the data line m. In order to form a better image, a compensation voltage may be applied so as to react against the constant RMS voltage.

Next, attention is paid to the cross-talk removing method shown in the period T _2. Note that these two separate methods are shown in the same figure for convenience of comparison. Generally period T ₃
The voltage waveform shown on data line m has a different characteristic than the simple binary complement shown for that provided in period T ₁ + T ₂ . In particular, the method shown by the waveform on the data line m in the period T ₃ is applicable when using gray-scale display. For gray-scale display, voltages V _1, such as 0 ≦ V ₁ ≦ V _max is applied during the first half of the line address period, the RMS complement is applied to the second half. In particular, the RMS complement is calculated as:

In this way, the period T _3, there are two different voltages applied to the data line m. In the first half of the period, the applied voltage is V _1. In the second half of the period T _3, the voltage applied to the data line m is V _2, i.e., RMS complement. This also guarantees a constant RMS voltage on data line m. If a voltage greater than V ₀ = V _max is available, the correction is made in a shorter period and the same constant RM
Generates S voltage level. Need not period T ₃ is divided into two identical parts of the.

A fourth embodiment of the present invention is shown in FIG. However, the main configuration is the same. In particular, after some number of row address periods _Nmax , a correction voltage is applied to data line m, and the RMS voltage has a constant value over an extended period. As shown in FIG. 4, the voltage applied during the correction period is selected to be the RMS complement of the average voltage applied during the _Nmax row address period. It should be noted that FIG. 4 shows the relative values and timing, especially during the illustrated row address period, not all data values are binary values. In the embodiment shown in FIG. 4, all data lines are addressed in the usual manner, and the RMS correction waveform is applied to provide a constant RMS voltage on the data lines for the entire period (row address period + correction period). You. If the same amplitude is applied during the correction, the correction period is equal to _Nmax row address periods. If twice the maximum data voltage is available, only one quarter of the row address period is needed.

Digital means to achieve a method shown in the period T ₁ and T ₂ of FIG. 3 is shown in Figure 5 and Figure 6. Especially,
Note that exclusive OR circuit 31 is used to perform the desired binary complement operation described above. Two levels
For displays, this circuit generates a constant RMS waveform. This constant RMS waveform is generated by inverting the data during half of the line address period and energizing the scan output during the non-inverted half of the line address period. This is achieved by providing an exclusive OR gate at the output of each data driver as shown in FIG.
This is achieved by using exclusive OR gates on the serial data input lines for the 30 shift registers. In this latter embodiment, data is supplied to the data driver twice during each line address period. In this latter embodiment, a single exclusive OR circuit 32 is used.
Note that only this is necessary (see FIG. 6).

An embodiment of the above-described correction method for a multi-level or grayscale display is shown in FIGS. 7 and 8. In particular, the circuit shown in FIG. 7 uses analog sample / hold (S / H) drivers 55 and 56. The RMS complement is output using analog circuits such as a squarer 51, an adder / subtracter 52, a square root calculator 53 and a switch 54. Switch 54 selects raw input line video data or analog video data which is selected by the scan enable signal and processed to generate the RMS complement value. The timing signals provided to the sample / hold circuits 55 and 56 ensure that valid data is simultaneously available to a selected row of the display as determined by its associated video display data.

A second embodiment of the RMS complement generator is shown in FIG. This embodiment uses digital data and a look-up table (LUT) to determine the RMS complement. A digital-to-analog converter 66 is used as a data line driver. In particular, FIG. 8 shows the case where the video data is input in digital form, where 8 bits are allocated to determine one of the 256 gray scale levels applied to the pixel electrodes. Especially,
The data is supplied to a look-up table 60. The look-up table 60 has a ROM of (for example) 256 × 256 elements, the ROM of 256 × 256 elements being used to determine the RMS complement for 256 possible combinations of data inputs. I have. Scan energizing signal is switch 64
Switch 64 selects either the raw digital data or the digital data that has been processed to determine its RMS complement. For example, see the waveform shown in the latter half of the period T3 in the first diagram shown in FIG. This 8-bit binary data is provided to data bus and data latch 65.
Each of these latches is a digital to analog converter 66
And this converter 66 is used to drive the various data lines in the pixel array. Thus, the desired RMS
A voltage waveform is applied to the data lines to form a desired constant RMS voltage.

Thus, it will be appreciated that the method and apparatus of the present invention is suitable for eliminating crosstalk in a matrix-addressed liquid crystal display. More particularly, it can be seen that the method and apparatus of the present invention include means for compensating for additional signals that may be undesirably applied to various pixel elements. In particular, this method is important for high resolution displays that have large parasitic capacitance effects due to proximity structures. Then, the uncertainty of the voltage on the element caused by the parasitic capacitance between the data line and the pixel electrode is eliminated. It should be noted that the method of the present invention is easy to implement and solves a significant problem in manufacturing high resolution liquid crystal display devices.

Although the present invention has been described in detail with reference to its preferred embodiments,
Many modifications and variations will be apparent to practitioners skilled in the art. Therefore,
It is intended that the appended claims cover all such modifications and variations that fall within the true spirit and scope of the invention.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the entire structure of the present invention. FIG. 2 is a block diagram of an electrical circuit of a portion of the pixel array shown in FIG. 1, specifically illustrating the parasitic capacitance effect that is to be reduced by the present invention. FIG. 3 is a waveform diagram showing voltage with respect to time of a specific data line and scanning line signal. FIG. 4 is a waveform diagram showing a voltage with respect to a time of a data line to which an RMS correction voltage is applied after a plurality of specific scanning periods. Fig. 5 shows the RM using the on / off type display
FIG. 9 is a block diagram showing one method of applying an S voltage correction waveform. FIG. 6 is a block diagram showing a modification of the circuit shown in FIG. FIG. 7 is a block diagram showing an analog RMS voltage compensation circuit for a gray scale display device. FIG. 9 is a block diagram illustrating another digital gray scale display compensation system of FIG. 10 ... LCD display device, 20 ... Pixel array, 21 ...
... pixel electrode, 22 ... scanning line, 24 ... data line, 25 ... switching element.

Claims (4)

(57) [Claims] A plurality of pixel electrodes arranged in a lattice pattern on a first insulating substrate; a plurality of semiconductor switching elements connected to the corresponding pixel electrodes so as to be associated with the corresponding pixel electrodes; A second ground plane electrode disposed thereon and at least one ground plane electrode disposed at a predetermined distance from the first substrate;
And a liquid crystal material disposed between the substrates, wherein the liquid crystal material constitutes a capacitive electric element together with the pixel electrode and the at least one ground plane electrode. A plurality of conductive scanning lines connected to the plurality of semiconductor switching elements associated with a row; and a plurality of conductive scanning lines each connected to the plurality of semiconductor switching elements associated with a column of the pixel electrode grid. A data line, a unit for sequentially supplying a unipolar energizing signal to the scanning line, and a data signal supplying unit for supplying a plurality of unipolar data signals to the data line, wherein the data signals are successive. Generated during a period between each other at the start of the scan line energizing signal generated during the period such that a substantially constant RMS voltage is provided to at least some of the data lines during the period. A data voltage supply means for applying a desired voltage level to the data line in a first part of the period, and a correction voltage level to the data line in a second part of the period And a display device comprising: 2. The apparatus of claim 1, wherein said correction voltage level is a binary complement of said desired voltage level. 3. A method of driving a thin film transistor matrix addressed liquid crystal display device having a scanning line extending in a first direction and a data line extending in a second direction, wherein a unipolar energizing signal is applied to the scanning line. Providing a plurality of unipolar data signals to the data lines, wherein the data signals are generated within a period between each other at the beginning of successively generated scan line activation signals; During a first portion of the period, a desired voltage level is applied to the data line such that a substantially constant RMS voltage is provided to at least some of the data lines during the period, and 2. The method of claim 2, wherein the correction voltage level is supplied to the data line in the part (2). 4. A plurality of pixel electrodes arranged in a grid pattern on a first insulating substrate; a plurality of semiconductor switching elements connected to the corresponding pixel electrodes so as to be associated with the corresponding pixel electrodes; A second substrate having at least one ground plane electrode disposed thereon, disposed at a predetermined distance from the first substrate, and a liquid crystal material disposed between the substrates; A liquid crystal material forming a capacitive electrical element with a pixel electrode and the at least one ground plane electrode; and a plurality of semiconductor switching elements each connected to a plurality of the semiconductor switching elements associated with a row of the pixel electrode grid. A plurality of conductive data lines connected to the plurality of semiconductor switching elements, each of which is associated with a column of the pixel electrode grid; and a unipolar energizing signal to the scan lines. And data signal supply means for supplying a plurality of unipolar data signals to the data line, wherein the means is an integral multiple of a period between the scanning line signals supplied one after another. Acting for an equal amount of time, applying various desired voltage levels to the data line during the extended period of time and applying a correction voltage level to the data line during the period following the extended period. And a data signal supply means for supplying a substantially constant RMS voltage to at least some of the data lines over the extended time period and a time period following the extended time period.