JP2010276800A - Display device, voltage correction method of signal line, and signal line drive section - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device that sets the voltage correction amount for each signal line and corrects line-like display irregularity caused by variation, or the like, of the parasitic capacitance between a selector switch TFT (thin-film transistor) and a signal lines, a voltage correction method of the signal lines and a signal line driving section. <P>SOLUTION: The display device includes a pixel array section 101, where pixel TFTs 103-11 to 103-mn electrically connected to scanning lines 116-1 to 116-m and signal lines 115-1 to 115-n and pixels PIX11-PIXmn, consisting of pixel electrodes 104-11 to 104-mn electrically connected to the pixel TFTs 103-11 to 103-mn are arranged in an array shape, and a signal line voltage correction section 20 including voltage correction capacitances 22-1 and 22-n, electrically connected to the signal lines 115-1 to 115-n and TFT memories 21-1 to 21-n, electrically connected to the voltage correction capacitances 22-1 to 22-n. The threshold of the TFT memories 21-1 to 21-n is variable. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a display device, a voltage correction method for a signal line provided in the display device, and a signal line driving unit provided in the display device, and in particular, corrects display unevenness in an active matrix display device. The present invention relates to a display device, a signal line voltage correction method, and a signal line driving unit.

  In recent years, an active matrix type liquid crystal display device using a thin film transistor (TFT) is used as a display device for a portable information terminal such as a mobile phone, a PDA (Personal Digital Assistant), and a notebook personal computer. This liquid crystal display device is characterized by being lightweight, thin, and low power consumption.

  FIG. 9 is an explanatory diagram showing a conventional example of a pixel array unit included in a display panel of a liquid crystal display device.

  In general, a liquid crystal display device includes a display panel in which a liquid crystal layer is sandwiched between two opposing substrates (not shown).

  One of the two substrates is provided with a pixel array unit 101 including a plurality of pixels PIX11 to PIXmn arranged in a matrix (array). In this pixel array portion 101, a plurality of signal lines (n signal lines 115-1 to 115-n in the figure) for transmitting video signals and a plurality of scanning lines to which scanning line selection signals G1 to Gm are input ( In the figure, m scanning lines 116-1 to 116-m) are formed in a lattice pattern. In the one substrate, pixel TFTs 103-11 to 103- functioning as switches at the time of pixel selection are provided at intersections of the signal lines 115-1 to 115-n and the scanning lines 116-1 to 116-m. mn and pixel electrodes 104-11 to 104-mn to which video signals are input via the pixel TFTs 103-11 to 103-mn are provided, respectively. Further, a common electrode 118 is disposed on the one substrate.

  A counter electrode 106 and a color filter (not shown) are formed on the other of the two substrates.

  Next, each pixel of the liquid crystal display device will be described in more detail.

  FIG. 10 is an explanatory diagram illustrating an electrical configuration example of one pixel provided in the pixel array unit illustrated in FIG. 9.

  For example, the pixel PIXjk in the j-th row and the k-th column (where 1 ≦ j ≦ m, 1 ≦ k ≦ n) includes a pixel TFT 103-jk as shown in FIG. 10, and the gate of this pixel TFT 103-jk The electrodes 103a-jk are connected to the scanning line 116-j to which the scanning line selection signal Gj is input, and the source electrodes 103b-jk are connected to the signal line 115-k to which the video signal SIGk is input. The drain electrode 103c-jk is connected to the pixel electrode 104-jk. Thus, when the pixel TFT 103-jk is turned on in accordance with the value of the scanning line selection signal Gj, a voltage (video signal voltage) corresponding to the value of the video signal input to the signal line 115-k is applied to the pixel electrode 104-jk. Applied.

  Further, the pixel PIXjk has a video signal voltage formed between the liquid crystal capacitor 105-jk formed between the pixel electrode 104-jk and the counter electrode 106, and between the pixel electrode 104-jk and the common electrode 118. A charge holding capacitor 107-jk for holding.

  When display is performed using the pixel PIXjk having such a configuration, the pixel TFT 103 − is applied according to the value of the scanning line selection signal Gj in a state where the counter electrode voltage is applied to the counter electrode 106 and the common electrode voltage is applied to the common electrode 118. When jk is turned on, a voltage (video signal voltage) corresponding to the value of the video signal input to the signal line 115-k is applied to the pixel electrode 104-jk. Thereby, the transmittance of the liquid crystal layer of the pixel PIXjk changes according to the difference between the counter electrode voltage and the video signal voltage. In the liquid crystal display device, a desired image is displayed by controlling the transmittance of each pixel in this way.

  The active matrix type liquid crystal display device outputs a video signal to each signal line to drive each signal line, and outputs a scanning line selection signal to each scanning line. A scanning line driving circuit (gate driver) for driving the scanning lines is also provided.

  The source driver is generally formed using a driver IC (integrated circuit) and used in a state of being externally attached to two substrates. Therefore, it is necessary to physically connect the signal line formed on the one substrate and the output line of the driver IC. In recent years, liquid crystal display devices have become highly precise, so the pixel pitch has become very narrow, and the spacing between signal lines has become very narrow. As a result, there has been a problem that it is difficult to connect one output line of the driver IC and one signal line.

  In order to solve such a problem, a plurality of signal lines are associated with one output line of the driver IC, and the output of the driver IC is time-divided into each signal line by a selector circuit formed on the one substrate. A so-called selector driving method is used. As a conventional example of a display device adopting this selector driving method, there is a display device disclosed in Japanese Patent Application Laid-Open No. 2003-323162, which is described later.

  FIG. 11 is an explanatory view showing a conventional example of an active matrix type liquid crystal display device adopting a selector driving method.

  Since the pixel array unit 101 of the liquid crystal display device has the same configuration as the pixel array unit of the liquid crystal display device shown in FIG. 9, the same parts are denoted by the same reference numerals and description thereof is omitted.

  The liquid crystal display device illustrated in FIG. 11 includes a source driver that outputs video signals to the plurality of signal lines 115-1 to 115-n of the pixel array unit 101 to drive each signal line, and a plurality of scans of the pixel array unit 101. A gate driver that outputs scanning line selection signals G1 to Gm to the lines 116-1 to 116-m, drives the scanning lines 116-1 to 116-m, and outputs a signal of a constant voltage to the common electrode 118, respectively. 113.

  In order to reduce the number of source driver output lines of the source driver 111, this liquid crystal display device employs a selector driving method in which a plurality of signal lines are associated with one source driver output line of the source driver 111. In the liquid crystal display device shown in FIG. 11, in order to employ the selector driving method, a selector switch unit 120 described later, and a control for outputting control signals such as a selector signal SEL1, a selector signal SEL2, and a selector signal SEL3 to the selector switch unit 120 are provided. And a circuit 112.

  When the selector driving method is adopted, a plurality of source driver output lines and a plurality of signal lines of the source driver 111 are set in a 1-to-x (x is an integer of 2 or more) comparison relationship, and one source of the source driver 111 is set. The x signal lines assigned to the driver output lines are selected and driven in a time division manner. In the selector switch section 120 of the liquid crystal display device shown in FIG. 11, n / 3 source driver output lines 111-1 to 111 -n / 3 and n signal lines 115-1 to 115 -n are in a one-to-three relationship. The three signal lines assigned to one source driver output line of the source driver 111 are selected and driven in a time division manner. For example, three signal lines 115-1 to 115-3 are assigned to the first source driver output line 111-1 of the source driver 111.

  More specifically, the selector switch unit 120 includes three selector scanning lines 124-1 to 124-3 and selector switch TFTs 114-1 to 114-n that function as switching elements.

  Each gate electrode of the selector switch TFTs 114-1 to 114-n is connected to any one of the selector scanning lines. For example, the gate electrodes of the first-stage selector switch TFT 114-1 and the selector switch TFT 114- (n-2) are connected to the first selector scanning line 124-1, and the second-stage selector switch TFT 114- 2 and the selector switch TFT 114- (n-1) are connected to the second selector scanning line 124-2, and the third stage selector switch TFT 114-3 and the gate electrode of the selector switch TFT 114-n. Are connected to the third selector scanning line 124-3.

  In addition, each source electrode of the selector switch TFTs 114-1 to 114-n is connected to any one of the plurality of source driver output lines 111-1 to 111 -n / 3 of the source driver 111. ing. For example, each source electrode of the selector switch TFTs 114-1 to 114-3 is connected to the source driver output line 111-1.

  Further, each drain electrode of the selector switch TFTs 114-1 to 114-n is connected to any one signal line. For example, the drain electrode of the selector switch TFT 114-1 is connected to the signal line 115-1, the drain electrode of the selector switch TFT 114-2 is connected to the signal line 115-2, and the drain electrode of the selector switch TFT 114-3. Is connected to the signal line 115-3.

  When displaying a video, three video signals SIG1 are output from the source driver output line 111-1 of the source driver 111 to the three signal lines 115-1 to 115-3 while being time-divided. At this time, while the video signal SIG1 is outputting data for the signal line 115-1, the selector switch TFT 114-1 is turned on by the selector signal SEL1, and at the same time, the selector switch SEL2 and the selector signal SEL3 are used. The TFT 114-2 and the selector switch TFT 114-3 are turned off. Similarly, while the video signal SIG1 is outputting data for the signal line 115-2, the selector switch TFT 114-1 and the selector switch TFT 114-3 are simultaneously switched to the ON state. While the video signal SIG1 is outputting data for the signal line 115-3, the selector switch TFT 114-3 and the selector switch TFT 114- are simultaneously switched on. 2 is turned off.

  Further, the pixel TFTs 103-11 to 103-mn are sequentially turned on for each of the scanning lines 116-1 to 116-m by the scanning line selection signals G1 to Gm output from the gate driver 113 to the scanning lines 116-1 to 116-m. By doing so, a video signal can be written to a desired pixel (the transmittance of each pixel is controlled).

  However, the above-described conventional display device has a problem that display unevenness such as a dot shape or a line shape may occur due to various reasons.

  For example, in the case of a selector driving type liquid crystal display device as shown in FIG. 11, variations in the pulse waveforms of the selector signal SEL1, the selector signal SEL2, and the selector signal SEL3 output from the control circuit 112, and selector switch TFTs 114-1 to 114- 3 and the signal lines 115-1 to 115 -n, due to variations in the feedthrough voltage caused by variations in the parasitic capacitance between the signal lines 115-1 to 115 -n, particularly when the entire gray display is performed, the signal lines 115-1 to 115 -n. Line-shaped display unevenness along the line may be seen.

  In order to solve such a problem, a method for eliminating the variation in the pulse waveform of the selector signal, which is one of the causes of the variation in the feedthrough voltage, has been proposed. As a conventional example of a method for eliminating the variation in the pulse waveform of the selector signal, there is a display device driving method disclosed in Japanese Patent Application Laid-Open No. 2006-308711, which will be described later.

  In the display device driving method disclosed in Japanese Patent Laid-Open No. 2006-308711, the power supply voltage supplied to the three buffers is forcibly controlled at the end of driving of each of the three buffers, whereby each buffer is controlled. The variation in the feedthrough voltage is reduced by making the falling waveforms of the signals output from the output signals substantially the same.

JP 2003-323162 A JP 2006-308711 A

  However, in the driving method of the display device disclosed in Patent Document 2 described above, the variation in feedthrough voltage due to the variation in parasitic capacitance between the selector switch TFT and the signal line cannot be suppressed. In the case of variation, there is a problem that it is difficult to obtain a good display without display unevenness.

  The present invention was devised to solve such a problem, and even when a line-shaped display unevenness occurs due to a variation in parasitic capacitance between the selector switch TFT and the signal line, it is written in the pixel electrode. It is an object of the present invention to provide a display device, a signal line voltage correction method, and a signal line driver that can correct video signal voltage and obtain good display characteristics.

  In order to solve the above problems, a display device of the present invention is electrically connected to a first switching element (pixel TFT) electrically connected to a scanning line and a signal line, and the first switching element. A pixel array unit in which a plurality of pixels each having a pixel electrode are arranged in an array, a scanning line driving circuit (gate driver) that outputs an electric signal for driving the scanning line, and an electric signal for driving the signal line A capacitor element (voltage correction capacitance) electrically connected to the signal line, and a second switching element (TFT memory) electrically connected to the capacitor element. ), And the threshold value of the second switching element is variable.

  Thus, by providing the second switching element that can change the threshold value for each signal line, the voltage after adjusting the threshold value of the second switching element according to the state of display unevenness. By performing the correction process, the voltage correction amount for each signal line can be set. Therefore, even when line-shaped display unevenness is detected along the signal line direction, it is possible to correct the display unevenness and obtain a display device having good display characteristics.

  Further, by changing the voltage applied to the second switching element from one level to another level, the potential of the pixel electrode selected by the electric signal output from the scanning line driving circuit is changed. It may be changed according to the threshold value.

  In this case, display unevenness can be corrected without hindering the display operation.

  The second switching element may be a thin film transistor.

  In this case, the second switching element can be formed at the same time as the thin film transistor used in the pixel array portion or the thin film transistor used in the gate driver, and the display device can be manufactured without adding a process.

  In addition, a selector switch unit provided between the signal line driver circuit and the signal line is further provided, and the selector switch unit supports a plurality of signal lines for one output of the signal line driver circuit. You may let them.

  In this case, the number of source driver output lines of the source driver can be reduced.

  In addition, the signal line voltage correction unit may further include a threshold adjusting unit that adjusts the threshold of the second switching element by electrically changing.

  In this case, the threshold value of the second switching element can be easily adjusted.

  In addition, the threshold adjustment means includes a shift register (S / R) that outputs an electrical signal in the on state at the timing for adjusting the threshold, and a timing at which the electrical signal in the on state is output from the shift register. In addition, a third switching element (memory selection TFT) for applying a voltage to the second switching element may be used.

  In this case, the threshold values of the second switching elements arranged in a line can be set independently.

  The threshold value of the second switching element may be adjusted according to the display state after confirming the display state of the display device.

  In this case, for example, the luminance of each pixel can be detected, display unevenness can be confirmed according to this luminance, and the threshold value can be adjusted.

  Further, the number of the second switching elements may be larger than the number of signal lines.

  In this case, a large amount can be used as a dummy second switching element. That is, the threshold adjustment processing condition (threshold adjustment processing time and / or threshold adjustment) when the dummy second switching element electrically changes the threshold of the second switching element. The value of the voltage applied at the time of processing) can be confirmed in advance. As a result, even when the threshold adjustment amount for the threshold adjustment processing varies slightly for each display device, it is possible to set appropriate threshold adjustment processing conditions for the second switching element. .

  Further, only when the voltage of the signal line is corrected, the voltage applied to the second switching element may be switched on.

  In this case, when a good display state can be obtained without performing the threshold adjustment process, power consumption can be reduced by stopping the supply of voltage to the second switching element.

  The display device of the present invention includes a plurality of pixels in an array formed of a first switching element electrically connected to a scanning line and a signal line, and a pixel electrode electrically connected to the first switching element. An electrically connected to the signal line, an arrayed pixel array section, a scanning line driving circuit for outputting an electrical signal for driving the scanning line, a signal line driving circuit for outputting an electrical signal for driving the signal line And a signal line voltage correction unit including a second switching element electrically connected to the capacitance element, and the threshold value of the second switching element is variable, and the display The array unit is provided in the display panel, and the signal line drive circuit and the signal line voltage correction unit are externally attached to the display panel.

  Thereby, the voltage correction amount for each signal line can be set by performing the voltage correction processing after adjusting the threshold value of the second switching element according to the display unevenness situation. Therefore, even when line-shaped display unevenness is detected along the signal line direction, it is possible to correct the display unevenness and obtain a display device having good display characteristics. Furthermore, it is possible to obtain a display device capable of correcting the voltage of a signal line only by externally attaching a signal line driving unit to the general display panel without changing the configuration of the general display panel. it can.

  Further, by changing the voltage applied to the second switching element from one level to another level, the potential of the pixel electrode selected by the electric signal output from the scanning line driving circuit is changed. It may be changed according to the threshold value.

  In this case, display unevenness can be corrected without hindering the display operation.

  The second switching element may be a semiconductor memory element.

  In this case, the signal line drive circuit can be formed in the same IC chip as the signal line voltage correction unit.

  In addition, the signal line voltage correction unit may further include a threshold adjusting unit that adjusts the threshold of the second switching element by electrically changing.

  In this case, the threshold value of the second switching element can be easily adjusted.

  The threshold adjusting means outputs a shift register that outputs an electrical signal in an on state at a timing for adjusting the threshold, and performs a second switching at a timing when the electrical signal in an on state is output from the shift register. It may comprise a third switching element that applies a voltage to the element.

  In this case, the threshold values of the second switching elements arranged in a line can be set independently.

  The threshold value of the second switching element may be adjusted according to the display state after confirming the display state of the display device.

  In this case, the luminance of each pixel can be detected and the threshold value can be adjusted according to this luminance.

  Further, only when the voltage of the signal line is corrected, the voltage applied to the second switching element may be switched on.

  In this case, when a good display state can be obtained without performing the threshold adjustment process, power consumption can be reduced by stopping the supply of voltage to the second switching element.

  The voltage correction method for a signal line according to the present invention includes a plurality of first switching elements electrically connected to the scanning lines and the signal lines, and a plurality of pixel electrodes electrically connected to the first switching elements. A method of correcting a voltage of the signal line of a display device including a pixel, the display device comprising: a capacitor element electrically connected to the signal line; and a second element electrically connected to the capacitor element. A signal line voltage correction unit including the switching element, the threshold value of the second switching element is variable, and the threshold value is adjusted by applying a voltage to the second switching element. And a voltage correction procedure for outputting a voltage correction signal corresponding to the adjusted threshold value from the second switching element to the capacitive element to correct the voltage of the signal line. Become.

  Thereby, the voltage correction amount for each signal line can be set by performing the voltage correction processing after adjusting the threshold value of the second switching element according to the display unevenness situation. Therefore, even when line-shaped display unevenness is detected along the signal line direction, the display unevenness can be corrected and a display device having good display characteristics can be obtained.

  The signal line drive unit of the present invention includes a signal line drive circuit including a digital-analog converter that converts a digital signal into an analog signal and outputs the analog signal, an output terminal of the signal line drive circuit, and the signal line. Capacitance element having one end electrically connected to the connection part (such as a MOS (metal-oxide semiconductor) capacitance formed on a semiconductor substrate) and a switching element electrically connected to the other end of the capacitor (Semiconductor memory element), and the threshold value of the switching element is variable.

  Thereby, the voltage correction amount for each signal line can be set by performing the voltage correction processing after adjusting the threshold value of the switching element according to the display unevenness situation. Therefore, even when line-shaped display unevenness is detected along the signal line direction, the display unevenness can be corrected and a display device having good display characteristics can be obtained. Furthermore, it is possible to obtain a display device capable of correcting the voltage of a signal line only by externally attaching a signal line driving unit to the general display panel without changing the configuration of the general display panel. it can.

  Since the present invention is configured as described above, a voltage correction amount can be set for each signal line. As a result, it is possible to correct line-shaped display unevenness in the display device due to variations in parasitic capacitance between the selector switch TFT and the signal line.

It is explanatory drawing which shows Embodiment 1 of the display apparatus of this invention. FIG. 2 is a partial enlarged view of a portion related to a k-th signal line of the display device shown in FIG. 3 is a graph showing an example of current-voltage characteristics of the TFT memory according to the first embodiment. 3 is a graph showing an example of an output voltage waveform of the TFT memory according to the first embodiment. It is a timing chart which shows Embodiment 1 of the voltage correction method of the signal wire | line of this invention. It is the elements on larger scale of the display apparatus shown in FIG. It is a timing chart which shows Embodiment 2 of the voltage correction method of the signal wire | line of this invention. It is a block diagram which shows one Embodiment of the signal line drive part of this invention. It is explanatory drawing which shows one prior art example of the pixel array part contained in the display panel of a liquid crystal display device. It is explanatory drawing which shows one pixel provided in the pixel array part shown in FIG. It is explanatory drawing which shows one prior art example of the active matrix type liquid crystal display device which employ | adopted the selector drive system.

  Hereinafter, embodiments of a display device, a signal line voltage correction method, and a signal line driver of the present invention will be described.

  In the embodiment described below, a configuration in which the present invention is applied to an active matrix liquid crystal display device capable of multi-tone display using liquid crystal as an electro-optical material is illustrated. However, the present invention can be implemented in many different modes and should not be construed as being limited to the description of the embodiments described below.

<Embodiment 1 of Display Device and Signal Line Voltage Correction Method>
First, Embodiment 1 of the display device of the present invention will be described with reference to the drawings.

  FIG. 1 is an explanatory diagram showing Embodiment 1 of the display device of the present invention, and FIG. 1 shows only the electrical configuration.

  In the figure, the same parts as those in the liquid crystal display device shown in FIG.

  The display device of this embodiment includes a display panel including two substrates (not shown) that face each other with a liquid crystal layer interposed therebetween.

  One of the two substrates is provided with a pixel array unit 101 including a plurality of pixels PIX11 to PIXmn arranged in an array. In this pixel array portion 101, a plurality of signal lines (n signal lines 115-1 to 115-n in the figure) for transmitting video signals and a plurality of scanning lines to which scanning line selection signals G1 to Gm are input ( In the figure, m scanning lines 116-1 to 116-m) are formed in a lattice pattern. In the one substrate, pixel TFTs (first switching) functioning as switches at the time of pixel selection are provided at intersections of the signal lines 115-1 to 115-n and the scanning lines 116-1 to 116-m. Elements) 103-11 to 103-mn and pixel electrodes 104-11 to 104-mn to which video signals are inputted through the pixel TFTs 103-11 to 103-mn are provided. Further, a common electrode 118 is disposed on the one substrate.

  A counter electrode 106 and a color filter (not shown) are formed on the other of the two substrates (not shown).

  The display device according to the present embodiment includes a selector switch unit 120, a signal line voltage correction unit 20, a control circuit 12 that outputs various control signals to the selector switch unit 120 and the signal line voltage correction unit 20, and video signals SIG1 to SIG1. A source driver 111 that outputs SIGn / 3 and a gate driver 113 that outputs scanning line selection signals G1 to Gm are further provided. For example, the source driver 111 is composed of, for example, a digital-analog converter that converts a digital signal into an analog signal and outputs it to a signal line, and is externally attached to the display panel. Further, the selector switch unit 120, the signal line voltage correction unit 20, the control circuit 12, and the gate driver 113 are arranged in the periphery of the pixel array unit 101 of the display panel. In the display device illustrated in FIG. 1, the signal line voltage correction unit 20 is disposed between the selector switch unit 120 and the pixel array unit 101.

  In this embodiment, in order to reduce the number of source driver output lines of the source driver 111, a selector driving method is adopted in which a plurality of signal lines are associated with one source driver output line of the source driver 111.

  In the display device shown in FIG. 1, control signals such as a selector signal SEL1, a selector signal SEL2, and a selector signal SEL3 are output from the control circuit 12 to the selector switch unit 120 in order to employ the selector driving method. When the selector driving method is adopted, a plurality of source driver output lines and a plurality of signal lines of the source driver 111 are set in a 1-to-x (x is an integer of 2 or more) comparison relationship, and one source of the source driver 111 is set. The x signal lines assigned to the driver output lines are selected and driven in a time division manner. In the display device shown in FIG. 1, n / 3 source driver output lines 111-1 to 111-n / 3 and n signal lines 115-1 to 115-n are set in a one-to-three contrast relationship. The three signal lines assigned to one source driver output line of the source driver 111 are selected and driven in a time division manner. As a specific example, three signal lines 115-1 to 115-3 are assigned to one source driver output line 111-1 of the source driver 111, and the video signal SIG 1 has a signal line 115. Video signals for three lines −1 to 115-3 are included in a time-divided state.

  Further, the source driver 111 outputs the video signals SIG1 to SIGn / 3 to the plurality of signal lines 115-1 to 115-n via the source driver output lines 111-1 to 111-n / 3 and outputs the signal lines 115-. 1 is a signal line driving circuit for driving 1-115-n. The source driver 111 has a function of converting a digital video signal input from the outside into an analog voltage signal corresponding to the characteristics of the liquid crystal to be used, and outputting the analog voltage signal, and a digital-analog converter (digital-analog converter). ), A shift register (S / R), a data latch circuit, and the like. In FIG. 1, the source driver 111 outputs an analog video signal SIG1 to the first source driver output line 111-1, and the analog to the n / 3th source driver output line 111-n / 3. The video signal SIGn / 3 is output.

  The selector switch unit 120 includes a plurality of selector scanning lines and a plurality of selector switch TFTs, and the number of selector scanning lines is set according to the comparison relationship between the source driver output lines and the signal lines. The number of TFTs is set according to the number of signal lines. In the display device shown in FIG. 1, since the comparison relationship is 1: 3, the selector switch unit 120 is provided with three selector scanning lines 124-1 to 124-3.

  As a specific example, the first selector scanning line 124-1 is connected to the gate electrodes of the first-stage selector switch TFTs 114-1 to 114- (n-2), and the second selector scanning line. The line 124-2 is connected to the gate electrodes of the second stage selector switch TFTs 114-2 to 114- (n-1), and the third selector scanning line 124-3 is the third stage selector switch. It is connected to the gate electrodes of the TFTs 114-3 to 114-n. Further, the first source driver output line 111-1 is connected to the source electrodes of the three selector switch TFTs 114-1 to 114-3, and one of the three selector switch TFTs 114-1 to 114-3 is one stage. The drain electrode of the first selector switch TFT 114-1 is connected to the first signal line 115-1, and the drain electrode of the second stage selector switch TFT 114-2 is connected to the second signal line 115-2. The drain electrode of the TFT 114-3 is connected to the third signal line 115-3. In such a configuration, when the selector switch TFT 114-1 is turned on according to the value of the selector signal SEL1, the video signal SIG1 output from the first source driver output line 111-1 is 1 through the selector switch TFT 114-1. The signal is input to the signal line 115-1.

  The control circuit 12 controls the selector scanning lines 124-1 to 124-3 in order to control the operation timing of the selector switch TFTs 114-1 to 114-n by using various control signals (selector signal SEL 1, selector signal SEL 2, and so on). And a correction gate line 25a, a first correction signal line 25b1, and a second correction signal line, which will be described later, in order to control the operation of the signal line voltage correction unit 20. 25b2 also has a function of outputting various control signals (correction gate signal GP, first correction drain signal DP1, and second correction drain signal DP2 described later).

  The gate driver 113 is composed of, for example, a shift register or the like, and outputs scanning line selection signals G1 to Gm to a plurality of scanning lines 116-1 to 116-m to drive the scanning lines 116-1 to 116-m, respectively. In addition, the scan line driver circuit has a function of outputting a signal having a constant voltage to the common electrode 118. As a specific example, in FIG. 1, the gate driver 113 is configured to output a scanning line selection signal G1 to the first scanning line 116-1.

  Here, a configuration example of the signal line voltage correction unit 20 will be described with reference to FIGS. 1 and 2.

  FIG. 2 is a partially enlarged view of a portion related to the kth signal line of the display device shown in FIG.

  Among a plurality of pixels arranged in a matrix (array) in the pixel array unit 101, for example, a pixel PIXjk in the j-th row and the k-th column (where 1 ≦ j ≦ m, 1 ≦ k ≦ n) is shown in FIG. As shown, the pixel TFT 103-jk functioning as a switch, the pixel electrode 104-jk, and the liquid crystal layer are arranged at the intersection of the kth signal line 115-k and the jth scanning line 116-j. A liquid crystal capacitor 105-jk formed between the opposing pixel electrode 104-jk and the counter electrode 106, and a charge holding capacitor 107-jk formed between the pixel electrode 104-jk and the common electrode 118. Comprising.

  The gate electrode 103a-jk of the pixel TFT 103-jk is connected to the scanning line 116-j to which the scanning line selection signal Gj is input, and the source electrode 103b-jk is the signal line 115- to which the video signal SIGk is input. The drain electrode 103c-jk is connected to the pixel electrode 104-jk. In such a configuration, in the pixel PIXjk, when the pixel TFT 103-jk is turned on in accordance with the value of the scanning line selection signal Gj, the video signal voltage corresponding to the value of the video signal input to the signal line 115-k is applied to the pixel electrode. 104-jk. As a result, the transmittance of the liquid crystal layer is determined by the potential difference between the pixel electrode 104-jk and the counter electrode 106, and the display gradation of the pixel PIXjk is determined. The charge holding capacitor 107-jk has a function of holding the charge stored in the pixel electrode 104-jk in accordance with the voltage of the video signal SIGk.

  Further, as shown in FIG. 1, the signal line voltage correction unit 20 includes a correction gate line 25a, a first correction signal line 25b1, and a first correction signal line formed in parallel to the scanning lines 116-1 to 116-m. 2 correction signal line 25b2. Further, the signal line voltage correction unit 20 includes TFT memories (second switching elements) 21-1 to 21-n arranged at the intersections of the correction gate line 25a and the signal lines 115-1 to 115-n. And voltage correction capacitances (capacitance elements) 22-1 to 22-n connected between the signal lines 115-1 to 115-n and the TFT memories 21-1 to 21-n. The voltage correction capacitances 22-1 to 22-n are formed, for example, between a silicon film used for the body region of the TFT and a metal film used for the gate electrode of the TFT via a gate insulating film. A MOS capacitance or the like can be considered.

  The correction gate signal GP is supplied from the control circuit 12 to one end of the correction gate line 25a, and the first correction drain signal DP1 is supplied from the control circuit 12 to the one end of the first correction signal line 25b1. The second correction drain signal DP2 is input from the control circuit 12 to one end of the signal line 25b2. The other end of the correction gate line 25a is provided with a gate (Gwrite) pad 26a that is used only during threshold adjustment processing. The first correction signal line 25b1 and the second correction signal line 25b2 At the other end, a drain (Dwrite) pad 26b1 and a Dwrite pad 26b2 are provided.

  In this embodiment, for some reason (for example, the parasitic capacitance between the selector switch TFTs 114-1 to 114-n and the signal lines 115-1 to 115-n varies for each of the signal lines 115-1 to 115-n, and the selector switch unit 120), the potential difference between the pixel electrode and the counter electrode is deviated from a preset value in a part of the pixel array portion due to a variation in the field through voltage generated at 120 for each of the signal lines 115-1 to 115-n. In this case, the signal line voltage correction unit 20 is used to perform voltage correction on at least some of the signal lines, thereby correcting the shift and obtaining a good display.

  A liquid crystal display device using a generally used liquid crystal material as an electro-optical material is usually required to have a voltage accuracy of ± 10 millivolts (mV) or less. For this reason, when the voltage applied to some of the pixel electrodes deviates more than ± 10 (mV) from a preset value due to variations in parasitic capacitance, etc., the same gradation is used. Display unevenness occurs when the entire screen is displayed.

  However, in this embodiment, the threshold values of the TFT memories 21-1 to 21-n are adjusted by threshold adjustment processing described in detail later, and the voltage correction amounts of the signal lines 115-1 to 115-n are adjusted. Is stored in each of the TFT memories 21-1 to 21-n as an analog quantity, thereby correcting display unevenness. Therefore, as shown in FIG. 1, the signal line voltage correction unit 20 includes a correction source line 25 c provided with a source (Write) pad 26 c at one end and a trigger (TRG). ) A correction start pulse line 25d provided with a pad 26d at one end, a correction clock pulse line 25e provided with a clock (CLK) pad 26e at one end, and a memory selection TFT (third switching element) 23 -1 to 23-n and shift registers 24-1 to 24-n.

  Note that the Gwrite pad 26a, the Dwrite pad 26b1, the Dwrite pad 26b2, the Swrite pad 26c, the TRG pad 26d, and the CLK pad 26e are disposed, for example, in the periphery of the signal line voltage correction unit 20 of the display panel.

  Here, with reference to FIG. 2, a part related to the kth signal line 115-k in the signal line voltage correction unit 20 will be described in more detail.

  The signal line voltage correction unit 20 performs threshold value adjustment processing on the TFT memory 21-k, the voltage correction capacitance 22-k, and the TFT memory 21-k as parts related to the kth signal line 115-k. A memory selection TFT 23-k that inputs a voltage applied to the Swrite pad 26c to the source electrode of the TFT memory 21-k and a memory selection TFT 23 when a threshold adjustment process is performed on the TFT memory 21-k. The shift register 24-k that switches -k to the on state is provided, and such a configuration is provided for each of the signal lines 115-1 to 115-n.

  One end of the voltage correction capacitance 22-k is connected to the kth signal line 115-k, and the other end is connected to the source electrode of the TFT memory 21-k. The gate electrode of the TFT memory 21-k is connected to the Gwrite pad 26a via the correction gate line 25a, and the drain electrode is connected to the first correction signal line 25b1 to which the first correction drain signal DP1 is input. Is connected to the Dwrite pad 26b1 or to the Dwrite pad 26b2 via the second correction signal line 25b2 to which the second correction drain signal DP2 is inputted.

  Further, the drain electrode of the memory selection TFT 23-k is connected to the connection portion between the other end of the voltage correction capacitance 22-k and the source electrode of the TFT memory 21-k, and the source electrode of the memory selection TFT 23-k is The gate electrode of the memory selection TFT 23-k is connected to the output line of the shift register 24-k through the correction source line 25c. The TRG pad 26d is connected to the trigger terminal of the shift register 24-k via the correction start pulse line 25d, and the clock terminal of the shift register 24-k is connected to the trigger terminal via the correction clock pulse line 25e. The CLK pad 26e is connected.

  In the present embodiment, the TFT memories 21-1 to 21-n used in the signal line voltage correction unit 20 are used in the pixel TFTs 103-11 to 103-mn used in the pixel array unit 101 and the selector switch unit 120. A TFT having the same structure as that of at least one of the selector switches TFT 114-1 to 114-n and the TFT (not shown) used in the gate driver 113 is used. Thereby, the TFT memories 21-1 to 21-n can be formed at the same time when other TFTs are formed, and it is possible to prevent an increase in the number of processes for forming the TFT memories 21-1 to 21-n. . In the present embodiment, P-type TFTs are used as the TFT memories 21-1 to 21-n.

  The Gwrite pad 26a, Dwrite pad 26b1, Dwrite pad 26b2, Swrite pad 26c, TRG pad 26d, and CLK pad 26e are used only when the threshold values of the TFT memories 21-1 to 21-n need to be adjusted. The pad is open when a normal display operation is performed in the display device. Furthermore, the Gwrite pad 26a, the Dwrite pad 26b1, the Dwrite pad 26b2, the Swrite pad 26c, the TRG pad 26d, and the CLK pad 26e are such that the prober needle for applying a voltage during the threshold adjustment process can contact (contact). It is a size.

  In the present invention, as will be described in detail later, when performing display, the selector switches TFT 114-1 to 114-n are sequentially turned on, and video signals are sent from the source driver 111 to desired pixel electrodes 104-11 to 104 -mn. After applying each voltage, at the timing when each selector switch TFT 114-1 to 114-n is turned off, a pulse waveform having a voltage amplitude corresponding to the parasitic capacitance of each signal line 115-1 to 115-n is generated. A correction signal is applied from the TFT memories 21-1 to 21-n to the voltage correction capacitors 22-1 to 22-n, respectively, and the voltages of the signal lines 115-1 to 115-n are set in advance. It is corrected as follows.

  Therefore, after the display device is assembled, inspection is performed, and as a result of this inspection, line unevenness occurs linearly along the signal line direction, and when display unevenness occurs between adjacent pixels in the scanning line direction, The signal line voltage correction method described below is performed, and the voltage amplitude of the pulse waveform of the correction signal input to the voltage correction capacitances 22-1 to 22-n is set for each signal line in accordance with the degree of display unevenness. There is a need to. In the present invention, the voltage amplitude is set by utilizing a so-called threshold drop of the TFT memories 21-1 to 21-n.

  Next, Embodiment 1 of the signal line voltage correction method of the present invention will be described in more detail with reference to FIG.

  In the present embodiment, after the display device assembly process and the display device inspection process are performed, the signal line voltage correction method described later is applied only to the display device that is determined to have display unevenness in the inspection process. Implemented to correct display unevenness. Then, after the display unevenness is corrected by executing the voltage correction method of the signal line, a process of shipping the display device is performed.

  Here, a case where the threshold value of the TFT memory 21-k connected to the kth signal line 115-k via the voltage correction capacitance 22-k is adjusted will be described.

  First, after applying a start pulse to the TRG pad 26d, a pulse is input to the CLK pad 26e, and the outputs of the shift registers 24-1 to 24-n are sequentially turned on. As a result, the output of the desired shift register 24-k is turned on only for a certain period, and the memory selection TFT 23-k connected to the shift register 24-k is turned on.

  During the period in which the memory selection TFT 23-k is in the on state, the source electrode of the TFT memory 21-k that performs the threshold adjustment process and the write pad 26c are electrically connected. Further, by applying a voltage of, for example, about −30 (V) to the Gwrite pad 26a and applying a voltage of, for example, about −10 (V) to the Dwrite pad 26b1 while the TFT memory 21-k is conducting. Threshold adjustment processing is performed to change the threshold value of the TFT memory 21-k.

  The pulse signal of the first correction drain signal DP1 or the second correction drain signal DP2 input to the drain electrode of the TFT memory 21-k has a small voltage swing by about the threshold value in the TFT memory 21-k. Thus, it is output from the source electrode of the TFT memory 21-k and input to the voltage correction capacitance 22-k. Therefore, by changing the threshold value of the TFT memory 21-k, the voltage amplitude ΔVb input to the voltage correction capacitance 21-k in the equation (1) described later can be set for each signal line. As a result, an appropriate voltage correction amount ΔV of the signal line corresponding to the unevenness along the signal line can be set for each signal line according to the equation (1) described later. By appropriately correcting the voltage of the signal line so as to cancel out the unevenness, a good display without unevenness can be obtained.

  Note that the value of the voltage applied to the Gwrite pad 26a and the Dwrite pad 26b1 when performing the threshold adjustment processing is not limited to the above-described value, and may be a value that can change the threshold. For example, the value of the voltage applied to the Gwrite pad 26a is 2 to 3 times the voltage applied when performing a normal switching operation using the TFT memory, and is applied to the Dwrite pad 26b1 and the Dwrite pad 26b2. Since the voltage value is 1.5 to 2 times the voltage applied when performing a normal switching operation using the TFT memory, the threshold value can be adjusted to an appropriate value. preferable. However, the value of the voltage applied to the Gwrite pad 26a, the Dwrite pad 26b1, and the Dwrite pad 26b2 needs to be selected in consideration of the configuration of the TFT memory, the amount of adjusting the threshold value, and the like.

  FIG. 3 is a graph showing an example of the current-voltage characteristics of the TFT memory according to the first embodiment. The vertical axis shows the drain current (A), and the horizontal axis shows the gate voltage (V). This current-voltage characteristic indicates that the current (drain current) flowing between the source electrode and the drain electrode while changing the gate voltage in a state where the drain voltage is fixed to a constant value such as −5 (V). It was obtained by measurement.

  In the current-voltage characteristics shown in FIG. 3, a plurality of TFTs having the same voltage value applied during the threshold adjustment process but having different voltage application time (threshold adjustment process time) during the threshold adjustment process. It was obtained using memory. Specifically, L11 represents the current-voltage characteristics of the TFT memory in the initial (Init) state, L12 represents the current-voltage characteristics of the TFT memory with a threshold adjustment processing time of 1 msec, and L13 represents the threshold adjustment processing time. Shows the current-voltage characteristics of a TFT memory with 10 msec, L14 shows the current-voltage characteristics of a TFT memory with a threshold adjustment processing time of 100 msec, and L15 shows the current-voltage characteristics of a TFT memory with a threshold adjustment processing time of 1000 msec. Show.

For example, referring to the gate voltage when the drain current is 1.0 × 10 ⁻⁸ (A), the gate voltage of the TFT memory not subjected to the threshold adjustment process is about −1.2 (L11). V), the gate voltage of the TFT memory whose threshold adjustment processing time is 1 msec is about −1.6 (V) as shown in L12, and the gate voltage of the TFT memory whose threshold adjustment processing time is 10 msec is shown in L13. As shown in L14, the gate voltage of the TFT memory having a threshold adjustment processing time of 100 msec is about −3.3 (V) and the threshold adjustment processing time being 1000 msec. The gate voltage of the memory is about −4.8 (V) as indicated by L15. That is, the threshold adjustment amount for the TFT memories 21-1 to 21-n can be controlled by changing the threshold adjustment processing time. The threshold adjustment amount to the TFT memories 21-1 to 21-n can also be controlled by the value of the voltage applied during the threshold adjustment process.

  Even if a display device is manufactured according to the same procedures and conditions, appropriate threshold adjustment processing conditions (for each display device) may be caused due to variations in the thickness of the gate oxide film covering the gate electrode surface and variations in gate length. The threshold adjustment processing time and / or the value of the voltage applied during the threshold adjustment processing may be different. In order to cope with such a case, a dummy TFT memory is also provided when the TFT memory 21-1 to 21-n is provided in the pixel array unit 101, and a preliminary threshold is set for the dummy TFT memory. It is desirable to check the threshold adjustment amount by performing value adjustment processing, and to determine threshold adjustment processing conditions to be adopted when performing threshold adjustment processing on the non-dummy TFT memories 21-1 to 21-n. . The dummy TFT memory is provided, for example, in an area that does not affect the correction of the feedthrough voltage in both ends of the signal line voltage correction unit 20.

  FIG. 4 is a graph showing an example of the output voltage waveform of the TFT memory according to the first embodiment. The vertical axis shows the output voltage (V), and the horizontal axis shows time.

  Each output voltage waveform shown in FIG. 4 is obtained by using five TFT memories used when obtaining the current-voltage characteristics shown in FIG. Here, for each TFT memory, a pulse of −5 (V) was applied to the drain electrode between time T1 and time T2 with the gate voltage fixed at a constant value such as −6 (V). The output voltage waveform of the source electrode is monitored.

  Specifically, L21 shows the output voltage waveform of the TFT memory in the Init state, L22 shows the output voltage waveform of the TFT memory with the threshold adjustment processing time of 1 msec, and L23 shows the threshold adjustment processing time of 10 msec. An output voltage waveform of the TFT memory is shown, L24 shows an output voltage waveform of the TFT memory having a threshold adjustment processing time of 100 msec, and L25 shows an output voltage waveform of the TFT memory having a threshold adjustment processing time of 1000 msec.

  Referring to FIG. 4, the voltage swing of the output voltage waveform L21 is about −4V, whereas the voltage swing of the output voltage waveform L22 is about −3.5 (V), and the voltage of the output voltage waveform L23 is The amplitude is about −3.0 (V), the voltage amplitude of the output voltage waveform L24 is about −2.0 (V), and the voltage amplitude of the output voltage waveform L25 is about −1.0 (V). ).

  That is, by applying a threshold voltage adjustment process to the TFT memories 21-1 to 21-n by applying a sufficiently higher voltage than when performing a normal switching operation, an output voltage is output when a normal switching operation is performed later. A so-called threshold drop occurs in which the value of.

  The present invention uses this threshold drop to set the voltage amplitude of the pulse waveform of the correction signal input to the voltage correction capacitances 22-1 to 22-n, so that the voltage correction capacitances 22-1 to 22-1 are set. The characteristic is that the voltage of the signal line is corrected via 22-n to correct display unevenness caused by variations in the feedthrough voltage.

  Here, mathematical expressions used to determine the voltage applied to the voltage correction capacitances 22-1 to 22-n and the capacitance values of the voltage correction capacitances 22-1 to 22-n will be described.

  The capacitance value of the voltage correction capacitance (for example, the voltage correction capacitance 22-k) is Cb (F), the capacitance value of the charge holding capacitance (for example, the charge holding capacitance 107-jk) is Cs (F), The capacitance value of the liquid crystal capacitance (for example, the liquid crystal capacitance 105-jk) is Clc (F), the capacitance value of the signal line (for example, the signal line 115-k) is Csl (F), and the voltage correction capacitance ( For example, when the voltage amplitude of the pulse waveform of the correction signal input to the voltage correction capacitance 22-k is ΔVb, the voltage correction amount (that is, the pixel electrode (for example, the signal line 115-k) of the signal line (for example, the signal line 115-k)). The voltage correction amount ΔV of the pixel electrode 104-jk) is obtained by the following equation (1).

ΔV = ΔVb × Cb / (Cb + Cs + Clc + Csl) (1)
For example, when the maximum value of the voltage correction amount ΔV is set to about 200 (mV) and the maximum value of the threshold adjustment amount of the threshold value of the TFT memory is set to about 5 (V), the pulse of the correction signal is set. The maximum value of the voltage swing width ΔVb of the waveform is about 5 (V), and the capacitance value Cs of the charge holding capacitance, the capacitance value Clc of the liquid crystal capacitance, and the capacitance value Csl of the signal line are known values. Therefore, the capacitance value Cb of the voltage correction capacitances 22-1 to 22-n is determined from the equation (1).

  In the signal line voltage correction method of the present embodiment, when the assembly of the display device is completed, first, a lighting inspection (inspection for displaying the same gradation on the entire surface and confirming display unevenness) is performed to obtain an inspection result. This inspection result is, for example, data obtained by digitizing the luminance of the pixel. Then, using this data, the luminance of the pixel where the display unevenness occurs and the reference luminance (here, the luminance of the darkest part of the pixels around the pixel where the display unevenness occurs) The difference is calculated, and the voltage correction amount ΔV is determined from the calculated difference and the luminance-voltage characteristic acquired in advance. Subsequently, the voltage correction amount ΔV, the capacitance value Cb of the voltage correction capacitance, the capacitance value Cs of the charge holding capacitance, the capacitance value Clc of the liquid crystal capacitance, and the capacitance value Csl of the signal line are obtained. Substituting into the equation (1), the voltage amplitude ΔVb of the pulse waveform of the correction signal is calculated. Further, a threshold adjustment amount for each signal line is determined according to the calculated voltage amplitude ΔVb, and threshold adjustment processing is performed.

  Next, a specific example of the signal line voltage correction method performed in the display device in which the threshold value adjustment processing of the TFT memory is performed for each signal line by the above method will be described.

  In the present embodiment, after the video signal voltage is written to the pixel electrode, the voltage applied to the TFT memory is changed to one level by changing the phase of the first correction drain signal DP1 and the phase of the second correction drain signal DP2. From one level to the other. In particular, in this specific example, a pixel for plus writing (a pixel in which the video signal SIG1 has a positive value with respect to the counter electrode voltage when the pixel TFT is turned on) is more effective than at the time of writing. However, the voltage is lower during the voltage correction process, and for negatively written pixels (pixels in which the video signal SIG1 is negative with respect to the counter electrode voltage when the pixel TFT is turned on). Thus, the phase of the first correction drain signal DP1 and the phase of the second correction drain signal DP2 are changed so that the voltage is higher during voltage correction than during writing.

  By using such first correction drain signal DP1 and second correction drain signal DP2, the display state of the pixel becomes darker as the voltage amplitude of the pulse waveform of the correction signal increases. That is, display unevenness can be improved by changing the display state in the direction of darkening. However, the liquid crystal layer is a normally black type.

  In other words, when the threshold adjustment amount of the TFT memories 21-1 to 21-3 is large, the first correction drain signal DP1 or the second correction drain signal input from the drain electrode side of the TFT memories 21-1 to 21-3. Since the drain signal DP2 greatly drops in the threshold values in the TFT memories 21-1 to 21-3, the drain signal DP2 hardly appears on the source electrode side of the TFT memories 21-1 to 21-3, and the TFT memories 21-1 to 21-21. The output of the correction signal from −3 to the voltage correction capacitances 22-1 to 22-3 becomes a very small value. As a result, the brightness of the pixel corresponding to the signal line connected to the TFT memory having a large threshold adjustment amount via the voltage correction capacitance is the input of the first correction drain signal DP1 or the second correction drain signal DP2. Despite this, it hardly changes.

  On the contrary, if threshold adjustment processing is not performed on the TFT memories 21-1 to 21-3, the first correction drain signal DP1 input from the drain electrode side of the TFT memories 21-1 to 21-3 or The second correction drain signal DP2 slightly drops in threshold value in the TFT memories 21-1 to 21-3, and then appears on the source electrode side of the TFT memories 21-1 to 21-3, and the TFT memories 21-1 to 21-21. -3 to the voltage correction capacitances 22-1 to 22-3 as a correction signal. Further, this correction signal is input to the voltage correction capacitances 22-1 to 22-3, and the voltages of the pixel electrodes 104-11 to 104-13 (see FIG. 6) according to the voltage amplitude ΔVb of the pulse waveform of the correction signal. The correction amount ΔV changes by an amount based on the above-described equation (1). Thus, the brightness of the pixel corresponding to the signal line connected to the TFT memory that has not been subjected to the threshold adjustment process via the voltage correction capacitance is determined by the first correction drain signal DP1 or the second correction drain signal. It changes in the direction of darkening according to the input of DP2.

  A specific example will be described with reference to FIG. 1. After the assembly of the display device is completed, first, a lighting inspection (inspection for displaying the same gradation on the entire surface and checking display unevenness) is performed. Here, as a result of this lighting inspection, the display of the pixel PIX11 corresponding to the first signal line 115-1 is dark, the display of the pixel PIX13 corresponding to the third signal line 115-3 is bright, and the second signal line. Assume that it is detected that the display of the pixel PIX12 corresponding to 115-2 has an intermediate brightness between the brightness of the pixel PIX11 and the brightness of the pixel PIX13.

  Subsequently, in order to improve the detected display unevenness, the signal line voltage correction method is performed using the signal line voltage correction unit 20 to perform threshold adjustment processing, and the TFT memory 21-1 and the TFT memory 21- 2 and the threshold value of the TFT memory 21-3 are adjusted to appropriate values. That is, for the TFT memory 21-1 corresponding to the first signal line 115-1 that causes dark display unevenness, the threshold adjustment processing is deeply performed so that the threshold adjustment amount becomes large. Thus, the threshold drop in the TFT memory 21-1 is increased. Thereby, the current brightness of the pixel PIX11 is maintained. Further, the threshold adjustment processing is shallow so that the threshold adjustment amount is small with respect to the TFT memory 21-3 corresponding to the third signal line 115-3 that causes the bright display unevenness. Thus, the threshold drop in the TFT memory 21-1 is reduced. Thereby, when the voltage of the first correction drain signal DP1 changes, the display state of the pixel PIX13 becomes dark to the same extent as the brightness of the pixel PIX11. Further, for the TFT memory 21-2 corresponding to the second signal line 115-2, which causes the display unevenness of the intermediate brightness, the threshold adjustment amount is the TFT memory 21-1. Threshold adjustment processing is performed so that the threshold adjustment amount with respect to and the threshold adjustment amount with respect to the TFT memory 21-3 are approximately intermediate. Thereby, when the voltage of the second correction drain signal DP2 changes, the display state of the pixel PIX12 becomes dark to the same extent as the brightness of the pixel PIX11.

  Next, an operation example after voltage correction of the display device of this embodiment will be described.

  Here, as an example of operation after voltage correction of the display device, an example of writing operation to the three pixels PIX11 to PIX13 will be described with reference to FIGS.

  FIG. 5 is a timing chart showing the first embodiment of the signal line voltage correction method of the present invention, in which the horizontal axis indicates time and the vertical axis indicates voltage. Note that the pixel electrode potential of the pixel PIX11 is pix11, the pixel electrode potential of the pixel PIX12 is pix12, and the pixel electrode potential of the pixel PIX13 is pix13.

  FIG. 6 is a partially enlarged view of the display device shown in FIG. 1 and shows portions related to three signal lines 115-1 to 115-3.

  More specifically, the timing chart of FIG. 5 shows an appropriate amount (threshold adjustment amount) for the TFT memory 21-1, the TFT memory 21-2, and the TFT memory 21-3 according to the display unevenness state of the display device. ) Of the display device after the threshold values of the TFT memory 21-1, the TFT memory 21-2, and the TFT memory 21-3 are respectively adjusted to optimum values. Explain.

  Further, FIG. 5A shows the correction gate signal GP output from the source driver 111 and input to the correction gate line 25a. The correction gate signal GP is a voltage signal applied to the gate electrodes of the TFT memory 21-1, the TFT memory 21-2, and the TFT memory 21-3. FIG. 5B shows the scanning line selection signal G1 output from the gate driver 113 and input to the first scanning line 116-1. FIG. 5C shows the selector signal SEL1 output from the control circuit 12 and input to the selector scanning line 124-1, and FIG. 5D shows the selector signal SEL1 output from the control circuit 12. 2 indicates the selector signal SEL2 input, and FIG. 5E illustrates the selector signal SEL3 output from the control circuit 12 and input to the selector scanning line 124-3. FIG. 5F shows the video signal SIG1 output from the first source driver output line 111-1 of the source driver 111. FIG. 5 (g) shows the first correction drain signal DP1 output from the control circuit 12 and input to the first correction signal line 25b1, and FIG. 5 (h) is output from the control circuit 12, The second correction drain signal DP2 input to the second correction signal line 25b2. 5 (i) shows the potential pix11 of the pixel electrode of the pixel PIX11, FIG. 5 (j) shows the potential pix12 of the pixel electrode of the pixel PIX12, and FIG. 5 (k) shows the potential pix13 of the pixel electrode of the pixel PIX13. Each broken line indicates the potential of the counter electrode 106. 5A to 5K are shown on the same time axis.

  In this embodiment, a P-type TFT is used as the TFT memory.

  When the display device displays an image after performing the threshold adjustment process described above, the gate driver 113 outputs the scanning line selection signal G1 output to the first scanning line 116-1 to the pixel TFT 103-11. The value is switched to a value that turns on a state of 103 to 13-13 (see FIG. 5B).

  Further, while the pixel TFTs 103-11 to 103-13 are in the ON state, the selector circuit SEL1 to SEL3 output to the selector scanning lines 124-1 to 124-3 by the control circuit 12 is sent to the selector switch TFT 114-1. ˜114-3 are sequentially switched to values that turn on (see FIG. 5C to FIG. 5E). At this time, the source driver 111 causes the video signal SIG1 to be written to the pixel PIX11 while the selector switch TFT 114-1 is on (to a voltage applied to the pixel electrode 104-11), and the selector switch TFT 114- 2 is set to a value written to the pixel PIX12 (to a voltage applied to the pixel electrode 104-12), while the selector switch TFT 114-3 is turned on to a value written to the pixel PIX13 ( The voltage is sequentially switched to the voltage applied to the pixel electrode 104-13 (see FIG. 5F). That is, in the selector switch unit 120, the on / off states of the three selector switch TFTs 114-1 to 114-3 are controlled by sequentially switching the selector signals SEL1 to SEL3 shown in FIGS. 5 (c) to 5 (d). Thus, the video signal SIG1 is distributed to the three signal lines 115-1 to 115-3.

  Thereby, the potential pix11 of the pixel electrode of the pixel PIX11 has a value corresponding to the image to be displayed, as shown in FIG. 5 (i), according to the voltage of the video signal SIG1 when the selector signal SEL1 is on. It has become. Further, the potential pix12 of the pixel electrode of the pixel PIX12 becomes a value corresponding to the video to be displayed as shown in FIG. 5 (j) in accordance with the voltage of the video signal SIG1 when the selector signal SEL2 is on. ing. Further, the potential pix13 of the pixel electrode of the pixel PIX13 becomes a value corresponding to the video to be displayed as shown in FIG. 5 (k) according to the voltage of the video signal SIG1 when the selector signal SEL3 is in the ON state. ing.

  Note that the display device of this embodiment uses a dot inversion method as a liquid crystal driving method. Therefore, as shown in FIGS. 5I to 5K, the polarities of the video signals input to the pixel electrodes 104-11 to 104-13 are reversed between adjacent pixels. .

  In the dot inversion driving method, the voltage for the positive writing pixel is lower during the voltage correction processing than during the writing, and for the negative writing pixel during the voltage correction processing than during the writing. As a correction drain signal input to each drain electrode of the TFT memory 21-1, the TFT memory 21-2, and the TFT memory 21-3 so that the voltage becomes higher, the first correction shown in FIG. The drain signal DP1 for use and the second correction drain signal DP2 shown in FIG. 5 (h) are used. Therefore, as the correction signal line connecting the control circuit 12 and the drain electrodes of the TFT memory 21-1, the TFT memory 21-2, and the TFT memory 21-3, the first correction shown in FIG. Two systems are prepared: a first correction signal line 25b1 to which the drain signal DP1 is input and a second correction signal line 25b2 to which the second correction drain signal DP2 shown in FIG. 5 (h) is input. Yes.

  Here, the first correction drain signal DP1 and the second correction drain signal DP2 are generated by the control circuit 12 at time T11 and time T12, which are timings when switching from the video signal writing to the pixel electrode to the voltage correction processing. The potential of is changed. As a result, the potentials pix11, pix12, and pix13 of the pixel electrodes of the pixels PIX11, PIX12, and PIX13 are equal to the value (voltage correction amount ΔV) calculated by the above equation (1) immediately after the time T11 and the time T12. Change.

  Here, as shown in FIG. 5 (i), the potential pix11 is equal to ΔV1, as shown in FIG. 5 (j), the potential pix12 is equal to ΔV2, and as shown in FIG. 5 (k), the potential pix13 is equal to ΔV3. Each changes. However, in the lighting inspection before the threshold adjustment process, the display of the pixel PIX11 corresponding to the first signal line 115-1 is dark, and the display of the pixel PIX13 corresponding to the third signal line 115-3 is bright. Since the display of the pixel PIX12 corresponding to the main signal line 115-2 is detected to have an intermediate brightness between the brightness of the pixel PIX11 and the brightness of the pixel PIX13, the above-described threshold adjustment processing is used. The threshold value of the TFT memory to be adjusted is adjusted in advance to an appropriate value. That is, the TFT memory 21-1 corresponding to the pixel PIX11 is deeply adjusted in threshold value, and adjusted so that the threshold value is higher than those of the other TFT memory 21-2 and TFT memory 21-3. Has been. Further, a moderate threshold value adjustment process is performed on the TFT memory 21-2 corresponding to the pixel PIX12, and the threshold value is medium compared with the other TFT memories 21-1 and 21-3. It has been adjusted to be. The TFT memory 21-3 corresponding to the pixel PIX13 is shallowly threshold-adjusted and adjusted so that the threshold value is lower than those of the other TFT memories 21-1 and 21-2. Yes.

  As a result of such threshold adjustment processing, the first correction drain signal DP1 or the second correction signal input to each drain electrode of the TFT memories 21-1 to 21-3 when performing display on the display device. The correction drain signal DP2 is input to the voltage correction capacitances 22-1 to 22-3 as a correction signal after the threshold value is dropped in the TFT memory 21-1, TFT memory 21-2 or TFT memory 21-3. Is done.

  Finally, the voltage correction amounts ΔV1, ΔV2, and ΔV3 of the potentials pix11, pix12, and pix13 due to the voltage change of the first correction drain signal DP1 and the second correction drain signal DP2 at time T11 are expressed by the following equation (1). ), ΔV3> ΔV2> ΔV1.

  That is, by appropriately adjusting the threshold value of the TFT memory, the brightness of the bright PIX 12 and PIX 13 can be matched with the brightness of the PIX 11 to correct display unevenness.

  As described above, according to the display device and the signal line voltage correction method of the present embodiment, even when there is display unevenness immediately after manufacturing, an appropriate threshold value adjustment process is applied to the TFT memory provided for each signal line. By performing the above, it is possible to obtain a display device that can correct and improve the line-shaped display unevenness. Accordingly, a display device that has been disposed of as a defective product based on the result of the inspection can be shipped as a non-defective product by correcting the voltage of the signal line. As a result, according to the present embodiment, it is possible to dramatically increase the manufacturing yield of the display device.

  In the display device according to the first embodiment, as shown in FIG. 2, in order to adjust the threshold value of the TFT memory 21-k by performing threshold value adjustment processing, the memory selection TFTs 23-k, Configuration for threshold adjustment processing such as a shift register 24-k and a plurality of pads (Gwrite pad 26a, Dwrite pad 26b1, Dwrite pad 26b2, Swrite pad 26c, TRG pad 26d and CLK pad 26e) for contacting prober needles Is provided. However, without providing such a configuration for threshold adjustment processing, when display unevenness occurs, ultraviolet rays or X-rays focused in a spot shape are applied to the TFT memory at a time and intensity according to the degree of the display unevenness. The threshold value of the TFT memory may be adjusted by selective irradiation. In this case, since it is not necessary to provide the threshold adjustment processing structure on the display panel, the area of the display panel can be greatly reduced, and the display device can be downsized.

  In the first embodiment, the case where a P-type TFT is used as the TFT memory has been described. However, an N-type TFT may be used instead of the P-type TFT.

  Further, when a good display can be obtained without performing the threshold adjustment process described in the first embodiment, the first correction drain signal DP1 and the second correction drain to be applied to the drain electrode of the TFT memory. The control circuit 12 may be configured so that the output of the signal DP2 can be stopped. In this case, power consumption during display of the display device can be reduced.

<Embodiment 2 of Display Device and Signal Line Voltage Correction Method>
First, since the second embodiment of the display device of the present invention has the same configuration as the display device shown in the first embodiment (see FIGS. 1, 2 and 6), a detailed description will be given here. Is omitted.

  Next, a signal line voltage correction method according to the present embodiment will be described.

  Compared with the signal line voltage correction method of the first embodiment, the signal line voltage correction method of the present embodiment is a first correction drain signal input to the drain electrodes of the TFT memories 21-1 to 21-n. The phase changes of the DP1 and the second correction drain signal DP2 are made different from each other. Like the signal line voltage correction method of the first embodiment described above, the so-called TFT memory 21-1 to 21-n is used. Using the threshold drop, the voltage amplitude of the pulse waveform of the correction signal input to the voltage correction capacitances 22-1 to 22-n is set for each signal line.

  Next, a specific example of the signal line voltage correction method of the present embodiment will be described with reference to FIG.

  However, here, for the sake of simplicity, three pixels (pixel PIX11) arranged at the intersection of one of the three signal lines 115-1 to 115-3 and the scanning line 116-1. ˜PIX13) will be described only.

  In the present embodiment, similarly to the above-described first embodiment, after the video signal voltage is written to the pixel electrode, the phase of the first correction drain signal DP1 and the phase of the second correction drain signal DP2 are changed. The voltage applied to the TFT memory is changed from one level to another level. However, in this specific example, the voltage is higher in the voltage correction process than in the writing process for the positive writing pixel, and the voltage correction process is more in the negative writing pixel than in the writing process. The first correction drain signal DP1 and the second correction drain signal DP2 whose phases are changed so that the voltage is lowered are used. The voltages of the first correction drain signal DP1 and the second correction drain signal DP2 are controlled by the control circuit 12.

  By using the first correction drain signal DP1 and the second correction drain signal DP2 as described above, the display state of the pixel becomes brighter as the voltage amplitude ΔVb of the correction signal increases. That is, display unevenness can be improved by changing the display state in the direction of brightening. However, the liquid crystal layer is a normally black type.

  In other words, when the threshold adjustment amount of the TFT memories 21-1 to 21-3 is large, the first correction drain signal DP1 or the second correction drain signal input from the drain electrode side of the TFT memories 21-1 to 21-3. Since the drain signal DP2 greatly drops in the threshold values in the TFT memories 21-1 to 21-3, the drain signal DP2 hardly appears on the source electrode side of the TFT memories 21-1 to 21-3, and the TFT memories 21-1 to 21-21. The output of the correction signal from −3 to the voltage correction capacitances 22-1 to 22-3 becomes a very small value. As a result, the brightness of the pixel corresponding to the signal line connected to the TFT memory having a large threshold adjustment amount via the voltage correction capacitance is the input of the first correction drain signal DP1 or the second correction drain signal DP2. Despite this, it hardly changes.

  On the contrary, if threshold adjustment processing is not performed on the TFT memories 21-1 to 21-3, the first correction drain signal DP1 input from the drain electrode side of the TFT memories 21-1 to 21-3 or The second correction drain signal DP2 slightly drops in threshold value in the TFT memories 21-1 to 21-3, and then appears on the source electrode side of the TFT memories 21-1 to 21-3, and the TFT memories 21-1 to 21-21. -3 to the voltage correction capacitances 22-1 to 22-3 as a correction signal. Further, this correction signal is input to the voltage correction capacitances 22-1 to 22-3, and the voltage correction amount ΔV of the pixel electrodes 104-11 to 104-13 is changed according to the voltage amplitude ΔVb of the pulse waveform of the correction signal. It changes by the amount based on the aforementioned equation (1). Thus, the brightness of the pixel corresponding to the signal line connected to the TFT memory that has not been subjected to the threshold adjustment process via the voltage correction capacitance is determined by the first correction drain signal DP1 or the second correction drain signal. It changes in the direction of brightening according to the input of DP2.

  As a specific example, after the assembly of the display device is completed, first, a lighting inspection (inspection for displaying the same gradation on the entire surface and checking display unevenness) is performed. Here, as a result of this lighting inspection, the display of the pixel PIX11 corresponding to the first signal line 115-1 is dark, the display of the pixel PIX13 corresponding to the third signal line 115-3 is bright, and the second signal line. Assume that it is detected that the display of the pixel PIX12 corresponding to 115-2 has an intermediate brightness between the brightness of the pixel PIX11 and the brightness of the pixel PIX13.

  Subsequently, in order to improve the detected display unevenness, the signal line voltage correction method is performed using the signal line voltage correction unit 20 to perform threshold adjustment processing, and the TFT memory 21-1 and the TFT memory 21- 2 and the threshold value of the TFT memory 21-3 are adjusted to appropriate values. That is, for the TFT memory 21-1 corresponding to the first signal line 115-1 that causes dark display unevenness, the threshold adjustment processing is shallow so that the threshold adjustment amount becomes small. Thus, the threshold drop in the TFT memory 21-1 is reduced. As a result, when the voltage of the first correction drain signal DP1 changes, the display state of the pixel PIX11 becomes as bright as the brightness of the pixel PIX13. Further, for the TFT memory 21-3 corresponding to the third signal line 115-3 that causes bright display unevenness, the threshold adjustment processing is deeply performed so that the threshold adjustment amount is increased. Thus, the threshold drop in the TFT memory 21-1 is increased. Thereby, the brightness of the pixel PIX13 is maintained. Further, for the TFT memory 21-2 corresponding to the second signal line 115-2, which causes the display unevenness of the intermediate brightness, the threshold adjustment amount is the TFT memory 21-1. Threshold adjustment processing is performed so that the threshold adjustment amount with respect to and the threshold adjustment amount with respect to the TFT memory 21-3 are approximately intermediate. Thereby, when the voltage of the second correction drain signal DP2 changes, the display state of the pixel PIX12 becomes brighter to the same degree as the brightness of the pixel PIX11.

  Next, an operation example after voltage correction of the display device of this embodiment will be described.

  Here, as an example of operation after voltage correction of the display device, an example of writing operation to the three pixels PIX11 to PIX13 will be described with reference to FIGS.

  FIG. 7 is a timing chart showing Embodiment 2 of the signal line voltage correction method of the present invention, in which the horizontal axis represents time and the vertical axis represents voltage. Note that the pixel electrode potential of the pixel PIX11 is pix11, the pixel electrode potential of the pixel PIX12 is pix12, and the pixel electrode potential of the pixel PIX13 is pix13.

  More specifically, the timing chart of FIG. 7 shows an appropriate amount (threshold adjustment amount) for the TFT memory 21-1, the TFT memory 21-2, and the TFT memory 21-3 according to the display unevenness state of the display device. ) Of the display device after the threshold values of the TFT memory 21-1, the TFT memory 21-2, and the TFT memory 21-3 are respectively adjusted to optimum values. Explain.

  Further, FIG. 7A shows the correction gate signal GP output from the source driver 111 and input to the correction gate line 25a. The correction gate signal GP is a voltage signal applied to the gate electrodes of the TFT memory 21-1, the TFT memory 21-2, and the TFT memory 21-3. FIG. 7B shows the scanning line selection signal G1 output from the gate driver 113 and input to the first scanning line 116-1. FIG. 7C shows the selector signal SEL1 output from the control circuit 12 and input to the selector scanning line 124-1, and FIG. 7D shows the selector signal SEL1 output from the control circuit 12. -2 shows the selector signal SEL2 inputted, and FIG. 7E shows the selector signal SEL3 outputted from the control circuit 12 and inputted to the selector scanning line 124-3. FIG. 7F shows the video signal SIG1 output from the first source driver output line 111-1 of the source driver 111. FIG. 7 (g) shows the first correction drain signal DP1 output from the control circuit 12 and input to the first correction signal line 25b1, and FIG. 7 (h) is output from the control circuit 12, The second correction drain signal DP2 input to the second correction signal line 25b2. 7 (i) shows the potential pix11 of the pixel electrode of the pixel PIX11, FIG. 7 (j) shows the potential pix12 of the pixel electrode of the pixel PIX12, and FIG. 7 (k) shows the potential pix13 of the pixel electrode of the pixel PIX13. Each broken line indicates the potential of the counter electrode 106. 7A to 7K are shown on the same time axis.

  In this embodiment, a P-type TFT is used as the TFT memory.

  When the display device displays an image after performing the threshold adjustment process described above, the gate driver 113 outputs the scanning line selection signal G1 output to the first scanning line 116-1 to the pixel TFT 103-11. The value is switched to a value that turns on a state of 103 to 13-13 (see FIG. 7B).

  Further, while the pixel TFTs 103-11 to 103-13 are in the ON state, the selector circuit SEL1 to SEL3 output to the selector scanning lines 124-1 to 124-3 by the control circuit 12 is sent to the selector switch TFT 114-1. ˜114-3 are sequentially switched to values that turn on (see FIG. 7C to FIG. 7E). At this time, the source driver 111 converts the video signal SIG1 into a value to be written to the pixel PIX11 (to a voltage applied to the pixel electrode 104-11) while the selector switch TFT 114-1 is in the ON state, and the selector switch TFT 114- 2 is set to a value written to the pixel PIX12 (to a voltage applied to the pixel electrode 104-12), while the selector switch TFT 114-3 is turned on to a value written to the pixel PIX13 ( The voltage is sequentially switched to the voltage applied to the pixel electrode 104-13 (see FIG. 7F). That is, in the selector switch unit 120, the on / off states of the three selector switch TFTs 1141-1 to 114-3 are controlled by sequentially switching the selector signals SEL1 to SEL3 shown in FIGS. 7 (c) to 7 (d). Thus, the video signal SIG1 is distributed to the three signal lines 115-1 to 115-3.

  Thereby, the potential pix11 of the pixel electrode of the pixel PIX11 has a value corresponding to the video to be displayed, as shown in FIG. 7 (i), according to the voltage of the video signal SIG1 when the selector signal SEL1 is on. It has become. Further, the potential pix12 of the pixel electrode of the pixel PIX12 becomes a value corresponding to the video to be displayed as shown in FIG. 7 (j) according to the voltage of the video signal SIG1 when the selector signal SEL2 is in the ON state. ing. Further, the potential pix13 of the pixel electrode of the pixel PIX13 has a value corresponding to the video to be displayed as shown in FIG. 7 (k) according to the voltage of the video signal SIG1 when the selector signal SEL3 is in the ON state. ing.

  Note that the display device of this embodiment uses a dot inversion method as a liquid crystal driving method. Therefore, as shown in FIG. 7 (i) to FIG. 7 (k), the polarity of the video signal input to each pixel electrode 104-11 to 104-13 is reversed between adjacent pixels. .

  In the dot inversion driving method, the voltage for the positive writing pixel is lower during the voltage correction processing than during the writing, and for the negative writing pixel during the voltage correction processing than during the writing. As a correction drain signal input to each drain electrode of the TFT memory 21-1, the TFT memory 21-2, and the TFT memory 21-3 so that the voltage becomes higher, the first correction shown in FIG. The drain signal DP1 for use and the second correction drain signal DP2 shown in FIG. 7 (h) are used. Therefore, as the correction signal line connecting the control circuit 12 and the drain electrodes of the TFT memory 21-1, the TFT memory 21-2, and the TFT memory 21-3, the first correction shown in FIG. Two systems of a first correction signal line 25b1 to which a drain signal DP1 for input is input and a second correction signal line 25b2 to which a second correction drain signal DP2 shown in FIG. 7 (h) is input are prepared. Yes.

  Here, the first correction drain signal DP1 and the second correction drain signal DP2 are generated by the control circuit 12 at time T11 and time T12, which are timings when switching from the video signal writing to the pixel electrode to the voltage correction processing. The potential of is changed. As a result, the potentials pix11, pix12, and pix13 of the pixel electrodes of the pixels PIX11, PIX12, and PIX13 are equal to the value (voltage correction amount ΔV) calculated by the above equation (1) immediately after the time T11 and the time T12. Change.

  Here, the potential pix11 is only ΔV1 as shown in FIG. 7 (i), the potential pix12 is ΔV2 as shown in FIG. 7 (j), and the potential pix13 is ΔV3 as shown in FIG. 7 (k). Each changes. However, in the lighting inspection before the threshold adjustment process, the display of the pixel PIX11 corresponding to the first signal line 115-1 is dark, and the display of the pixel PIX13 corresponding to the third signal line 115-3 is bright. Since the display of the pixel PIX12 corresponding to the main signal line 115-2 is detected to have an intermediate brightness between the brightness of the pixel PIX11 and the brightness of the pixel PIX13, the above-described threshold adjustment processing is used. The threshold value of the TFT memory to be adjusted is adjusted in advance to an appropriate value. In other words, the TFT memory 21-1 corresponding to the pixel PIX11 is shallowly subjected to threshold adjustment processing, and adjusted so that the threshold is lower than those of the other TFT memory 21-2 and TFT memory 21-3. Has been. Further, a moderate threshold value adjustment process is performed on the TFT memory 21-2 corresponding to the pixel PIX12, and the threshold value is medium compared with the other TFT memories 21-1 and 21-3. It has been adjusted to be. The TFT memory 21-3 corresponding to the pixel PIX13 is deeply adjusted in threshold value, and adjusted so that the threshold value is higher than those of the other TFT memory 21-1 and TFT memory 21-2. Yes.

  As a result of such threshold adjustment processing, the first correction drain signal DP1 or the second correction signal input to each drain electrode of the TFT memories 21-1 to 21-3 when performing display on the display device. The correction drain signal DP2 is input to the voltage correction capacitances 22-1 to 22-3 as a correction signal after the threshold value is dropped in the TFT memory 21-1, TFT memory 21-2 or TFT memory 21-3. Is done.

  Finally, the voltage correction amounts ΔV1, ΔV2, and ΔV3 of the potentials pix11, pix12, and pix13 due to the voltage change of the first correction drain signal DP1 and the second correction drain signal DP2 at time T11 are expressed by the following equation (1). ), ΔV1> ΔV2> ΔV3.

  That is, by appropriately adjusting the threshold value of the TFT memory, the brightness of the dark PIX11 and PIX12 can be matched with the brightness of the PIX13 to correct display unevenness.

  As described above, according to the display device and the signal line voltage correction method of the present embodiment, even when there is display unevenness immediately after manufacturing, an appropriate threshold value adjustment process is applied to the TFT memory provided for each signal line. By performing the above, it is possible to correct the line-shaped display unevenness and to obtain a display device that performs good display. Accordingly, a display device that has been disposed of as a defective product based on the result of the inspection can be shipped as a non-defective product by correcting the voltage of the signal line. As a result, according to the present embodiment, it is possible to dramatically increase the manufacturing yield of the display device.

  In the display device according to the above-described second embodiment, as shown in FIG. 2, in order to adjust the threshold value of the TFT memory 21-k by performing threshold value adjustment processing, the memory selection TFTs 23-k, For threshold adjustment processing such as a shift register 24-k and a plurality of pads (Gwrite pad 26a, Dwrite pad 26b1, Dwrite pad 26b2, Swrite pad 26c, TRG pad 26d, and CLK pad 26e) for contacting prober needles Is provided. However, without providing such a configuration for threshold adjustment processing, when display unevenness occurs, ultraviolet rays or X-rays focused in a spot shape are applied to the TFT memory at a time and intensity according to the degree of the display unevenness. The threshold value of the TFT memory may be adjusted by selective irradiation. In this case, since the configuration for the threshold adjustment process can be omitted, the area of the display panel can be greatly reduced, and the display device can be downsized.

  In the second embodiment, the case where a P-type TFT is used as the TFT memory has been described. However, an N-type TFT may be used instead of the P-type TFT.

  Further, when a good display can be obtained without performing the threshold adjustment process described in the second embodiment, the first correction drain signal DP1 and the second correction drain to be applied to the drain electrode of the TFT memory. The control circuit 12 may be configured so that the output of the signal DP2 can be stopped. In this case, power consumption during display of the display device can be reduced.

<One Embodiment of Signal Line Driver>
Next, an embodiment of a signal line driving unit of the present invention will be described with reference to the drawings.

  FIG. 8 is a block diagram showing an embodiment of the signal line driver of the present invention.

  In the first and second embodiments of the display device and the signal line voltage correction method described above, the signal line voltage correction unit 20 is formed in the display panel using TFTs. In contrast, in the present embodiment, as shown in FIG. 8, the signal line voltage correction unit 201 is formed in the same IC chip as the source driver 202. That is, the signal line drive unit 200 includes a signal line voltage correction unit 201 and a source driver 202 formed in the same IC chip. Furthermore, in the present embodiment, the signal line driver 200 includes a control circuit 203 having the same configuration and function as the control circuit 12 shown in FIG. 1, and the control circuit 203 is also the same IC as the source driver 202. It is formed in the chip.

  For example, when the source driver 202 is formed in an IC chip such as a driver IC, the TFT memories 21-1 to 21-n shown in FIG. By replacing 22-n with a MOS capacitance or the like formed on the semiconductor substrate, a signal line voltage correction unit 201 having the same configuration and function as the signal line voltage correction unit 20 described above is formed in the IC chip. be able to.

  In the present embodiment, as the threshold adjustment process, a high voltage is applied to the semiconductor memory element, and an electron injection process is performed in the floating gate of the semiconductor memory element, thereby adjusting the threshold value of the semiconductor memory. Correct the voltage of the signal line.

  According to the signal line driving unit of the present embodiment, even when there is display unevenness immediately after manufacturing, by performing appropriate threshold value adjustment processing on the semiconductor memory element provided for each signal line, a line-shaped display A display device that can correct and improve unevenness can be obtained. Accordingly, a display device that has been disposed of as a defective product based on the result of the inspection can be shipped as a non-defective product by correcting the voltage of the signal line. As a result, according to the present embodiment, it is possible to dramatically increase the manufacturing yield of the display device. Further, the signal line driving unit 200 such as an IC chip is externally attached to the general display panel without changing the configuration of the general display panel (for example, a display panel including a pixel array unit and a gate driver). Thus, a display device capable of correcting the voltage of the signal line can be obtained.

<Third embodiment of display device>
The display device of this embodiment is different from the display devices shown in Embodiments 1 and 2 described above in that the signal line voltage correction unit is externally attached to the display panel. For example, FIG. The signal line driving unit shown in FIG. 3 is externally attached to the display panel. Note that other configurations of the display device, signal line voltage correction method, and adjusting the threshold as necessary after confirming the display state are the same as in the first and second embodiments described above. Therefore, detailed description is omitted. Also in this embodiment, the voltage applied to the second switching element may be switched to the ON state only when correcting the voltage of the signal line.

  According to the display device of this embodiment, the same effects as those of the display devices described in the first and second embodiments can be obtained, and a general display panel (for example, a pixel array unit and a gate driver is provided). To obtain a display device capable of correcting the voltage of a signal line only by externally attaching a signal line driving unit 200 such as an IC chip to the general display panel without changing the configuration of the display panel) Can do.

  The display device, the signal line voltage correction method, and the signal line driver of the present invention can be used when display unevenness occurs in an active matrix display device.

12, 203 Control circuit 20, 201 Signal line voltage correction unit 21-1 to 21-n TFT memory 22-1 to 22-n Voltage correction capacitance 23-1 to 23-n Memory selection TFT
24-1 to 24-n Shift register 25a Correction gate line 25b1 First correction signal line 25b2 Second correction signal line 25c Correction source line 25d Correction start pulse line 25e Correction clock pulse line 26a Gwrite pad 26b1, 26b2 Dwrite pad 26c Swrite pad 26d TRG pad 26e CLK pad 100 Display panel 101 Pixel array unit 103-11 to 103-mn Pixel TFT
104-11 to 104-mn Pixel electrode 106 Counter electrode 111, 202 Source driver 111-1 to 111-n / 3 Source driver output line 113 Gate driver 114-1 to 114-n Selector switch TFT
115-1 to 115-n signal lines 116-1 to 116-m scanning lines 118 common electrodes 120, 204 selector switch sections 124-1 to 124-3 selector scanning lines 200 signal line driving section DP1 first correction drain signal DP2 Second correction drain signal G1 to Gm Scan line selection signal GP Correction gate signal PIX11 to PIXmn Pixels SIG1 to SIGn / 3 Video signal SEL1 to SEL3 Selector signal

Claims (18)

A first switching element electrically connected to the scanning line and the signal line, and a pixel array unit in which a plurality of pixels each including a pixel electrode electrically connected to the first switching element are arranged in an array; A display device comprising: a scanning line driving circuit that outputs an electrical signal that drives the scanning line; and a signal line driving circuit that outputs an electrical signal that drives the signal line.
A signal line voltage correction unit including a capacitive element electrically connected to the signal line and a second switching element electrically connected to the capacitive element; and the second switching element. A threshold value of the display device is variable. The display device according to claim 1,
By changing the voltage applied to the second switching element from one level to another level, the potential of the pixel electrode selected by the electric signal output from the scanning line driving circuit is changed to the threshold value. A display device that changes according to the condition. The display device according to claim 1 or 2,
The display device, wherein the second switching element is a thin film transistor. The display device according to claim 1, claim 2, or claim 3,
The display further includes a selector switch unit provided between the signal line driver circuit and the signal line, and the selector switch unit associates a plurality of signal lines with one output of the signal line driver circuit. apparatus. In the display device according to any one of claims 1 to 4,
The signal line voltage correction unit further includes a threshold adjustment unit that adjusts the threshold of the second switching element by electrically changing the threshold. The display device according to claim 5, wherein
The threshold adjustment means outputs a shift register that outputs an electrical signal in an on state at a timing for adjusting the threshold, and a second switching element at a timing when the electrical signal in an on state is output from the shift register. A display device comprising a third switching element for applying a voltage. In the display device according to any one of claims 1 to 6,
The threshold value of the second switching element is a display device that is adjusted according to the display state after confirming the display state of the display device. In the display device according to any one of claims 1 to 7,
A display device in which the number of the second switching elements is larger than the number of signal lines. In the display device according to any one of claims 1 to 8,
A display device in which the voltage applied to the second switching element is switched to an ON state only when the voltage of the signal line is corrected. A first switching element electrically connected to the scanning line and the signal line, and a pixel array unit in which a plurality of pixels each including a pixel electrode electrically connected to the first switching element are arranged in an array; ,
A scanning line driving circuit for outputting an electrical signal for driving the scanning line;
A signal line driving circuit for outputting an electrical signal for driving the signal line;
A capacitor element electrically connected to the signal line, and a signal line voltage correction unit including a second switching element electrically connected to the capacitor element;
The threshold value of the second switching element is variable,
The display array unit is provided in a display panel, and the signal line drive circuit and the signal line voltage correction unit are externally attached to the display panel. The display device according to claim 10.
By changing the voltage applied to the second switching element from one level to another level, the potential of the pixel electrode selected by the electric signal output from the scanning line driving circuit is changed to the threshold value. A display device that changes according to the condition. The display device according to claim 10 or 11,
The display device, wherein the second switching element is a semiconductor memory element. The display device according to claim 10, claim 11 or claim 12,
The signal line voltage correction unit further includes a threshold adjustment unit that adjusts the threshold of the second switching element by electrically changing the threshold. The display device according to claim 13,
The threshold adjustment means outputs a shift register that outputs an electrical signal in an on state at a timing for adjusting the threshold, and a second switching element at a timing when the electrical signal in an on state is output from the shift register. A display device comprising a third switching element for applying a voltage. The display device according to any one of claims 10 to 14,
The threshold value of the second switching element is a display device that is adjusted according to the display state after confirming the display state of the display device. The display device according to any one of claims 10 to 15,
A display device in which the voltage applied to the second switching element is switched to an ON state only when the voltage of the signal line is corrected. A first switching element electrically connected to the scanning line and the signal line, and a plurality of pixels each including a pixel electrode electrically connected to the first switching element. In the method of correcting the voltage,
The display device further includes a signal line voltage correction unit including a capacitive element electrically connected to the signal line and a second switching element electrically connected to the capacitive element,
The threshold value of the second switching element is variable,
A threshold adjustment procedure for adjusting a threshold by applying a voltage to the second switching element;
A signal line voltage correction method comprising: a voltage correction procedure for correcting a voltage of a signal line by outputting a signal for correcting a voltage corresponding to the adjusted threshold value from the second switching element to the capacitor element. A signal line driver circuit including a digital-analog converter that converts a digital signal into an analog signal and outputs the signal to a signal line, and one end of the signal line driver circuit is electrically connected to an output terminal of the signal line driver circuit and the signal line. A connected capacitive element, and a switching element electrically connected to the other end of the capacitive element,
A signal line driving unit in which a threshold value of the switching element is variable.

Images