JPH06204468A - Field-effect transistor - Google Patents

Abstract

PURPOSE:To relax electric field concentration near a drain and eliminate the device characteristic inhibiting causes by fixing the length of the part of a gate which faces the drain by the specific gate width ratio. CONSTITUTION:The conventional rectangle flat-shape of the gate 2 of a MOSFET with a gate length 0.5mum or shorter is changed and the width of a drain side gate 5 which faces a drain 3 is permitted to be 1.5 or more times wider than the width of a gate 4 which faces a source 1. Since electric field near the drain is relaxed, the gate length can be shortened compared with the field effect transistor of the conventional structure. Higher operation voltage can be applied by the electric field relaxation and high speed operation is allowed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a field effect transistor (FET) which is a main constituent element of LSI.

[0002]

2. Description of the Related Art A conventional FET has a structure in which a source and a drain of the same size sandwich a rectangular gate from both long sides thereof (for example, see "Semiconductor Device" (Industrial Books) by SMSze). See "MOSFET" section).

FIG. 5 shows its outline. Hereinafter, in the present specification, the horizontal direction of the paper in each of the cross-sectional views, that is, the direction of current flow is referred to as “horizontal”, and the vertical direction of the paper orthogonal to this is referred to as “vertical”. Further, when simply referred to as “length”, it means a length along the current, and when simply referred to as “width”, the length in the direction orthogonal to the current (for example, the plane of FIG. 5). (Length in the vertical direction of the paper surface in the figure).

[0004]

In the FET as shown in FIG. 5, although the structure is symmetrical with the gate 2 in between, when the operating voltage is applied between the source 1 and the drain 3, the drain 3 Concentration of electric field occurs in the vicinity of. FIG. 6 shows a result of simulating this state for an nMOSFET having a gate length of 0.5 μm. As the device simulator, S-PISCESIIB manufactured by Silvaco was used, and only the impurity concentration dependency was considered in the mobility model and only electrons were considered as carriers. The horizontal axis shows the spatial axis from the source to the drain, and the vertical axis shows the horizontal component of the electric field. Since the simulation assumes an n-channel FET, the electric field has a negative sign, but the electric field is concentrated near the drain. As will be described later, this electric field concentration becomes more remarkable as the gate length 7 becomes shorter. In FIG. 5, 4 indicates the source side gate width, and 5 indicates the drain side gate width, which are all equal to the gate width 6 which is the long side of the rectangular gate.

If the electric field is excessively concentrated, phenomena such as carrier acceleration exceeding the saturation speed or impact ionization are caused, which adversely affects the electrical characteristics of the device.
If the operating voltage is reduced in response to the reduction of the gate length, electric field concentration will not be a problem, but there are demands for noise countermeasures, high-speed operation, or compatibility with conventional devices.
The operating voltage cannot be extremely lowered. Therefore, as device miniaturization advances, the importance of electric field relaxation increases. In particular, in the most miniaturized MOSFET among various electronic devices, mitigation of electric field concentration is an unavoidable issue in the next-generation or next-generation devices.

Therefore, an object of the present invention is to alleviate the electric field concentration in the vicinity of the drain, which becomes conspicuous with the miniaturization of the device, and to eliminate the device characteristic inhibiting factors such as impact ionization due to the electric field concentration. is there.

[0007]

In order to solve the above-mentioned problems, in the field effect transistor of the present invention, the length of the portion of the gate facing the drain is 1 times the length of the portion of the gate facing the source. It is more than 5 times.

[0008]

The operation of the present invention will be described with reference to FIG. FIG. 2 schematically shows the electric flux just below the gate of the field effect transistor having the ring-shaped gate shown in FIG. In this specification, the length of the portion of the gate facing the drain and the length of the portion of the gate facing the source are referred to as the “drain side gate width” and the “source side gate width”, respectively. Further, the ratio of the drain side gate width to the source side gate width is defined as “gate width ratio”.

Taking the pMOSFET as an example, the electric flux entering the drain is equal to the electric flux 9 emerging from the source and the electric flux emerging from the charge 8 existing in the channel. If the charge distribution does not change, the gate width ratio can be made larger than "1" to reduce the density of the electric flux emitted from the source near the drain. Since the electric field is considered to have substantially the same meaning as the electric flux density, this method can prevent the electric field from being concentrated.

Also in the nMOSFET, the action of the electric field relaxation is the same except that the direction of the electric field is reversed.

[0011]

EXAMPLES The present invention will be described below with reference to examples. In these embodiments, parts corresponding to those of the conventional example shown in FIG.

Embodiment 1 FIG. 1 shows an example of the most typical MOSFET of the present invention in which the gate width ratio is "3". In the figure, 1 is a source, 2 is a gate, and 3 is a drain. The gate length 7 of this MOSFET is equal to the gate length 7 of the conventional MOSFET of FIG. The electrodes are omitted.

In Table 1 below, the gate length 7 of both is 1.0.
The maximum value of the horizontal component of the electric field immediately below the gate when the device simulation is performed for the case of 0 to 0.24 μm is collectively shown. In Table 1, the electric field relaxation rate is defined by 1- (maximum electric field in the present invention type) / (maximum electric field in the conventional type).

[0014]

[Table 1] Table 1 Maximum value of horizontal component of electric field (unit: kV / cm) ─────────────────────────────── ──── Gate length (μm) 1.00 0.70 0.50 0.34 0.24 ─────────────────────────── ──────── Conventional structure 174 185 200 233 275 Structure of the present invention 146 148 154 164 176 ─────────────────────────── ──────── Electric field relaxation rate (%) 16 20 23 30 36 ─────────────────────────────── ───

Table 1 shows that the electric field relaxation rate increases as the gate length decreases, and thus the effect of the present invention increases as the device size decreases. Although the MOSFET is taken as an example here, the effect of electric field relaxation is caused by the electric field spreading from the source to the drain, and is therefore considered to be the same in JFET.

Table 2 shows the contribution of the gate width ratio to the electric field relaxation rate when the gate length 7 is 0.50 μm.

[0017]

[Table 2] Table 2 Dependence of electric field relaxation rate on gate width ratio ─────────────────────────────── Gate width ratio 3 2 1.7 1.5 1.3 Electric field relaxation rate (%) 23 18 17 16 14 14 ─────────────────────────────── ──

As is obvious from the viewpoint of operation, it can be seen from Table 2 that the electric field relaxation effect is more remarkable as the gate width ratio is larger, and in particular, it is desired to obtain a relaxation effect of 15% or more. For example, it can be seen that a gate width ratio of 1.5 or more is necessary.

Embodiment 2 FIG. 3 shows an improved example of Embodiment 1 shown in FIG. In the FET of the first embodiment, wiring for the source 1 and the gate 2 is relatively difficult, but in the improved example of FIG. 3, the gate 2 has a semicircular shape to secure a wiring space for them.

As a matter of course, if a part of the circle is cut out, the wiring for the source 1 and the gate 2 is easy, so that the central angle of the gate 2 does not necessarily need to be 180 ° (half circle), and it is optional. Can be any angle. In that case, if the relationship between the outer diameter of the source 1 and the inner diameter of the drain 3 is the same as that of the first embodiment, the effect of alleviating the electric field is naturally the same as that of the first embodiment.

Embodiment 3 FIG. 4 shows an example in which the device of the present invention is constituted by only straight lines. If the CAD used to create the mask pattern does not have the arc drawing capability, the mask design is difficult with the configurations of the first and second embodiments. Further, when a large number of devices are densely arranged, useless space is increased in the configurations of the first and second embodiments. On the other hand, in this example, since the patterns are all composed of straight lines, the above-mentioned inconvenience does not occur.

Moreover, the gate width ratio becomes about 2.3, and the electric flux emitted from the source 1 spreads toward the drain 3 and exhibits the same electric field relaxation effect as that of the second embodiment. If the structure of this example is created in an actual LSI manufacturing process,
The corners are rounded due to the diffusion of the implanted impurities.
It has a similar structure to.

[0023]

According to the field effect transistor of the present invention, the electric field in the vicinity of the drain is relaxed, so that the gate length can be shortened as compared with the field effect transistor of the conventional structure. Further, since an operating voltage as high as the electric field is relieved can be adopted, high speed operation becomes possible.

[Brief description of drawings]

FIG. 1 is a schematic plan view and a sectional view showing a configuration of a field effect transistor according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing an electric flux just below a gate for explaining the operation of the present invention.

FIG. 3 is a schematic plan view of a field effect transistor according to a second embodiment of the present invention.

FIG. 4 is a schematic plan view of a field effect transistor according to a third embodiment of the present invention.

5A and 5B are a schematic plan view and a sectional view showing the configuration of a conventional field effect transistor.

6 is a graph showing the horizontal component of the electric field just below the gate of the field effect transistor of FIG.

[Explanation of symbols]

 1 Source 2 Gate 3 Drain 4 Source Side Gate Width 5 Drain Side Gate Width 6 Gate Width 7 Gate Length

Claims (1)

[Claims] 1. The field effect transistor, wherein the length of the portion of the gate facing the drain is 1.5 times or more the length of the portion of the gate facing the source.