JPH03209759A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH03209759A
JPH03209759A JP527390A JP527390A JPH03209759A JP H03209759 A JPH03209759 A JP H03209759A JP 527390 A JP527390 A JP 527390A JP 527390 A JP527390 A JP 527390A JP H03209759 A JPH03209759 A JP H03209759A
Authority
JP
Japan
Prior art keywords
contact window
current
contact
input terminal
window
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP527390A
Other languages
Japanese (ja)
Inventor
Yoshinobu Nishio
西尾 好伸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP527390A priority Critical patent/JPH03209759A/en
Publication of JPH03209759A publication Critical patent/JPH03209759A/en
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To relieve current density of a contact window when a current is biased in a specified window, and remarkably improve electrostatic breakdown strength, by making the contact hole, which a surge current passes, sufficiently large. CONSTITUTION:A contact window 15 has an area 4 times as large as the smallest contact window out of contact windows except the contact window group existing on input terminal nodes and the contact window group existing on transistor source nodes. When a surge being the transient negative maximum current is applied to an input terminal, a diffusion layer under polysilicon 14 forms a channel being the carrier path. A current flows from an aluminum wiring 11 connected with an input terminal to an aluminum wiring 12 of earth potential via the contact windows 15. Since the contact window which the surge current passes is as large as 4 times or more, the current density of a contact window is relieved even if the current is biased on a specified window. Hence the electrostatic breakdown strength is remarkably improved.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、静電破壊耐性の高いコンタクト窓形状の半導
体集積回路を有する半導体装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having a contact window-shaped semiconductor integrated circuit with high resistance to electrostatic discharge damage.

[従来の技術] 従来より、半導体集積回路の入出力部分には、静電破壊
耐性を得るために、保護回路が設けられている。以下に
従来の半導体集積回路の入力保護回路の1例について、
第2図に基づき説明する。
[Prior Art] Conventionally, a protection circuit has been provided in the input/output portion of a semiconductor integrated circuit in order to obtain resistance to electrostatic discharge damage. Below is an example of a conventional input protection circuit for a semiconductor integrated circuit.
This will be explained based on FIG.

第2図において、1は入力端子につながるアルミ配線、
2は接地電位のアルミ配線、3は拡散層、4はポリシリ
コン、5はコンタクト窓を示している。
In Figure 2, 1 is an aluminum wire connected to the input terminal,
Reference numeral 2 indicates an aluminum wiring at a ground potential, 3 a diffusion layer, 4 polysilicon, and 5 a contact window.

上記のように構成された半導体集積回路の入力保護回路
について、以下その動作を説明する。
The operation of the input protection circuit for the semiconductor integrated circuit configured as described above will be described below.

まず、入力端子(図示せず)に負の過渡的な最大電流で
あるサージが印加されたとき、ポリシリコン4の下の拡
散層はキャリアの通路であるチャネルを形成し、入力端
子につながっているアルミ配線1から接地電位のアルミ
配線2へ、コンタクト窓5を介して電流が生じる。
First, when a negative transient maximum current surge is applied to the input terminal (not shown), the diffusion layer under the polysilicon 4 forms a channel, which is a carrier path, and is connected to the input terminal. A current is generated from the aluminum wiring 1 at the ground potential to the aluminum wiring 2 at the ground potential through the contact window 5.

また、入力端子に正のサージが印加された時には、前述
と逆方向の経路で、コレクターエミッタ間電圧によって
エミッターベース間のエネルギー障壁が十分に下げられ
た際に生じるパンチスルー電流が流れる。
Furthermore, when a positive surge is applied to the input terminal, a punch-through current that occurs when the energy barrier between the emitter and the base is sufficiently lowered by the collector-emitter voltage flows in a path in the opposite direction to that described above.

従って、入力端子に印加されたサージは、入力保護回路
を通じて接地電位のアルミ配線2へ流れ込むことができ
るため、内部回路は保護される。
Therefore, the surge applied to the input terminal can flow into the aluminum wiring 2 at ground potential through the input protection circuit, so that the internal circuit is protected.

出力保護回路も同様にして、出力端子ノードをドレイン
とするトランジスタの前記パンチスルー電流によって、
サージが接地電位のアルミ配線2、または電源電圧電位
のアルミ配線へ流れ込むことができるため、内部回路が
保護される。
Similarly, in the output protection circuit, due to the punch-through current of the transistor whose drain is the output terminal node,
Since the surge can flow into the aluminum wiring 2 at ground potential or the aluminum wiring at power supply voltage potential, the internal circuit is protected.

[発明が解決しようとする課題] しかしながら、従来の半導体集積回路の構成では、近年
のパターン・ルールの微細化に伴い、サージが通過する
コンタクト窓の面積が小さくなり、かつそれぞれのコン
タクト窓は全て対称的な位置関係にあるのではないため
、入出力端子と同一ノードにあるコンタクト窓群、また
はこのノードをドレインとするトランジスタのソースと
同一ノードにあるコンタクト窓群のうちの、ある特定の
コンタクト窓に電流が偏りやすく、前記特定のコンタク
ト窓が破壊しやすいという課題を有してきた。
[Problems to be Solved by the Invention] However, in the configuration of conventional semiconductor integrated circuits, with the miniaturization of pattern rules in recent years, the area of contact windows through which surges pass has become smaller, and each contact window is Because they are not in a symmetrical positional relationship, a certain contact among the contact windows that are on the same node as the input/output terminal, or the contact window group that is on the same node as the source of the transistor whose drain is this node. There has been a problem in that the current tends to be biased toward the window, and the specific contact window is easily destroyed.

本発明はこのような従来技術の′課題を解決するもので
、静電破壊耐性の高いコンタクト窓形状を有する半導体
集積回路を提供することを目的とするものである。
The present invention solves the problems of the prior art, and aims to provide a semiconductor integrated circuit having a contact window shape with high resistance to electrostatic discharge damage.

[課題を解決するための手段] 前記目的を達成するため、本発明は下記の構成からなる
。すなわち本発明は、入力端子若しくは出力端子と同一
ノードにあるコンタクト窓群、または前記入力端子若し
くは出力端子のノードをドレインとするトランジスタの
ソースと同一ノードにあるコンタクト窓群のうち、いず
れかあるいは全部が前記の全コンタクト窓群以外のコン
タクト窓のなかで最小の面積のコンタクト窓の面積の4
倍以上の面積を持つことを特徴とする半導体装置である
[Means for Solving the Problems] In order to achieve the above object, the present invention has the following configuration. In other words, the present invention provides a contact window group located at the same node as an input terminal or an output terminal, or a contact window group located at the same node as a source of a transistor whose drain is the node of the input terminal or output terminal, or all of them. is the area of the contact window with the smallest area among the contact windows other than all the contact windows mentioned above.
This is a semiconductor device characterized by having an area more than twice as large.

[作用] 上記した本発明の構成によれば、サージ電流の通過する
コンタクト窓が十分に大きいために、電流がある特定の
コンタクト窓に偏ってもコンタクト窓の電流密度は緩和
され、静電破壊耐性は大幅に高いものとなる [実施例] 以下、一実施例を用いて本発明をさらに具体的に説明す
る。なお本発明は下記の一実施例に限定されるものでは
ない。
[Function] According to the configuration of the present invention described above, since the contact window through which the surge current passes is sufficiently large, even if the current is biased toward a certain contact window, the current density in the contact window is relaxed, and electrostatic damage is prevented. The resistance is significantly higher [Example] The present invention will be explained in more detail below using an example. Note that the present invention is not limited to the following example.

第1図は、本発明の一実施態様を示すものである。すな
わち第1図は本発明にかかる半導体集積回路の平面図で
あり、11は入力端子につながるアルミ配線、12は接
地電位のアルミ配線、13は拡散層、14はポリシリコ
ン、15はコンタクト窓を示している。
FIG. 1 shows one embodiment of the present invention. That is, FIG. 1 is a plan view of a semiconductor integrated circuit according to the present invention, in which 11 is an aluminum wiring connected to an input terminal, 12 is an aluminum wiring at ground potential, 13 is a diffusion layer, 14 is polysilicon, and 15 is a contact window. It shows.

該コンタクト窓15は、上記入力端子のノードにあるコ
ンタクト窓群、あるいは入力端子のノードをドレインと
するトランジスタのソースのノードにあるコンタクト窓
群以外のコンタクト窓の中で最小の面積のコンタクト窓
の面積の4倍以上の面積を持つとする。
The contact window 15 has the smallest area among the contact windows other than the contact window group located at the node of the input terminal or the contact window group located at the source node of the transistor whose drain is the input terminal node. It is assumed that the area is more than four times the area of the area.

以上のように構成された入力保護回路について、次にそ
の動作を説明する。
Next, the operation of the input protection circuit configured as described above will be explained.

まず、入力端子(図示せず)に負の過渡的な最大電流で
あるサージが印加されたとき、ポリシリコン14の下の
拡散層はキャリアの通路であるチャネルを形成し、入力
端子につながっているアルミ配線11から接地電位のア
ルミ配線12へ、コンタクト窓15を介して電流が生じ
る。
First, when a negative transient maximum current surge is applied to the input terminal (not shown), the diffusion layer under the polysilicon 14 forms a channel, which is a carrier path, and is connected to the input terminal. A current is generated through the contact window 15 from the aluminum wiring 11 at the ground potential to the aluminum wiring 12 at the ground potential.

また、入力端子に正のサージが印加された時には、前述
と逆方向の経路で、コレクターエミッタ間電圧によって
エミッターベース間のエネルギー障壁が十分に下げられ
た際に生じるパンチスルー電流が流れる。
Furthermore, when a positive surge is applied to the input terminal, a punch-through current that occurs when the energy barrier between the emitter and the base is sufficiently lowered by the collector-emitter voltage flows in a path in the opposite direction to that described above.

従って、入力端子に印加されたサージは、入力保護回路
を通じて接地電位のアルミ配線12へ流れ込むことがで
きるため、内部回路は保護される。
Therefore, the surge applied to the input terminal can flow into the aluminum wiring 12 at ground potential through the input protection circuit, so that the internal circuit is protected.

出力保護回路も同様にして、出力端子ノードをドレイン
とするトランジスタの前記パンチスルー電流によって、
サージが接地電位のアルミ配線12、または電源電圧電
位のアルミ配線11へ流れ込むことができるため、内部
回路が保護される。、そして、サージ電流の通過するコ
ンタクト窓が4倍以上と十分に大きいために、電流があ
る特定のコンタクト窓に偏ってもコンタクト窓の電流密
度は緩和され、静電破壊耐性は大幅に高いものとなる。
Similarly, in the output protection circuit, due to the punch-through current of the transistor whose drain is the output terminal node,
Since the surge can flow into the aluminum wiring 12 at ground potential or the aluminum wiring 11 at power supply voltage potential, the internal circuit is protected. And, since the contact window through which the surge current passes is sufficiently large, at least four times as large, even if the current is biased toward a specific contact window, the current density in the contact window is relaxed, and the resistance to electrostatic damage is significantly high. becomes.

これに対して、サージ電流の通過するコンタクト窓が4
倍未満であっては、電流がある特定のコンタクト窓に偏
り易く、コンタクト窓の電流密度が超過して破壊してし
まう傾向となり、好ましくない。
On the other hand, the contact window through which the surge current passes is 4.
If it is less than twice that, the current tends to be concentrated in a certain contact window, and the current density of the contact window tends to exceed and destroy it, which is not preferable.

尚、本発明の実施例では入力保護回路を例にとったが、
出力保護回路についても同様に適用される。
In the embodiment of the present invention, an input protection circuit is taken as an example, but
The same applies to output protection circuits.

[発明の効果] 以上のように本発明によれば、サージ電流の通過するコ
ンタクト窓が十分に大きいために、電流がある特定のコ
ンタクト窓に偏ってもコンタクト窓の電流密度は緩和さ
れ、静電破壊耐性は大幅に高いものとなるという効果を
達成できる。
[Effects of the Invention] As described above, according to the present invention, the contact window through which the surge current passes is sufficiently large, so even if the current is biased toward a certain contact window, the current density in the contact window is relaxed, and the current density in the contact window is relaxed. It is possible to achieve the effect that electrical breakdown resistance is significantly increased.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例にかかる半導体集積回路の平
面図、第2図は従来例を示す平面図である。 1.11・・・入力端子につながるアルミ配線2・・・
接地電位のアルミ配線 3・・・拡散層 4・・・ポリシリコン 5・・・コンタクト窓 第1図 第2図
FIG. 1 is a plan view of a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 2 is a plan view showing a conventional example. 1.11... Aluminum wiring connected to input terminal 2...
Aluminum wiring at ground potential 3...Diffusion layer 4...Polysilicon 5...Contact window Fig. 1 Fig. 2

Claims (1)

【特許請求の範囲】[Claims] (1)入力端子若しくは出力端子と同一ノードにあるコ
ンタクト窓群、または前記入力端子若しくは出力端子の
ノードをドレインとするトランジスタのソースと同一ノ
ードにあるコンタクト窓群のうち、いずれかあるいは全
部が前記の全コンタクト窓群以外のコンタクト窓のなか
で最小の面積のコンタクト窓の面積の4倍以上の面積を
持つことを特徴とする半導体装置。
(1) Any or all of the contact windows located at the same node as the input terminal or output terminal, or the contact windows located at the same node as the source of the transistor whose drain is the node of the input terminal or output terminal, A semiconductor device characterized in that the semiconductor device has an area that is four times or more the area of the smallest contact window among the contact windows other than all the contact window groups.
JP527390A 1990-01-11 1990-01-11 Semiconductor device Pending JPH03209759A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP527390A JPH03209759A (en) 1990-01-11 1990-01-11 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP527390A JPH03209759A (en) 1990-01-11 1990-01-11 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH03209759A true JPH03209759A (en) 1991-09-12

Family

ID=11606626

Family Applications (1)

Application Number Title Priority Date Filing Date
JP527390A Pending JPH03209759A (en) 1990-01-11 1990-01-11 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH03209759A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5477407A (en) * 1993-12-17 1995-12-19 Fujitsu Limited Protection circuit for protecting a semiconductor device from a voltage surge

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5477407A (en) * 1993-12-17 1995-12-19 Fujitsu Limited Protection circuit for protecting a semiconductor device from a voltage surge

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