JPH0619323U - Timing adjustment circuit with differential gate - Google Patents

Abstract

(57) [Abstract] [Purpose] The output of the output differential gate 4 is input to the differential gate 2
Adjust with half the resolution of the delay time of. [Structure] A plurality of input differential gates 2 are cascade-connected to sequentially delay differential signals. The selector 3 inputs the first outputs of the plurality of input differential gates 2, respectively. The output differential gate 4 has the output of the selector 3 as a first input and one of the second outputs of the plurality of input differential gates 2 as a second input. The output timing of the output differential gate 4 is adjusted by selecting one of the first outputs of the plurality of input differential gates 2 by the selector 3.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a timing adjustment circuit that uses the delay time of cascaded differential gates.

[0002]

[Prior art]

 In the IC tester, a test pattern is added to the IC to be tested, and the quality of the IC is judged by the response signal. Next, the configuration of the IC tester will be described with reference to FIG. In FIG. 4, 21 is a pattern generator for generating a test pattern, 22 and 23 are timing adjustment circuits, 24 and 25 are drivers, 26 is an IC to be tested, and 27 and 28 are lines. When the test patterns are sent from the drivers 24 and 25 through the lines 27 and 28, the lines 27 and 28 cause a transmission delay, so the timing adjustment circuits 22 and 23 adjust the timing of the test patterns.

A test pattern is sent from the pattern generator 1 to the drivers 24 and 25 by a differential signal which will be described later, and a normal on / off signal is applied to the IC 26 from the drivers 24 and 25. The transmission delay caused by the lines 27 and 28 is corrected by the timing adjusting circuits 22 and 23.

Next, the configuration of the timing adjustment circuit according to the conventional technique will be described with reference to FIG. In FIG. 5, 1A and 1B are input terminals, 2A to 2D are cascaded input differential gates, 3A to 3D are AND gates, 3E is a control signal generator, 3F is an OR gate, 4 is an output differential gate, and 5A. And 5B are output terminals. The AND gates 3A to 3D, the control signal generator 3E and the OR gate 3F form the selector 3. The operation of the differential gate is also described in, for example, Japanese Patent Application Laid-Open No. 2-253715.

Differential signals are input to the input differential gates 2A to 2D from the input terminals 1A and 1B of FIG. The differential signal is delayed by a fixed time each time it passes through the input differential gates 2A to 2D. In FIG. 5, the input differential gates 2A to 2D are configured in four stages, but other than four stages may be used.

The first outputs of the input differential gates 2A to 2D are input to the AND gates 3A to 3D, respectively. The outputs of the AND gates 3A to 3D are selected by the control signal generator 3E and input to the OR gate 3F. The output of the OR gate 3F is input to the first input of the output differential gate 4, and V _BB is input to the second input. The "H" level and the "L" level of the first input are inverted, and the delayed differential signal is output from the output terminals 5A and 5B.

Next, the waveform of each part of FIG. 5 will be described with reference to FIG. FIG. 6A shows a signal waveform supplied to the input terminal 1A, which changes from the "L" level to the "H" level. 6A shows a signal waveform supplied to the input terminal 1B, which is an inverted signal of FIG. 6A. FIG. 6C shows the waveform of the first output of the input differential gate 2A, which is output with a delay time ΔT1 with respect to the waveform of FIG. 6A. FIG. 6D shows the waveform of the second output of the input differential gate 2A, which is output with a delay of time ΔT1 from the waveform of FIG. 6A.

FIG. 6E shows an input waveform of the input differential gate 2A. Since the signals of FIGS. 6A and 6A are simultaneously input to the input of the input differential gate 2A, the waveforms of FIGS. 6A and 6A are combined. FIG. 6 shows the output waveform of the input differential gate 2A. In the input differential gate 2A, the level of the differential signal is inverted between the “H” level and the “L” level, and the output signal is also inverted. Since it is output, the waveform is a combination of the waveforms of FIG. 6C and FIG.

FIG. 6C shows the output waveform of the input differential gate 2B, and the signal is delayed by ΔT2 from FIG. 6C. FIG. 6C shows the output waveform of the input differential gate 2C, and the signal is delayed by ΔT3 from FIG. 6C. FIG. 6C shows the output waveform of the input differential gate 2D, and the signal is delayed by ΔT 4 from FIG. Therefore, the signal of the output of the input differential gate 2D is delayed by ΔT1 + ΔT2 + ΔT3 + ΔT4 from FIG. For example, if the delay times ΔT1 to ΔT4 are set to 1 ns, the output of the input differential gate 2D lags behind the differential signals of the input terminals 1A and 1B by 4 ns.

By selecting the output of the input differential gates 2A to 2D by the output of the control signal generator 3E, the differential signal can be taken out from the output differential gate 4 by changing the delay time. In FIG. 5, the delay time of the AND gates 3A to 3D and the OR gate 3F is not taken into consideration.

[0011]

[Problems to be solved by the device]

In the configuration of FIG. 5, since the differential signal is delayed by the delay time of the input differential gates 2A to 2D, the time width of timing adjustment cannot be set to the delay time or less. Also, the output differential gate 4 can adjust the output timing by raising or lowering the level of V _BB of the second input, but in this case, the pulse width of the output changes.

According to the present invention, the first outputs of the plurality of input differential gates 2 are respectively used as the inputs of the selector 3, and the outputs of the selector 3 are used as the first inputs of the output differential gate 4. One of the second outputs of the output differential gate 4 is used as the second input of the output differential gate 4 and one of the first outputs of the input differential gate 2 is selected by the selector 3. An object is to provide a timing adjustment circuit that adjusts the output timing.

[0013]

[Means for Solving the Problems]

 In order to achieve this object, in the present invention, a plurality of input differential gates 2 connected in cascade and sequentially delaying a differential signal, and a first output of each of the plurality of input differential gates 2 are input. A selector 3 and an output differential gate 4 having an output of the selector 3 as a first input and one of a plurality of inputs of a second output of the differential gate 2 as a second input. The output timing of the output differential gate 4 is adjusted by selecting one of the first outputs of the plurality of input differential gates 2 by.

[0014]

[Action]

Next, the structure of the timing adjusting circuit according to the present invention will be described with reference to FIG. In FIG. 1, the first output of the input differential gates 2A and 2B is taken out by the selector 3 and used as the first input of the output differential gate 4, which is the same as in FIG. The difference between FIG. 1 and FIG. 5 is that V _BB is applied to the second input of the output differential gate 4 in FIG. 5, whereas the second output of the input differential gates 2A and 2B is shown in FIG. One of them is the second input of the output differential gate 4. In FIG. 1, the second output of the input differential gate 2A is input to the second input of the output differential gate 4.

Next, the input / output waveform of the output differential gate 4 will be described with reference to FIG. 2A shows the input waveform of the output differential gate 4, and the rising signal 13 is the second output signal of the input differential gate 2A. The falling signals 14 and 15 are the first outputs of the input differential gates 2A and 2B selected by the selector 3, and the time difference between the signals 14 and 15 is ΔT.

FIG. 2A shows an output waveform of the output differential gate 4. When the level of the differential input signal is inverted, the output differential gate 4 inverts and outputs the output signal. Therefore, the output differential gate 4 outputs the signal at the intersection of the signal 13 and the signals 14 and 15 in FIG. To do. The output of the input differential gates 2A and 2B selected by the selector 3 changes the intersection of FIG. At this time, the time difference between the intersections is half of ΔT. That is, the output of the output differential gate 4 can be adjusted with a resolution of half the delay time of the input differential gates 2A and 2B.

Next, a configuration diagram of the embodiment shown in FIG. 1 will be described with reference to FIG. 3 corresponds to FIG. 5, and 6 in FIG. 3 is a delay element for correcting the delay time of the selector 3. For example, if the delay times ΔT1 to ΔT4 of the input differential gates 2A to 2D in FIG. 3 are set to 1 ns, the output of the output differential gate 4 can be timing adjusted at intervals of 0.5 ns. It goes without saying that the circuit of FIG. 1 can be used as a delay circuit other than the timing adjustment circuit of the IC tester of FIG.

[0018]

[Effect of device]

 According to this invention, the first output of the plurality of input differential gates is used as the input of the selector, the selector output is used as the first input of the output differential gate, and the second output of the input differential gate is One of them is used as the second input of the output differential gate, and one of the first outputs of the input differential gate is selected by the selector. Therefore, the output of the output differential gate is half the delay time of the input differential gate. It can be adjusted by resolution.

[Brief description of drawings]

FIG. 1 is a block diagram of a timing adjustment circuit according to the present invention.

FIG. 2 is an input / output waveform diagram of the output differential gate 4 of FIG.

FIG. 3 is a configuration diagram of the embodiment of FIG.

FIG. 4 is an explanatory diagram of a configuration of an IC tester.

FIG. 5 is a configuration diagram of a timing adjustment circuit according to a conventional technique.

FIG. 6 is a waveform diagram for explaining the operation of FIG.

[Explanation of symbols]

 1A / 1B input terminal 2A-2D input differential gate 3 selector 4 output differential gate 5A / 5B output terminal

Claims (1)

[Scope of utility model registration request] 1. A plurality of input differential gates (2) that are connected in cascade and sequentially delay differential signals, and a selector (3) that receives the first outputs of the plurality of input differential gates (2), respectively. And an output differential gate (4) having the output of the selector (3) as the first input and one of the second outputs of the plurality of input differential gates (2) as the second input. The output differential gate (4) is provided by selecting one of the first outputs of the plurality of input differential gates (2) by the selector (3).
Adjusting circuit with a differential gate, which adjusts the timing of the output of the.