JPH06189113A - Image reader - Google Patents

Abstract

PURPOSE:To obtain an image reader capable of remarkably reducing the omission of both black data and white data and obtaining an image with low deterioration of resolution as the image reader. CONSTITUTION:The image reader is equipped with an image processing circuit which outputs by reading an image signal of one line sequentially, a binarization signal storage memory 3a which fetches the output of the image processing circuit at every other plural lines and stores binarization signals by plural lines, operation result storage memory 3b, 3c which store operation results by plural lines, and an arithmetic means 4 which performs the arithmetic operation of operation results fetched in the operation result storage memory, the binarization signals before plural lines, and the binary signal on the present line. Also, this device is composed in such a manner that the operation result by the arithmetic means 4 is set as the output of the image processing circuit and the operation result by the arithmetic means can be stored in the operation result storage memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image reading device,
Specifically, it can be applied to a linear density conversion method in an image reading apparatus such as a fax machine or a scanner, which converts a plurality of lines of data into one line of data, a method of converting from two pixel data into one pixel data, and the like. In particular, the present invention relates to an image reading apparatus capable of obtaining an image with less deterioration in resolution by reducing loss of both black data and white data.

[0002]

2. Description of the Related Art In a conventional image reading apparatus, a linear density conversion method, particularly when performing thinning processing such as reduction,
For example, there is one reported in Japanese Patent Application Laid-Open No. 1-152868, in which the logical OR is performed with an adjacent pixel or an adjacent line in order to prevent loss of black data.

[0003]

However, in the conventional image reading apparatus as described above, there is an advantage that black data loss can be prevented by taking the logical sum of the adjacent pixels or the adjacent lines. There is a problem in that the loss cannot be prevented, the white data is lost, and as a result, the image becomes a crushed image as a whole (FIGS. 6A, 6C, and 6D). ) And FIG. 7).

Therefore, there is a conventional image reading apparatus which solves the above-mentioned problem, for example, one disclosed in Japanese Patent Publication No. Sho 60-31421. In this case, when white data and black data are mixed, white is read. The data different from the immediately preceding pixel is output so that the data and the black data are averaged and output.
However, this conventional image reading apparatus has an advantage that the image crushing can be suppressed to some extent by outputting the white data and the black data as an average as much as possible. However, there is a problem in that the resolution is degraded (see FIGS. 6A, 6B and 7).

Therefore, an object of the present invention is to provide an image reading apparatus capable of extremely reducing black data loss and white data loss and obtaining an image with little deterioration in resolution.

[0006]

The invention according to claim 1 is
An image processing circuit that reads an image signal of one line and sequentially outputs the image signal, and an image reading device that takes in the output of the image processing circuit every plural lines, a binarized signal storage memory that stores binarized signals for a plurality of lines And a calculation result storage memory for storing calculation results for a plurality of lines, a calculation result fetched by the calculation result storage memory, a binarized signal before a plurality of lines, and a binarized signal for the current line. And a calculation unit configured to output the calculation result of the calculation unit as an output of the image processing circuit, and to store the calculation result of the calculation output unit in the calculation result storage memory. To do.

According to a second aspect of the invention, in the invention according to the first aspect, when data is captured every other line,
The calculation result of the second previous line L 'and _n-2, a binary signal of the previous line and L _n, and a binary signal of the current line and _{L n + 1, L n'} = L n + 1 + L n・ L ' _n-2 bar (however, L'
_{The n-2} bar has a logical operation means for performing a logical operation of L' _n-2 which is the inversion result of L' _n-2 .

According to a third aspect of the present invention, in an image reading apparatus for reading an image signal of one line, converting two adjacent pixel data into one pixel data and outputting the pixel data, a binarized signal for one pixel is output. Binary signal storage register to store, operation result storage register to store operation result for two pixels, operation result data of previous pixel, binary signal of previous pixel, and binary signal of current pixel And a calculation means for performing
The calculation result by the calculation means is stored in the calculation result storage register, and the calculation result by the calculation output means is output every other pixel.

The invention according to claim 4 is the above claim 3.
In the present invention, the calculation result of the pixel before the pixel is L '._n-2age,
L the binary signal of the current pixel_{n + 1}And the binary signal of the previous pixel
To L _nAnd L_n′ = L_{n + 1}+ L_n・ L_n-2Bar (but
And L '_n-2The bar is L '_n-2Is the inversion result of
It is also characterized by having a logical operation means for performing a logical operation.
Of.

[0010]

According to the first aspect of the invention, the binarized signals for a plurality of lines are stored, the operation results for a plurality of lines are stored, and the fetched operation results, the binarized signals before a plurality of lines, and the present value are stored. It is possible to perform an operation with the binarized signal of the line, output the operation result to the image processing circuit, and store the operation result in the operation result storage memory. For this reason, it is possible to appropriately determine the processing of the data to be captured next based on the data of the previous line that has actually been captured, so that it is possible to extremely reduce both black data and white data loss and to reduce resolution degradation. Images can be obtained.

According to the second aspect of the invention, when the data is fetched every other line, the calculation result of the line before the previous line is L' _n-2.
And the binarized signal of the previous line is L _n, and 2 of the current line
The binarized signal is L _{n + 1,} and L _n ′ = L _{n + 1} + L _n · L ′
It is possible to perform a logical operation of _n-2 bar (however, L' _n-2 bar is the inversion result of L' _n-2 ). Therefore, if the data of the previous line that has been actually captured is black, the data of the next line that is empty is output as it is, and if the data of the previous line that has been captured is white, the logical sum of the next two lines is calculated. Since the data can be output, it is possible to obtain data in which black data and white data are extremely missing, and it is possible to obtain an image with little deterioration in resolution.

According to the third aspect of the present invention, the binarized signal for one pixel is stored, the operation result for two pixels is stored, and the operation result data of the pixel before the preceding pixel, the binarized signal of the previous pixel, and the present signal are stored. 2 of pixels
It is possible to perform an operation with the binarized signal, store the operation result in the operation result storage register, and output the operation result every other pixel. For this reason, it is possible to appropriately determine the processing of the data to be captured next based on the data of the previous pixel actually captured, so that it is possible to extremely reduce the loss of both the black data and the white data and reduce the deterioration of resolution. Images can be obtained.

[0013] In fourth aspect of the invention, the operation result of the second previous pixel and L _'n-2, a binary signal of the current pixel and L _{n + 1,} the binary signal of the previous pixel and L _n , L _n ′ = L _{n + 1} +
It is possible to perform a logical operation of L _n · L ' _n-2 bar (where L' _n-2 bar is the inversion result of L' _n-2 ). Therefore, when the data of the previous pixel actually fetched is black, the data of the next pixel with one pixel vacant is output as it is, and when the data of the previous pixel fetched is white, the logical sum data of the next two pixels is output. Since it is possible to output, it is possible to obtain data in which black data and white data are extremely less missing, and it is possible to obtain an image with little deterioration in resolution.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention (Claim 1), an image processing circuit for reading an image signal of one line and sequentially outputting the image signal, and an image reading apparatus for fetching the output of this image processing circuit for every plural lines are used. A binarized signal storage memory that stores a binarized signal, an operation result storage memory that stores operation results for a plurality of lines, an operation result captured by the operation result storage memory, and a binarized signal before a plurality of lines And a binarized signal of the current line, and an arithmetic means for performing an arithmetic operation. The arithmetic result of the arithmetic means is output to the image processing circuit, and the arithmetic result is stored in the arithmetic result storage memory. With the above configuration, the processing of the data to be captured next is appropriately determined based on the data of the previous line that has actually been captured, and the black data and white data are both greatly reduced. Hereinafter, Embodiment 1 of the present invention will be specifically described with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing the arrangement of an image reading apparatus according to the first embodiment of the present invention. The illustrated example has an image processing circuit that reads an image signal of one line and sequentially outputs the image signal, and is applied to an image reading apparatus that takes in the output of this image processing circuit every plural lines. In FIG. 1, reference numeral 1 denotes an original reading circuit. The analog read data or multi-valued read data output from the original reading circuit 1 is input to a binarizing circuit 2 and the binarizing circuit 2 outputs white or black. Converted to binary data. In this embodiment, white data is 0 and black data is 1. Next, the binarized data converted by the binarization circuit 2 is stored in the line memory 3a and input to the arithmetic circuit 4. Next, the output of the arithmetic circuit 4 is stored in the line memories 3b and 3c, and is input to the arithmetic circuit 4 again via the line memories 3b and 3c. That is, the arithmetic circuit 4 receives the binarized data L _{n + 1} of the current line, the binarized data L _n of the previous line, and the output of the arithmetic circuit 4 of the line before the previous line in synchronization with the main scanning position. . Here, the arithmetic circuit 4 is shown in FIG.
The logical operation of the following equation is performed as shown in the arithmetic circuit of. In FIG. 2, 6 to 8 are OR, AND and inverter, respectively.

L _n ′ = L _{n +1} + L _n L ' _n-2 bar (where L' _n-2 bar is the calculation result L' _{n-2 of the} line before the last line)
In this embodiment, since the circuit configuration is such that the data of two lines is converted into the data of one line, the data is taken in every other line. Therefore, if the data of the current L _n ′ line is taken in, the data taken in as the previous line is the data of the L ′ _n−2 line. That is, the logical product of the inversion result of the data captured in the previous line, the binary data read in the previous line, and the logical sum of the binary data read in the current line is output as processing data.

FIG. 3 shows an output example of this circuit. The binarized data shown in FIG.
It is converted into data as shown in (b). Since the system fetches data every other line, it is fetched as data as shown in FIG. 3C or FIG. 3D depending on the fetching cycle. Further, when the data is fetched every 3 lines, the binarized data memory may be provided for 2 lines and the operation data memory may be provided for 4 lines.

As described above, in this embodiment, the binarized signals for a plurality of lines are stored, the operation results for a plurality of lines are stored, and the fetched operation results are used as the binarized signals before a plurality of lines. It is possible to perform an operation with the binarized signal of the current line, output the operation result to the operation circuit 4 serving as an image processing circuit, and store the operation result in the memories 3b and 3c. For this reason, it is possible to appropriately determine the processing of the data to be captured next based on the data of the previous line that has actually been captured, so that it is possible to extremely reduce both black data and white data loss and to reduce resolution degradation. Images can be obtained.

Further, in the present embodiment, when taking data on every other line, the calculation result of the second previous line and L _'n-2, and a binary signal of the previous line and L _n, 2 value of the current line The converted signal is L _{n + 1,} and L _n ′ = L _{n + 1} + L _n · L ′ _n-2
Bar (however, L' _n-2 bar is the inversion result of L' _n-2 ) can be performed. Therefore, if the data of the previous line that has been actually captured is black, the data of the next line that is empty is output as it is, and if the data of the previous line that has been captured is white, the logical sum of the next two lines is calculated. Since data can be output, it is possible to obtain data with extremely few missing black and white data.
An image with little deterioration in resolution can be obtained.

Next, in the present invention (claim 3), an image signal of one line is read and two adjacent pixel data are read as one.
In an image reading apparatus which converts and outputs one image data, a binarized signal storage register that stores a binarized signal for one pixel, an operation result storage register that stores an operation result for two pixels, The calculation result data of the pixel, the binarized signal of the previous pixel and the binarized signal of the current pixel are included in the calculation result, and the calculation result by the calculation unit is stored in the calculation result storage register. By configuring the calculation result by the calculation output means to output every other pixel, the processing of the data to be captured next is appropriately determined based on the data of the previous pixel that is actually captured, and both the black data and the white data are processed. The number of omissions is extremely small. The second embodiment of the present invention will be specifically described below with reference to the drawings.

(Embodiment 2) FIG. 4 is based on Embodiment 2 of the present invention.
3 is a block diagram showing the configuration of the image reading apparatus. Illustration
An example is to read the image signal of one line and
Image reading that converts raw data into one pixel data and outputs
This is the case when applied to a picking device. In FIG. 4, 11 is a document
This is a reading circuit, and the document output from this document reading circuit 11
The analog read data or multi-value read data is converted into a binary circuit 12
Is input to this binary circuit 12 and white or black binary data
Is converted to. In this embodiment, the white data is 0,
The black data is set to 1. Then, it is converted by the binarization circuit 12.
The binarized data is stored in the register 13a and
It is input to the arithmetic circuit 14. Then, the output of the arithmetic circuit 14 is
This register is stored in register 13b and register 13c.
It is again input to the arithmetic circuit 14 via the data 13b and 13c. Immediately
Then, the arithmetic circuit 14 supplies the binarized data L of the current pixel. _{n + 1},Previous
Binary data L of pixel_nAnd the output of the arithmetic circuit 14 of the pixel before two
The force is input in synchronization with the main scanning position. Where the calculation times
The path 14 has the following formula as shown in the arithmetic circuit of FIG.
Perform a logical operation.

[0022] _{L n '= L n + 1} + L n · L' n-2 bar (where, L _'n-2 bar calculation result L of the second previous pixel' shows the inversion results of the _n-2) present example Then, 1 from 2 pixel data
Since the circuit configuration is such that it is converted into pixel data, data is taken in every other pixel. Therefore, if the data of L _n ′ pixels is currently fetched, the data fetched as the previous pixel is the data of L ′ _n−2 pixels. That is, the logical product of the inversion result of the data taken in by the previous pixel, the binary data read by the previous pixel, and the logical sum of the binary data read by the current pixel is output as processing data.

FIG. 5 shows an output example of this circuit. The binarized data shown in FIG.
It is converted into data as shown in (b). Since the system samples data by every other pixel by the sampling circuit 15, sampling output is performed as shown in FIG. 5C or 5D. Further, in this embodiment, as shown in FIG. 4, pixels in the main scanning direction are thinned out to 1/2, stored in the registers 13a to 13c in pixel units, and data is sampled by the sampling circuit 15 every other pixel. There is.

As described above, in this embodiment, two pixels for one pixel are used.
The binarization signal is stored, the computation result for two pixels is stored, the computation result data of the previous pixel, the binarization signal of the previous pixel and the binarization signal of the current pixel are used for computation, and the computation result is registered. 13
The calculation results can be output every other pixel while being stored in b and 13c. For this reason, it is possible to appropriately determine the processing of the data to be captured next based on the data of the previous pixel actually captured, so that it is possible to extremely reduce the loss of both the black data and the white data and reduce the deterioration of resolution. Images can be obtained.

Further, in this embodiment, the operation result of the second previous pixel and L _'n-2, a binary signal of the current pixel and L _{n + 1,} the binary signal of the previous pixel and L _n, L _n ′ = L _{n + 1} + L _n
A logical operation of L _{n- 2} bar (where L' _n-2 bar is the inversion result of L' _n-2 ) can be performed. For this reason,
When the data of the previous pixel actually fetched is black, the data of the next pixel with one vacant pixel is output as it is, and when the data of the previous pixel fetched is white, the logical sum data of the next two pixels is output. Therefore, it is possible to obtain data in which black data and white data are extremely less missing, and it is possible to obtain an image with little deterioration in resolution.

[0026]

According to the present invention, it is possible to extremely reduce the loss of both black data and white data and to obtain an image with little deterioration in resolution.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an image reading apparatus according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an arithmetic circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram showing binarized data, an arithmetic circuit output, and fetched data according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of an image reading device according to a second embodiment of the present invention.

FIG. 5 is a diagram showing binarized data, an arithmetic circuit output, and a sampling output according to the second embodiment of the present invention.

FIG. 6 is a diagram illustrating a problem of a conventional example.

FIG. 7 is a diagram illustrating a problem of a conventional example.

[Explanation of symbols]

 1, 11 Original reading device 2, 12 Binarization circuit 3a to 3c Line memory 4, 14 Arithmetic circuit 6 or 7 and 8 Inverter 13a to 13c Register 15 Sampling circuit

Claims (4)

[Claims] 1. An image processing circuit which reads an image signal of one line and sequentially outputs the image signal, and an image reading device which takes in the output of the image processing circuit every plural lines, and stores binary signals for the plural lines. A binarized signal storage memory, a calculation result storage memory that stores calculation results for a plurality of lines,
And a calculation unit that performs a calculation with the calculation result fetched by the calculation result storage memory, the binarized signal before a plurality of lines, and the binarized signal of the current line, and the calculation result by the calculation unit is displayed in the image. An image reading apparatus configured to output the processing circuit and store the calculation result by the calculation output unit in the calculation result storage memory. Wherein when taking the data every other line, the calculation result of the second previous line and L _'n-2, a binary signal of the previous line and L _n, a binary signal of the current line L _{n +1} and L
_{n '= L n + 1 +} L n · L' n-2 bar (where, L _'n-2 bar L' is a result of the inversion of the _n-2), comprising a logical operation means for performing comprising logic operation The image reading apparatus according to claim 1. 3. A binarized signal for storing a binarized signal for one pixel in an image reading apparatus for reading an image signal of one line, converting two adjacent pixel data into one pixel data and outputting the pixel data. A storage register, a calculation result storage register that stores a calculation result of two pixels, and a calculation unit that performs calculation with the calculation result data of the pixel before the previous pixel, the binarized signal of the previous pixel, and the binarized signal of the current pixel. An image reading apparatus comprising: a calculation result stored by the calculation means in the calculation result storage register, and the calculation result output by the calculation output means every other pixel. 4. A calculation result of a pixel before two is L '._n-2And the current picture
The binary signal of the prime is L_{n + 1}And the binary signal of the previous pixel is L
_nAnd L_n′ = L_{n + 1}+ L_n・ L '_n-2Bar (however,
L ' _n-2The bar is L '_n-2Is the inversion result of)
A logical operation means for performing arithmetic operations is provided.
3. The image reading device described in 3.