JP3320124B2 - Image reading device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image reading apparatus,
More specifically, the present invention relates to an image reading apparatus that performs linear density conversion in an image reading apparatus such as a facsimile or a scanner.

[0002]

2. Description of the Related Art A linear density conversion method in a conventional image reading apparatus, particularly in a case where thinning processing is performed by reduction or the like, is described below.
For example, there is a report in Japanese Patent Application Laid-Open No. 1-152868, in which a logical OR is performed with an adjacent pixel or an adjacent line in order to prevent black data from being lost.

[0003]

However, the conventional image reading apparatus as described above has an advantage that black data can be prevented from being lost by taking a logical sum with adjacent pixels or adjacent lines. Loss cannot be prevented, and a problem remains in that white data is lost, resulting in an image that tends to be crushed as a whole (FIGS. 6A, 6C, and 6D). ) And FIG. 7).

A conventional image reading apparatus which solves the above-mentioned problem is disclosed in, for example, Japanese Patent Publication No. Sho 60-31421. Here, when white data and black data are mixed, white image data is used. Data different from the immediately preceding pixel is output so that data and black data are output on average.
However, this conventional image reading apparatus has an advantage that the collapse of an image can be suppressed to some extent by averaging and outputting white data and black data as much as possible. Therefore, a problem remains in that the resolution is degraded (see FIGS. 6A, 6B and 7).

SUMMARY OF THE INVENTION An object of the present invention is to provide an image reading apparatus capable of extremely reducing the loss of both black data and white data and obtaining an image with less deterioration in resolution.

[0006]

According to the first aspect of the present invention,
Analog or multi-valued read data obtained by reading an image
A binary circuit for converting the data into binary binary data,
An image reading device that performs linear density conversion of the binary data
Here, the binarized data output from the binarization circuit is
First storage means for storing each line, and the first storage means
The binarized data stored in the means is input and
The binarized data output from the binarizing circuit is input,
Line operation that performs operation for each line and outputs the operation result
Means and the calculation results of the line calculation means are written for each line.
A second storage means for storing the information again and outputting it to the line operation means
And a line operation means, wherein the line operation means comprises:
And binarized data L _n of the n-th line stored in stages, the
The binarized data of the (n + 1) th line output from the binarizing circuit
L _{n + 1} and two lines stored in the second storage means.
Based on the previous operation result L′ _n−2 ,
_n the _{L'n = L n + 1 +} L n · inv (L'n-2)
(However, inv (L' _n-2 ) is the inverse of (L' _n-2 ))
The result is a logical operation
It is assumed that.

[0007]

[0008]

[0009]

[0010]

[Action]

[0011] In the first aspect of the present invention, actually takes
If the data _L'n-2 is black but the line, one line vacated next line data L n _{+ 1} is output as it is, taken
When the data L ′ _n−2 of the inserted line is white, the logical sum data (L _n + L _{n + 1} ) of the next two lines can be output, so that the loss of black data and white data is extremely small. Data can be obtained, and an image with less deterioration in resolution can be obtained.

[0012]

[0013]

[0014]

EXAMPLES The following will now be specifically described with reference to the drawings Embodiment 1 of the present invention.

Embodiment 1 FIG. 1 is a block diagram showing a configuration of an image reading apparatus according to Embodiment 1 of the present invention. In FIG. 1, an image reading device
Represents a binarization circuit 2 and a first line memory 3a (first
Storage means), and second and third line memories 3b, 3c
(Second storage means ) and operation circuit 4 (line operation means)
And 1 is a document reading circuit, analog read data or multivalued read data output from the document scanning circuit 1 is inputted to the binarizing circuit 2, the binarizing circuit 2 in white or black binary data (Ie "binarized")
) . In this embodiment, white data is set to 0 and black data is set to 1. Next, the binarized data converted by the binarization circuit 2 is stored in the line memory 3a and input to the arithmetic circuit 4. Next, the output of the arithmetic circuit 4 is stored in the line memories 3b and 3c, and is again input to the arithmetic circuit 4 via the line memories 3b and 3c. That is, the arithmetic circuit 4 receives the binary data L _{n + 1} of the current line, the binary data L _n of the previous line, and the output of the arithmetic circuit 4 of the line before the last line in synchronization with the main scanning position. Here, the arithmetic circuit 4 have rows logical operation of the formula as shown in the arithmetic circuit of FIG. 2, and outputs the calculation result L _{n '.} FIG.
, 6 to 8 are OR, AND, and inverters, respectively.

[0016] _{L n '= L n + 1} + L n · inv (L' n-2) ( where, inv _{(L 'n-2)} the calculation result _L of the second previous _line' shows the inversion results of the _n-2) Namely , FIGS. 1, 2 and
As shown by the above equation, the arithmetic circuit 4 has the first
The binarized data of the n-th line stored in the line memory 3a
And data _{L n,} (n + 1) th line outputted from the binarizing circuit 2
In the binarized data Ln _{+ 1} and the third line memory 3c.
The stored operation result L' _n-2 two lines before is input.
And the inversion result of the operation result L' _n-2 two lines before and the n-th
Performs a logical product of the binary data L _n of the line, the logical
Results of Riseki and binarized data _{L n + 1} of the (n + 1) -th line
Is output as the operation result L _n ′. In this embodiment, since the circuit configuration converts data of two lines into data of one line, data is taken in every other line. Therefore , if L _n ′ is taken in, the data taken in as the previous line is L ′ _n−2 .

Here, FIG. 3 shows an output example of this circuit. The binarized data shown in FIG.
It is converted into data as shown in FIG. Since the system takes in data every other line, it is taken in as data as shown in FIG. 3 (c) or FIG. 3 (d) according to the taking cycle .

[0018]

In this embodiment, when the data L' _{n-2 of the} line actually fetched is black, the data Ln _{+ 1} of the next line that is one line vacant is output as it is and the fetched line
If in the data _L'n-2 is white, it is possible to output the logical sum data of the next two lines _{(L n + L n + 1} ), lack of black data and white data to obtain a extremely small data Therefore, it is possible to obtain an image with less deterioration in resolution.

Hereinafter, a second embodiment of the present invention will be specifically described with reference to the drawings.

Embodiment 2 FIG. 4 is a block diagram showing the configuration of an image reading apparatus according to Embodiment 2 of the present invention. In FIG. 4, an image reading device
Represents a binarization circuit 12 and a first register 13a (third register
Storage means), and the second and third registers 13b and 13c.
(Fourth storage means) and operation circuit 14 (pixel operation means)
And a sampling circuit 15. The illustrated example is a case where the present invention is applied to an image reading apparatus that converts two adjacent pixel data into one pixel data and outputs the data. In FIG.
Reference numeral 11 denotes a document reading circuit. Analog reading data or multi-valued reading data output from the document reading circuit 11 is input to a binarization circuit 12, and the binarization circuit 12 outputs white or black two-dimensional data.
It is converted into digitized data (ie, "binarization"). In this embodiment, white data is set to 0 and black data is set to 1. Next, the binarized data converted by the binarization circuit 12 is stored in the register 13a and input to the arithmetic circuit 14. Next, the output of the arithmetic circuit 14 is stored in the registers 13b and 13c, and is again input to the arithmetic circuit 14 via the registers 13b and 13c. That is, the binary data L _{n + 1} of the current pixel, the binary data L _n of the previous pixel, and the output of the arithmetic circuit 14 of the pixel before the previous pixel are input to the arithmetic circuit 14 in synchronization with the main scanning position. Here, the arithmetic circuit 14 is the first embodiment.
The logical operation of the following equation is performed as shown in the arithmetic circuit of FIG.
And outputs the operation result L _n ′.

[0022] _{L n '= L n + 1} + L n · inv (L' n-2) ( where, inv _{(L 'n-2)} the calculation result _L of the second previous _pixel' shows the inversion results of the _n-2) Namely , FIGS. 4, 2 and
As shown by the above equation, the arithmetic circuit 14
Binarized data of the n-th pixel stored in the register 13a
L _n and the (n + 1) th pixel output from the binarization circuit 12.
Binarized data Ln _{+ 1} and stored in third register 13c
The calculated result L ′ _n−2 two pixels before is input, and 2
The inversion result of the calculation result L′ _n−2 before the pixel and the 2
Performs a logical product of the binary data L _n, the result of this logical product
And the binary data L _{n + 1} of the ( _{n + 1) th} pixel
It is output as the operation result L _n '. In the present embodiment, since the circuit configuration converts data of two pixels into data of one pixel, data is taken in every other pixel. Therefore, if L _n ′ is taken in, the data taken in as the previous pixel is L ′ _n−2 .

FIG. 5 shows an output example of this circuit. The binary data shown in FIG.
It is converted into data as shown in FIG. Since the system samples data every other pixel by the sampling circuit 15, the data is sampled and output as shown in FIG. 5C or FIG. 5D. In the present embodiment, as shown in FIG. 4, pixels in the main scanning direction are thinned out to 1/2, stored in the registers 13a to 13c in pixel units, and data is sampled by the sampling circuit 15 every other pixel. I have.

[0024]

In this embodiment, when the actually taken pixel data L' _n-2 is black, the data Ln _{+ 1} of the next pixel left by one pixel is output as it is, and the taken pixel data L' _{n- If 2} is white, the logical sum data of the next two pixels
Since (L _n + L _{n + 1} ) can be output, data in which black data and white data are extremely small can be obtained, and an image with less deterioration in resolution can be obtained. Note that, in this specification, a binary value for each pixel in the second embodiment is used.
Data _{L n, L n + 1,} L'n-2 and _L'n are real
When distinguishing from the binarized data for each line of the first embodiment,
Re _{LE n, LE n + 1,} LE' n-2 and LE' _n both
expressed.

[0026]

According to the present invention, both black data and white data can be extremely reduced, so that an image with less deterioration in resolution can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image reading apparatus according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an arithmetic circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram showing binarized data, arithmetic circuit output, and captured data according to the first embodiment of the present invention.

FIG. 4 is a block diagram illustrating a configuration of an image reading device according to a second embodiment of the present invention.

FIG. 5 is a diagram showing binarized data, an arithmetic circuit output, and a sampling output according to the second embodiment of the present invention.

FIG. 6 is a diagram illustrating a problem of a conventional example.

FIG. 7 is a diagram illustrating a problem of a conventional example.

[Explanation of symbols]

1, 11 Document reading circuit 2, 12 Binarization circuit 3a Line memory (first storage means) 3b, 3c Line memory (second storage means) 4 Operation circuit (line operation means) 14 Operation circuit (pixel operation means 6 ) OR 7 and 8 Inverter 13a Register (third storage means) 13b, 13c Register (fourth storage means) 15 Sampling circuit

Claims (1)

(57) [Claims] (1)Analog or multiple images obtained by reading images
Binarization that converts read value data into binary binary data
A circuit for performing linear density conversion of the binary data.
In an image reading device, The binarized data output from the binarizing circuit is line-by-line
A first storage means for storing in the first storage means;
The binarized data is input and the binarization is performed.
Binary data output from the circuit is input, and for each line
A line operation means for performing an operation on and outputting an operation result;
The calculation result of the line calculation means is stored for each line and
And second storage means for outputting to the line operation means.
e, The line operation means is stored in the first storage means.
Binarized data L of the n-th line _n And the binarization circuit
Data L of the (n + 1) th line output from
_{n + 1} And before two lines stored in the second storage means.
Calculation result L ′ _n-2 And the calculation result L ′ _n To
L ' _n = L _{n + 1} + L _n ・ Inv (L ' _n-2 ) (But
And inv (L ' _n-2 ) Is (L ' _n-2 ) Inversion result
Is generated by a logical operation of
Image reading device.