JPH06188321A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH06188321A
JPH06188321A JP33868292A JP33868292A JPH06188321A JP H06188321 A JPH06188321 A JP H06188321A JP 33868292 A JP33868292 A JP 33868292A JP 33868292 A JP33868292 A JP 33868292A JP H06188321 A JPH06188321 A JP H06188321A
Authority
JP
Japan
Prior art keywords
wiring
substrate
layer
contact hole
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33868292A
Other languages
Japanese (ja)
Inventor
Hiroshi Suzuki
洋 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JFE Steel Corp
Original Assignee
Kawasaki Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kawasaki Steel Corp filed Critical Kawasaki Steel Corp
Priority to JP33868292A priority Critical patent/JPH06188321A/en
Publication of JPH06188321A publication Critical patent/JPH06188321A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To completely prevent a problem that Al is ionized and flows out into a liquid and that a wiring defect is caused when an Al interconnection is formed on an Si substrate, it is ashed and cleaned. CONSTITUTION:A contact hole is opened in an insulating layer on a substrate, tungsten 2 is filled into the contact hole, a polisilicon pad 3 is formed on its surface, a first-layer interconnection 4 is then formed independently of the substrate, an interlayer film 6 is deposited, a via hole 5j is opened in it, and a second-layer interconnection 7 is coupled to the substrate and to the first-layer interconnection 4.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置及びその製
造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method.

【0002】[0002]

【従来の技術】半導体の製造工程において、エッチング
後にフォトレジストを除去する際アッシングし、アッシ
ング残渣をアミン系の有機洗浄剤により洗浄する。基板
上にAl配線を形成する場合、上記アミン系有機洗浄及
び純水洗浄の段階において、Si基板とAl配線が洗浄
液中で電気回路を形成し、Alがイオン化して液中に流
出する。
2. Description of the Related Art In a semiconductor manufacturing process, ashing is performed when a photoresist is removed after etching, and the ashing residue is washed with an amine-based organic cleaning agent. When forming the Al wiring on the substrate, the Si substrate and the Al wiring form an electric circuit in the cleaning liquid in the steps of the amine-based organic cleaning and the pure water cleaning, and Al is ionized and flows out into the liquid.

【0003】この現象は光の影響によって加速される等
の事情もあり、急速にAlが溶出してAl配線部および
ビアコンタクトホール底部のAlに欠損が生ずることが
ある。この場合に、第1層配線部の断線が発生し、ま
た、第2層間膜のスパッタリングを行ったとき、層間膜
がコンタクトホール内に十分に入りにくいために、Al
の第1層と第2層との間が断線状態となる。
This phenomenon may be accelerated by the influence of light, etc., and Al may be rapidly eluted to cause defects in Al at the Al wiring portion and at the bottom of the via contact hole. In this case, disconnection of the first-layer wiring portion occurs, and when the second interlayer film is sputtered, the interlayer film does not easily enter the contact hole.
A disconnection occurs between the first layer and the second layer.

【0004】[0004]

【発明が解決しようとする課題】本発明は、洗浄工程に
おいて配線材料が滅失しないようにし、確実に結線する
ことを目的とする。すなわち、Al配線形成後の有機洗
浄に起因する配線オープン不良およびビアホールエッチ
ング後の有機洗浄に起因するビアオープン不良を防止す
ることを課題とするものである。
SUMMARY OF THE INVENTION It is an object of the present invention to prevent the wiring material from being lost in the cleaning process and to securely connect the wiring. That is, it is an object to prevent wiring open defects due to organic cleaning after Al wiring formation and via open defects due to organic cleaning after via hole etching.

【0005】[0005]

【課題を解決するための手段】本発明は、基板とは独立
に基板上に形成されている第1の配線に、第1の配線よ
り上方に位置し、基板と結合した第2の配線を接続した
ことを特徴とする半導体装置である。このような半導体
装置は、基板上の絶縁層にコンタクトホールを開口し、
導電性金属をこのコンタクトホールに埋込み、その上面
にパッドを形成し、次いで第1層の配線を基板とは独立
に形成し、層間膜を堆積し、これにビアホールを開口
し、第2層の配線を基板及び前記第1層の配線と結合す
ることにより製造することができる。
According to the present invention, a first wiring formed on a substrate independently of a substrate is provided with a second wiring located above the first wiring and coupled to the substrate. The semiconductor device is characterized by being connected. Such a semiconductor device has a contact hole opened in an insulating layer on a substrate,
A conductive metal is buried in this contact hole, a pad is formed on the upper surface of the contact hole, then a wiring of the first layer is formed independently of the substrate, an interlayer film is deposited, a via hole is opened in this, and a second layer of the second layer is formed. It can be manufactured by combining the wiring with the wiring of the substrate and the first layer.

【0006】[0006]

【作用】第1層のAl配線とSi基板とは通常はコンタ
クトホールを介して接続するが、本発明ではこれを接続
させない。そして層間膜を形成し、これにビアホールを
開口した後、第2層のAl配線を基板に接続させる。第
1層配線はSi基板と接続していないため、Alエッチ
およびビアエッチ後の有機洗浄時に、第1層配線とSi
基板間に溶液を介した電気回路が形成されない。その結
果、Alエッチ後の有機洗浄によるAl配線およびビア
エッチ後の有機洗浄によるビアホール部のAl溶出(腐
食)が発生せず、配線オープン不良を防止することがで
きる。
The Al wiring of the first layer and the Si substrate are normally connected via a contact hole, but they are not connected in the present invention. Then, an interlayer film is formed, a via hole is opened in this, and then the Al wiring of the second layer is connected to the substrate. Since the first-layer wiring is not connected to the Si substrate, the first-layer wiring and Si
No electric circuit is formed between the substrates via the solution. As a result, no Al elution (corrosion) occurs in the Al wiring due to the organic cleaning after the Al etching and the via hole portion due to the organic cleaning after the via etching, and the wiring open defect can be prevented.

【0007】このようにして製造された半導体装置は、
特殊な配線構造を有すると共にAl配線の断線状態等が
全く存在しない優れた半導体装置である。
The semiconductor device manufactured in this manner is
It is an excellent semiconductor device having a special wiring structure and having no broken state of Al wiring.

【0008】[0008]

【実施例】本発明の半導体装置の製造工程の実施例を図
1に従って説明する。 (a)コンタクトホールを開口し、このコンタクトホー
ルに導電性金属例えばタングステン2を埋め込む。さら
にタングステン2上に例えばポリシリコンでパッド3を
形成する。 (b)第1層配線4を形成する。このとき、第1層配線
4は基板とは接続せず絶縁被覆の上に形成する。 (c)第2層間膜6を堆積した後ビアホール5を開口す
る。 (d)第2層配線7を形成する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the manufacturing process of a semiconductor device of the present invention will be described with reference to FIG. (A) A contact hole is opened, and a conductive metal such as tungsten 2 is embedded in this contact hole. Further, a pad 3 is formed on the tungsten 2 by using, for example, polysilicon. (B) The first layer wiring 4 is formed. At this time, the first-layer wiring 4 is formed on the insulating coating without being connected to the substrate. (C) After depositing the second interlayer film 6, the via hole 5 is opened. (D) The second layer wiring 7 is formed.

【0009】このようにして配線を形成すると、第1層
配線4は洗浄工程においてSi基板と接続されていない
ので、Alが洗浄液中に浸出することがなく、健全な配
線を形成することができる。図2はこのようにして製造
された本発明の半導体装置の要部平面図である。第1の
配線(第1層配線)4は基板と独立に形成されている。
第2の配線(第2層配線)7はタングステン2、ポリシ
リコンのパッド3、ビアホール5を介して基板と接続さ
れている。そして第1の配線4は第2の配線7と結合さ
れている。このような半導体装置は、配線オープン不良
がない。
When the wiring is formed in this manner, since the first layer wiring 4 is not connected to the Si substrate in the cleaning process, Al does not leach into the cleaning liquid and a sound wiring can be formed. . FIG. 2 is a plan view of an essential part of the semiconductor device of the present invention manufactured as described above. The first wiring (first layer wiring) 4 is formed independently of the substrate.
The second wiring (second layer wiring) 7 is connected to the substrate via the tungsten 2, the polysilicon pad 3, and the via hole 5. Then, the first wiring 4 is coupled to the second wiring 7. Such a semiconductor device has no wiring open defect.

【0010】[0010]

【発明の効果】Si基板上にAl配線を形成し、アッシ
ング後洗浄するとAlがイオン化して液中に流出し、配
線欠陥が生ずる問題があったが、本発明によればこれを
完全に防止することが可能となった。
EFFECTS OF THE INVENTION When an Al wiring is formed on a Si substrate and washed after ashing, Al is ionized and flows out into the liquid, causing a wiring defect. The present invention completely prevents this. It became possible to do.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例の製造工程図である。FIG. 1 is a manufacturing process diagram of an example.

【図2】実施例の平面図である。FIG. 2 is a plan view of the embodiment.

【符号の説明】[Explanation of symbols]

1 ゲート 2 タングステ
ン 3 パッド 4 第1層配線 5 ビアホール 6 第2層間膜 7 第2層配線
1 Gate 2 Tungsten 3 Pad 4 First Layer Wiring 5 Via Hole 6 Second Interlayer Film 7 Second Layer Wiring

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 基板とは独立に基板上に形成されている
第1の配線に、第1の配線より上方に位置し、基板と結
合した第2の配線を接続したことを特徴とする半導体装
置。
1. A semiconductor characterized in that a second wiring, which is located above the first wiring and is coupled to the substrate, is connected to a first wiring formed on the substrate independently of the substrate. apparatus.
【請求項2】 基板上の絶縁層にコンタクトホールを開
口し、導電性金属を該コンタクトホールに埋込み、その
上面にパッドを形成し、第1層の配線を基板とは独立に
形成し、層間膜を堆積し、これにビアホールを開口し、
第2層の配線を基板及び第1層の配線と結合することを
特徴とする半導体装置の製造方法。
2. A contact hole is opened in an insulating layer on a substrate, a conductive metal is buried in the contact hole, a pad is formed on the upper surface of the contact hole, and a wiring for the first layer is formed independently of the substrate. Deposit a film, open a via hole in it,
A method of manufacturing a semiconductor device, characterized in that the wiring of the second layer is combined with the wiring of the substrate and the wiring of the first layer.
JP33868292A 1992-12-18 1992-12-18 Semiconductor device and manufacture thereof Pending JPH06188321A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33868292A JPH06188321A (en) 1992-12-18 1992-12-18 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33868292A JPH06188321A (en) 1992-12-18 1992-12-18 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH06188321A true JPH06188321A (en) 1994-07-08

Family

ID=18320470

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33868292A Pending JPH06188321A (en) 1992-12-18 1992-12-18 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH06188321A (en)

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