JPH06187471A - Multiplier - Google Patents

Abstract

PURPOSE:To provide the analog multiplier capable of improving linearity for input signals and suitable in high frequency operations. CONSTITUTION:One input voltage V1 is impressed between the bases of transistors Q1 and Q4 of the two pairs of transistors (Q1, Q2) and (Q3, Q4) to be driven by a constant current source I1. Then, a bias offset voltage Vk with the bases of Q1 and Q4 as positive poles is impressed respectively between the bases of Q4 and Q2 and between the bases of Q1 and Q4. The bases of (Q5, Q6) are connected in common and an input voltage V2 is impressed to the bases of (Q7, Q8) but the common connected bases of Q5 and Q6 are connected to the base of Q7. The collectors of Q1 and Q3 are connected to the emitters of (Q5, Q6) in common, and the collectors of Q4 are connected to the emitters of (Q7, Q8) in common. Then, a differential output pair is constituted by respectively connecting the collectors of Q5 and Q7 and the collectors of Q6 and Q8 in common.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplier for an analog signal formed on a bipolar integrated circuit, and more particularly to an analog multiplier which improves linearity with respect to an input signal and is suitable for high frequency operation. .

[0002]

2. Description of the Related Art In analog LSI design, a multiplier is an indispensable functional block, and a quilt multiplier is well known for it. In this gilbert multiplier, the linearity for one input signal is improved. A conventional pliers is, for example, FIG.
And that shown in FIG. 8 are known.

In FIG. 7, this multiplier is
(Q1, Q2) (Q3, Q4) (Q5, Q6). Transistor (Q1,
Q2) is driven by the constant current source I ₀ via the emitter resistor R _E , but one input voltage V ₁ is applied between both bases. The pair of transistors (Q3, Q4) is driven by Q1 and the pair of transistors (Q5, Q6) is driven by Q2, but the bases of Q3, Q4 and Q5 are connected in common, and this common connection base and the base of Q6 are connected. Is the other input voltage V ₂
Is applied. The collectors of Q3 and Q5 and the collectors of Q4 and Q6 are commonly connected to each other to form a differential output pair.

Although its operation is well known, its description will be omitted. In short, this multiplier is the emitter resistance of the differential pair (Q1, Q2) to which the input voltage V ₁ is applied in the basic form of the quilt multiplier. By inserting R _E , the linearity with respect to the input voltage V ₁ is improved.

Next, the multiplier shown in FIG. 8 is one differential pair to which the input voltage V ₁ in FIG. 7 is applied in the Gilbert multiplier cross-connecting the output terminal and the input terminal of the two differential pairs. Is replaced by two mismatched differential pairs with an emitter size ratio of 1: K. That is,
The pair of transistors (Q2, Q1) and the same (Q3, Q4)
Each is driven by a constant current source I ₀ , but when the emitter size of Q2 (Q3) is 1, the emitter size of Q1 (Q4) is K times, which is a mismatched differential pair. The bases of Q2 and Q4 are commonly connected to each other, and one input voltage V ₁ is applied between both common connection bases. The collectors of Q1 and Q3 are commonly connected to the commonly connected emitters of Q5 and Q6.
The collectors of 2 and Q4 are commonly connected to each other and to the commonly connected emitters of Q7 and Q8.

The outline of the operation of the multiplier shown in FIG. 8 is as follows. The current of the junction diode forming the bipolar transistor is expressed by Equation 1. In addition, Formula 1
, I _E is the emitter current, I _S is the saturation current, k is the Boltzmann constant, T is the absolute temperature, q is the unit electron charge, V
_BE is the base-emitter voltage.

[0007]

## EQU1 ## I _E = I _S {exp (qV _BE / kT) -1}

Here, if the thermal voltage V _T is set to V _T = kT / q, then V _BE >> V _T. Therefore, the mathematical expression 1 is exp (V _BE /
V _T ) >> 1 can be approximated as in Equation 2.

[0009]

(2) I _E ≈I _S exp (V _BE / V _T )

First, the collector current I _{C1 of} Q1 and Q2 forming an unmatched differential pair having an emitter size ratio of K: 1.
And the same I _C2 . The relationship between the input voltage V ₁ and the base-emitter voltage V _BEi , the relationship between the saturation currents of both transistors, the relationship between the collector current I _Ci and the constant current source I _0, and the like are shown in Equation 3. In Expression 3, α _F is the current amplification factor.

[0011]

## _EQU3 ## V ₁ = V _BE1 −V _BE2 V _BE1 = V _T ln (I _C1 / I _S1 ) V _BE2 = V _T ln (I _C2 / I _S2 ) I _S1 = KI _S2 I _C1 + I _C2 = α _F I ₀

Therefore, from Equation 3, I _C1 and I _C2 are given by Equation 4
Is asked. In the equation 4, V _K is V _K = V _T
lnK.

[0013]

[Equation 4]

Then, the differential output current ΔI ₁ is obtained by Equation 5, and the transconductance G _m1 is obtained by Equation 6.

[0015]

## EQU5 ## ΔI ₁ = I _C1 -I _C2 = α _F I ₀ tanh {(V ₁ + V _K ) / 2V _T }

[0016]

[Equation 6]

The same applies to the unmatched differential pair made up of Q3 and Q4, and the differential output current ΔI ₂ is given by Equation 7,
The transconductance G _m2 can be _calculated by Equation 8.

[0018]

[Expression 7] ΔI ₂ = I _C3 −I _C4 = α _F I ₀ tanh {(V ₁ −V _K ) / 2V _T }

[0019]

[Equation 8]

Therefore, the differential output current ΔI of the multiplier shown in FIG.

[0021]

[Formula 9] ΔI = (I _C5 + I _C7 ) − (I _C6 + I _C8 ) = (I _C5 −I _C6 ) + (I _C7 −I _C8 ) = α _F I ₁ tanh (V ₂ / 2V _T ) + α _F I ₂ tanh (-V ₂
/ 2V _T ) = α _F (I ₁ −I ₂ ) tanh (V ₂ / 2V _T ).

Since I ₁ -I ₂ in the equation 9 is obtained as the equation 10, the differential output current ΔI is finally obtained by the equation 11
Becomes

[0023]

Equation 10] _{I 1 -I 2 = (I C1} + I C3) - (I C2 + I C4) = (I C1 -I C2) + (I C3 -I C4) = ΔI 1 + ΔI 2 = α F I 0 [ tanh {(V ₁ + V _K ) / 2V _T } + tanh
{(V ₁ −V _K ) / 2V _T }]

[0024]

ΔI = α _F ² I ₀ tanh (V ₂ / 2V _T ) [tanh
{(V ₁ + V _K ) / 2V _T } + tanh {(V ₁ −V _K ) / 2V
_T }]

By the way, conventionally, since K = 4 is set, the value obtained by differentiating the differential output current ΔI with the input voltage V ₁ , that is, the transconductance does not have the maximum flat characteristic but has the equiripple characteristic. However, the linearity with respect to the input voltage V ₁ is improved even in the configuration of FIG.

[0026]

However, since the multiplier shown in FIG. 7 has the emitter resistance, the frequency characteristic becomes extremely poor as the frequency increases. Also, FIG.
The multiplier shown in (1) has a problem that since the emitter area of the transistor becomes about four times, the transistor size increases and it is not suitable for high frequency operation.

The present invention has been made in view of the above problems, and an object thereof is to provide a multiplier suitable for high frequency operation while improving linearity with respect to an input signal.

[0028]

In order to achieve the above object, the multiplier of the present invention has the following constitution.
That is, the multiplier of the first invention is a pair of first and second pair transistors which are driven by a constant current source and in which one input voltage is applied between the bases of the respective one transistors. And a third pair of transistors whose bases are commonly connected; and a pair of transistors to which the other input voltage is applied between the bases, wherein one transistor is connected to the common connection base of the third pair of transistors A fourth pair of transistors ;; between the base of one of the transistors of the first pair of transistors and the base of the other of the second pair of transistors; Between the base and the base of the other transistor of the first pair of transistors, the base having the positive polarity of the transistor of the one transistor, The as-offset voltage is applied; the collectors of one transistor of the first pair of transistors and the other transistor of the second pair of transistors are commonly connected to the emitters of the third pair of transistors; one of the second pair of transistors And the collectors of the other transistors of the first pair of transistors are commonly connected to the emitters of the fourth pair of transistors; in the third pair of transistors and the fourth pair of transistors, the collectors of one transistor and the other The collectors of the transistors are commonly connected to each other;

The multiplier of the second invention is a pair of transistors driven by a constant current source, wherein the bases of one of the transistors and the bases of the other transistor are commonly connected to each other. A first and second pair of transistors to which one input voltage is applied; a third pair of transistors whose emitters are connected to the collector of one of the first pair of transistors; A fourth paired transistor connected to the collector of the other transistor of the first paired transistor; a fifth paired transistor whose emitters are connected to the collector of one of the second paired transistors; Is connected to the collector of the other transistor of the second pair of transistors. And a base of one of the transistors of the third pair of transistors and one of the bases of one of the fifth and sixth pair of transistors are connected in common, and the base of the common connection and the base of the fourth pair of transistors are connected. The other input voltage is applied between the base of one of the transistors and the base of one of the transistors of the third pair of transistors and the base of the other of the fifth pair of transistors. Between the base of the other transistor of and the base of one of the fifth pair of transistors, and between the base of one of the fourth pair of transistors and the base of the other of the sixth pair of transistors. ,
A bias offset voltage having a base of one of the transistors as a positive electrode is applied between the base of the other transistor of the fourth pair of transistors and the base of the one transistor of the sixth pair of transistors, respectively.
Collectors of one transistor of the pair of transistors and the other transistor of the fifth pair of transistors, and one collector of the sixth pair of transistors and the collectors of the other transistor of the fourth pair of transistors are commonly connected; The collectors of one of the fourth pair of transistors and the other of the sixth pair of transistors, and the collectors of one of the fifth pair of transistors and the other of the third pair of transistors are commonly connected. Is characterized by the following.

The multiplier of the third invention comprises a first, second, third and fourth pair of transistors driven by a constant current source; a fifth pair of transistors respectively driven by these four paired transistors. A sixth, a seventh and an eighth pair of transistors ;; and the bases of one of the first pair of transistors and the bases of one of the third and fourth pair of transistors are commonly connected to each other. One input voltage is applied between the common connection base and the base of one of the transistors of the second pair of transistors;
The base of one of the fifth pair of transistors and the bases of one of the seventh and eighth pair of transistors are commonly connected to each other, and the common connection base and the base of one of the sixth pair of transistors are connected to each other. An input voltage of the other of the first pair of transistors is applied between the base of one of the transistors of the first pair of transistors and the base of the other of the third pair of transistors. And a base of one of the transistors of the third pair of transistors, a base of one of the transistors of the second pair of transistors and a base of the other of the fourth pair of transistors, a second pair of transistors. Between the base of the other transistor and the base of one of the fourth pair of transistors of Between the base of one of the pair of transistors and the base of the other of the seventh pair of transistors, and the base of the other transistor of the fifth pair of transistors and the base of one of the seventh pair of transistors. Between the base of one of the sixth pair of transistors and the base of the other of the eighth pair of transistors, and between the base of the other of the sixth pair of transistors and the eighth pair of transistors. A bias offset voltage having the base of one of the transistors as a positive electrode is applied between the base of the one of the transistors and one of the transistors of the first pair of transistors and the other of the third pair of transistors. The collectors and the emitters of the fifth pair of transistors are commonly connected; The collectors of the other transistors of the first pair of transistors and one of the transistors of the third pair of transistors are commonly connected to the emitters of the seventh pair of transistors; one transistor of the second pair of transistors and a fourth transistor The collectors of the other transistors of the paired transistors and the emitters of the sixth paired transistors are commonly connected; the other transistors of the second paired transistors and the collectors of one of the fourth paired transistors and the eighth paired transistors The emitters of the pair of transistors are commonly connected; the collectors of one of the fifth pair of transistors and the other of the seventh pair of transistors, the one of the eighth pair of transistors, and the sixth pair of transistors. The collectors of the other transistors are commonly connected; One transistor of the pair of transistors and a collector each other of the other transistor of the pair transistors of the eighth and one transistor of the seventh transistor pair 5
And the collectors of the other transistors of the pair of transistors are commonly connected;

[0031]

Next, the operation of the multiplier of the present invention constructed as above will be described. The multiplier of the present invention is
It is based on a Gilbert multiplier that connects the output and input ends of two differential pairs, but each differential pair is composed of bipolar transistors with the same characteristics, and the differential pair that improves linearity is biased. It is a method of applying an offset. That is, the first invention improves linearity with respect to one input voltage, the second invention improves linearity with respect to the other input voltage, and the third invention improves linearity with respect to both input voltages. Since each of them can be formed by the transistor having the minimum configuration, a multiplier suitable for high frequency operation can be obtained.

[0032]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a multiplier according to an embodiment of the present invention. In this first embodiment circuit, the differential pair (Q5, Q6) (Q7, Q8) to which the other input voltage V ₂ is applied is shown in FIG.
And a configuration similar to that shown in FIG. 8, but a differential pair (Q1, Q2) (Q
3, Q4) have their output terminals cross-connected, and a bias offset voltage V _K is applied between the cross-connected input terminals.

Specifically, (Q1, Q2) and (Q3, Q
The two paired transistors in 4) are constant current sources I ₀ respectively.
First and second paired transistors driven by
One input voltage V ₁ is applied between the bases of the respective one of the transistors (Q1, Q4). Between the base of one transistor Q1 of the first pair of transistors (Q1, Q2) and the base of the other transistor Q3 of the second pair of transistors (Q3, Q4), and also the second pair of transistors (Q3, Bias offset between the base of one of the transistors Q4 and the base of the other transistor Q2 of the first pair of transistors (Q1, Q2) with the base of one of the transistors (Q1, Q4) as a positive electrode. The voltage V _K is applied.

The bases are commonly connected (Q5, Q
6) is a third pair transistor, the other input voltage V ₂ is applied between the bases (Q7, Q8) is a fourth pair transistor, and the common connection base of Q5 and Q6 is the base of Q7. Connected, but the first pair of transistors (Q1,
The collectors of one transistor Q1 of Q2) and the other transistor Q3 of the second pair of transistors (Q3, Q4) are commonly connected to the emitters of the third pair of transistors (Q5, Q6), and (Q3, Q
4) The collectors of the one transistor Q4 and the other transistor Q2 of the first pair of transistors (Q1, Q2) are commonly connected to the emitters of the fourth pair of transistors (Q7, Q8).

The third pair of transistors (Q5, Q
6) and the fourth transistor pair (Q7, Q8), the collectors of one transistor (Q5, Q7) and the collectors of the other transistor (Q6, Q8) are commonly connected to each other to form a differential output pair. is doing.

In the above configuration, (Q1, Q2, I
_In the differential pair of ( ₀ ), Expression 12 is established.

[0037]

V _BE1 −V _BE2 = V ₁ + V _K V _BE1 = V _T ln (I _C1 / I _S1 ) V _BE2 = V _T ln (I _C2 / I _S2 ).

Then, I _S1 = I _S2 , I _C1 + I _C2 = α _F I
_Since it is ₀ , I _C1 and I _C2 can be obtained as Formula 13. Formula 4
It has the same content as. Therefore, the differential output current ΔI of the multiplier shown in FIG. 1 is given by the equation 14 having the same contents as the equation 11, and the transconductance with respect to the input voltage V ₁ , ie, d (ΔI) / dV ₁ is given by the equation 15.

[0039]

[Equation 13]

[0040]

[Expression 14] ΔI = α _F ² I ₀ tanh (V ₂ / 2V _T ) [tanh
{(V ₁ + V _K ) / 2V _T } + tanh {(V ₁ −V _K ) / 2V
_T }]

[0041]

[Equation 15]

By the way, the bias offset voltage V _K
Is a value of K = 2 + √3 in V _K = V _T lnK,
That is, if V _K = V _T ln (2 + √3) = 1.317V _T is selected, the transconductance shown in Formula 15 is as shown in FIG.
Shows the maximum flatness characteristic, and the linearity with respect to the input voltage V ₁ is improved as shown in FIG.

The bias offset voltage V _K can be applied by a method as shown in FIG. 4, for example.
In FIG. 4, Q1 to Q4 are as shown in FIG.
Furthermore transistors driven by a constant current source I ₀₀ (Q13~
Q16) is provided. Q13 (Q15) and Q14 (Q
In 16), the emitter size ratio is K: 1, the collectors and the bases are commonly connected, the commonly connected collectors are connected to the power supply V _CC , and the input voltage V ₁ is applied between the commonly connected bases. It

The gate of Q1 is connected to the emitter of Q13, the gate of Q3 is connected to the emitter of Q14, the gate of Q4 is connected to the emitter of Q15, and Q2.
Is connected to the emitter of Q16.

That is, the base-emitter voltage is Q13.
Since <Q14, Q15 <Q16, the emitter voltage becomes Q13> Q14, Q15> Q16, and the polarity of the bias offset voltage V _K is Q1 as shown in FIG.
And the Q4 side has a high potential. In FIG. 4, K
Is K = 2 + √3 as described above.

Next, FIG. 5 shows a multiplier according to the second embodiment of the present invention. The circuit of the second embodiment is intended to improve the linearity of the other input voltage V ₂ , and the same operation as that of the first embodiment provides the characteristics equivalent to those of FIGS. 2 and 3.

A concrete connection relationship is shown. The (Q1, Q2) and (Q3, Q4) two paired transistors driven by the constant current source I ₀ are the first and second paired transistors, and one of the transistors (Q1, Q3) of each one is The bases and the bases of the other transistors (Q2, Q4) are commonly connected to each other, and one input voltage V ₁ is applied between the common connection bases.

The third pair of transistors (Q5, Q6) are
The emitters are connected to the collector of one transistor Q1 of the first pair of transistors (Q1, Q2). Fourth
The paired transistors (Q7, Q8) are connected at their emitters to the collector of the other transistor Q2 of the first paired transistors (Q1, Q2). The emitters of the fifth pair of transistors (Q9, Q10) are connected to the collector of one transistor Q3 of the second pair of transistors (Q3, Q4). In addition, the sixth transistor pair (Q1
1, Q12) have their emitters connected to the collector of the other transistor Q4 of the second pair of transistors (Q3, Q4).

One of the transistors Q5 of the third pair of transistors (Q5, Q6) and the fifth pair of transistors (Q9, Q9,
The bases of one of the transistors Q9 of Q10) and one of the transistors Q11 of the sixth pair of transistors (Q11, Q12) are commonly connected, and one of the common connection base and one of the fourth pair of transistors (Q7, Q8) is connected. The other input voltage V ₂ is applied to the base Q7 of the other transistor.

Between the base of one transistor Q5 of the third pair of transistors and the base of the other transistor Q10 of the fifth pair of transistors, the base of the other transistor Q6 of the third pair of transistors and the fifth pair of transistors are provided. One of the transistors is connected to the base of the transistor Q9, and the fourth
Between the base of one transistor Q7 of the pair of transistors and the base of the other transistor Q12 of the sixth pair of transistors, and between the base of the other transistor Q8 of the fourth pair of transistors and the sixth pair of transistors. Between the base of one transistor Q11,
A bias offset voltage having a base of one of the transistors as a positive electrode is applied.

The collectors of one transistor Q5 of the third pair of transistors and the other transistor Q10 of the fifth pair of transistors, one transistor Q11 of the sixth pair of transistors and the other transistor Q4 of the fourth pair of transistors. The collectors of Q8 are commonly connected to each other, and the collectors of one transistor Q7 of the fourth pair of transistors and the other transistor Q12 of the sixth pair of transistors and one transistor Q9 of the fifth pair of transistors and the third pair of transistors are connected. The other transistor Q of the transistor
The six collectors are commonly connected to each other to form a differential output pair.

Next, FIG. 6 shows a multiplier according to the third embodiment of the present invention. The circuit of the third embodiment is intended to improve the linearity of both two input voltages, and the characteristics similar to those of FIGS. 2 and 3 can be obtained by the same operation as that of the first embodiment.

A concrete connection relationship is shown. (Q1, Q2)
(Q3, Q4) (Q5, Q6) (Q7, Q8) are the first, second, third and fourth pair transistors driven by the constant current source I ₀ , respectively (Q9, Q10) ( Q1
1, Q12) (Q13, Q14) (Q15, Q16)
Are fifth, sixth, seventh and eighth pair transistors, respectively driven by the first, second, third and fourth pair transistors.

One transistor Q1 of the first pair of transistors (Q1, Q2) and the third pair of transistors (Q5, Q5,
One of the transistors Q5 of Q6) and the base of one of the transistors Q7 of the fourth pair of transistors (Q7, Q8) are commonly connected, and the common connection base and one of the second pair of transistors (Q3, Q4) are connected. One input voltage V ₁ is applied to the base of the transistor Q3. Also, one transistor Q9 of the fifth pair of transistors (Q9, Q10) and the seventh pair of transistors (Q13, Q1)
4) The bases of the one transistor Q13 and the one transistor (Q15, Q16) of the eighth pair of transistors are commonly connected, and the common connection base and one of the sixth pair transistors (Q11, Q12) are connected. The other input voltage V ₂ is applied to the base of the transistor Q11.

Between the base of one transistor Q1 of the first pair of transistors and the base of the other transistor Q6 of the third pair of transistors, the base of the other transistor Q2 of the first pair of transistors and the third pair of transistors. Between the base of one of the transistors Q5 and the base of one of the transistors Q3 of the second pair of transistors and the base of the other transistor Q8 of the fourth pair of transistors, the other of the second pair of transistors. Between the base of the transistor Q4 and the base of one transistor Q7 of the fourth pair of transistors, and between the base of one transistor Q9 of the fifth pair of transistors and the base of the other transistor Q14 of the seventh pair of transistors. Between the base of the other transistor Q10 of the fifth pair of transistors and the seventh pair of transistors. Between the base of one transistor Q13 of the sixth pair of transistors and the base of the other transistor Q16 of the eighth pair of transistors, and the sixth pair of transistors. The other base of the transistor Q12 and the eighth
A bias offset voltage V _K having the base of one of the transistors as a positive electrode is applied between the pair of transistors and the base of the transistor Q15.

One transistor Q1 of the first pair of transistors and the other transistor Q of the third pair of transistors.
6 collectors and a fifth pair transistor (Q9, Q1
0) are commonly connected to each other, and the collectors of the other transistor Q2 of the first pair of transistors and one transistor Q5 of the third pair of transistors and the emitters of the seventh pair of transistors (Q13, Q14) are connected to each other. Are commonly connected, and one transistor Q3 of the second pair of transistors and the other transistor Q of the fourth pair of transistors are connected.
8 collectors and a sixth paired transistor (Q11, Q
12) are commonly connected to each other, and the collectors of the other transistor Q4 of the second pair of transistors and one transistor Q7 of the fourth pair of transistors and the emitters of the eighth pair of transistors (Q15, Q16) are connected to each other. Are commonly connected.

The collectors of one transistor Q9 of the fifth pair of transistors and the other transistor Q14 of the seventh pair of transistors, one transistor Q15 of the eighth pair of transistors and the other transistor of the sixth pair of transistors. The collectors of Q12 are commonly connected to each other, and one of the sixth pair of transistors Q11
And the collectors of the other transistors Q16 of the eighth pair of transistors, the one transistor Q13 of the seventh pair of transistors, and the collectors of the other transistor Q10 of the fifth pair of transistors are commonly connected to form a differential output pair. I am configuring.

[0058]

As described above, the multiplier of the present invention is basically based on the Gilbert multiplier which connects the output terminal and the input terminal of two differential pairs.
Since each differential pair is composed of bipolar transistors having the same characteristics, and the differential pair on the side for improving the linearity has a method of applying a bias offset, the first invention can improve the linearity for one input voltage. The second invention can improve the linearity with respect to the other input voltage, and the third invention can improve the linearity with respect to both input voltages. However, since the transistors can be formed by the transistors having the minimum configurations, a multiplier suitable for high frequency operation can be provided. effective.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a multiplier according to a first embodiment of the present invention.

FIG. 2 is a transconductance characteristic diagram of the multiplier shown in FIG.

FIG. 3 is an input / output characteristic diagram of the multiplier shown in FIG.

FIG. 4 is a circuit diagram of an example of a bias offset voltage application method.

FIG. 5 is a circuit diagram of a multiplier according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram of a multiplier according to a third embodiment of the present invention.

FIG. 7 is a circuit diagram of a conventional multiplier.

FIG. 8 is a circuit diagram of a conventional multiplier.

[Explanation of symbols]

Q1 to Q16 Bipolar transistor I ₀ Current source V ₁ , V ₂ Input voltage V _K Bias offset voltage

Claims (3)

[Claims] 1. A pair of first and second pair transistors which are driven by a constant current source, wherein one input voltage is applied between the bases of the respective one transistors; A third pair of transistors commonly connected; a fourth pair of transistors to which the other input voltage is applied between the bases, one transistor being connected to the common connection base of the third pair of transistors And; between the base of one of the transistors of the first pair of transistors and the base of the other of the second pair of transistors, and the base of one of the transistors of the second pair of transistors and the first of the transistors of the second pair of transistors. A bias offset voltage with the base of one of the transistors as the positive pole is applied between the pair of transistors and the base of the other transistor. The collectors of one of the first pair of transistors and the other of the second pair of transistors are commonly connected to the emitters of the third pair of transistors; The collectors of the other transistors of the one pair of transistors are commonly connected to the emitters of the fourth pair of transistors; the collectors of one of the transistors and the collectors of the other of the third pair of transistors and the fourth pair of transistors. Are commonly connected to each other; 2. A pair of two transistors driven by a constant current source, wherein the bases of one of the transistors and the bases of the other transistor are commonly connected to each other, and one input voltage is applied between the two common connection bases. A first and second pair of transistors to which is applied; a third pair of transistors whose emitters are connected to the collector of one of said first pair of transistors; and an emitter of said first pair of transistors A fourth pair of transistors connected to the collector of the other transistor;
A fifth pair transistor whose emitters are connected to the collector of one of said second pair transistors; and a sixth pair transistor whose emitters are connected to the collector of the other transistor of said second pair transistor And ;; the base of one of the third pair of transistors and the bases of one of the fifth and sixth pair of transistors are commonly connected, and the common connection base and one of the fourth pair of transistors are The other input voltage is applied to the base of the transistor of;
Between the base of one of the transistors of the third pair of transistors and the base of the other of the fifth pair of transistors, the base of the other transistor of the third pair of transistors and the one of the transistors of the fifth pair of transistors are Between the base of one transistor of the fourth pair of transistors and the base of the other transistor of the sixth pair of transistors, and between the base of the other transistor of the fourth pair of transistors and the sixth pair of transistors. Between the pair of transistors and the base of one of the transistors,
A bias offset voltage having a base of one of the transistors as a positive electrode is applied; collectors of one of the third pair of transistors and the other of the fifth pair of transistors, one of the sixth pair of transistors and one of the transistors of the sixth pair of transistors, and The collectors of the other transistors of the fourth pair of transistors are commonly connected; one of the transistors of the fourth pair of transistors and the other collectors of the other transistors of the sixth pair of transistors and one of the fifth pair of transistors A collector of the other transistor of the third pair of transistors is commonly connected; a multiplier. 3. A first, a second and a third driven by a constant current source.
And a fourth pair of transistors; fifth, sixth, seventh and eighth pair transistors respectively driven by these four pair transistors; and a base of one of the first pair transistors. The bases of one of the third and fourth pair of transistors are commonly connected to each other, and one input voltage is applied between the common connection base and the base of one of the transistors of the second pair of transistors; The base of one of the paired transistors of No. 5 and the bases of one of the transistors of the seventh and eighth paired transistors are commonly connected to each other, and the common connection base and the base of one of the transistors of the sixth paired transistors are connected. The other input voltage is applied in between;
Between the base of one of the transistors of the first pair of transistors and the base of the other of the third pair of transistors, the base of the other transistor of the first pair of transistors and the one of the transistors of the third pair of transistors are Between the base of one of the second pair of transistors and the base of the other of the fourth pair of transistors, between the base of the other of the second pair of transistors and the fourth pair of bases. Between the base of one of the transistors of the fifth pair of transistors and between the base of one of the transistors of the fifth pair of transistors and the base of the other of the seventh pair of transistors, A sixth pair of transistors is provided between the base and the base of one of the seventh pair of transistors. Between the base of one of the transistors and the base of the other of the eighth pair of transistors, and between the base of the other of the sixth pair of transistors and the base of one of the eighth pair of transistors. A bias offset voltage having a base of one of the transistors as a positive electrode is applied respectively between the collectors of one of the transistors of the first pair of transistors and the other of the third pair of transistors and the fifth pair of transistors. The emitters are commonly connected; the other transistor of the first pair of transistors and the collectors of one of the third pair of transistors and the emitters of the seventh pair of transistors are commonly connected; the second pair of transistors Transistor of one of the transistors and the other of the fourth pair of transistors The collectors of the second pair of transistors and the emitters of the sixth pair of transistors are commonly connected; And 5 are commonly connected; collectors of one of the fifth pair of transistors, the other of the seventh pair of transistors, one of the eighth pair of transistors and the other of the sixth pair of transistors And the collectors of one of the sixth pair of transistors and the other of the eighth pair of transistors, one of the seventh pair of transistors, and the other of the fifth pair of transistors. Characterized in that the collectors are commonly connected to each other; Multipliers.