JPH0333989A - Analog multiplier - Google Patents

Abstract

PURPOSE:To enable operation with a low voltage source by inputting the output current of a transformer conductance amplifier, which is equipped with differential paired inputs by an NPN transistor, through a current mirror circuit to a multiplier. CONSTITUTION:NPN transistors TRQ1-Q4 in 9 multiplication block constitute the upper step part of a gilbert multiplier and TRQ5 and Q6 constitute the lower step part. The TRQ5 and Q6 to respectively determine bias currents for the differential pairs of the TRQ1 and Q2 and of the TRQ3 and Q4 are connected through the current mirror circuit, which is composed of the TRQ7 and Q8, to the transformer conductance amplifier composed of TRQ9 and Q10. A current to be generated by a constant current source IQ1 is distributed to the respective parts of the differential pairs by the current mirror circuit, which is composed of TRQ15 and Q16 and a PNP TRQ4, and becomes the bias current of a differential circuit. Thus, by controlling the current with the conductance amplifier for the control of the lower step part in the multiplier, the operation can be executed by the low voltage source such as 1V, for example.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an analog multiplier, and more particularly to an analog multiplier that operates at high speed with a constant voltage of about 1 μm power supply voltage.

[Conventional technology]

Conventionally, as this type of analog multiplier, the circuit shown in FIG. 5 is widely known and used as a Gilbert multiplier. In the figure, NPN transistor Q! A differential pair of ~Q4 and load resistors R1 and R2 constitutes the upper block 11 of the multiplier, and an NPN transistor Q is formed from these differential pairs.
31. A constant current source IO2 is connected to the differential circuit of Q10 as a load.

In Fig. 5, input voltages V 1 , V 2 , output voltage T, are absolute temperature, q is electron charge amount〉, resistances R,, R2
is the resistance value of

[Problem to be solved by the invention]

The conventional analog multiplier described above has a circuit configuration in which transistors are stacked vertically between the power supply and ground, as shown in Figure 5. It is impossible to operate in the voltage range, and therefore it has the disadvantage that it cannot be applied to portable electronic devices that operate directly with a single dry cell battery.

An object of the present invention is to eliminate such drawbacks and to input the output current of a transconductance amplifier with a differential pair input using NPN transistors to a multiplier through a current mirror circuit, thereby reducing a voltage as low as the power supply voltage IV. The purpose of the present invention is to provide an analog multiplier that can operate in the following manner.

[Means to solve the problem]

The configuration of the analog multiplier of the present invention includes a transconductance amplifier that converts a first input voltage into a current, a current mirror circuit controlled by the output current of the transconductance amplifier, and a current mirror circuit connected to the lower stage. It is characterized by comprising an upper stage part of a Gilbert-type multiplication circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. As shown in the figure, the NPNPN transistors Q9Q2, Q3Q4 and load resistors R, R2 of this embodiment are similar to those of the conventional Gilbars 1 to 1.
It is connected in the same way as the upper stage (block 11) of the multiplier.

Transistor Q9. Differential pair of Q2 and transistor Q
9. The NPNPN transistor Q96, which constitutes a constant current source that determines the bias current of each differential pair of Q4, is connected to a diode-connected NPN transistor Q7. Q8 through a Karen 1-mirror circuit to NPN transistors Q9. It is connected to a transconductance amplifier composed of QIO.

Here, transistor Q9. The operation of a transconductance amplifier using QIO will be explained. constant current source r
The current generated at o+ is NPN) transistor Q+5. Q
+6, PNP) - is distributed to each part of the differential pair by a current mirror circuit consisting of transistor Q+4, and becomes a bias current for the differential circuit. Here Qll, Q10. Q16
Since the emitter areas of all are equal, the current of NPNPN transistor Q9 + constant current source IQI flows, but transistor Q12. Since the emitter area ratio of Q +3°Q10 is 2:2:1, a current of 2IQ flows through each of the PNPNP transistors Q9Q10.

As a result, the relationship between the output currents 1 and 2 of these differential pairs and the input voltage Vl becomes as shown in the characteristic diagram of FIG.

The DC transfer characteristics of these differential pairs are the same as those of a normal differential pair in which the bias is increased by the current IQI.

Here, the reason for providing a bias equal to IQI is the current 1
．． , I2, a current mirror circuit Q7. This is to prevent Q8 from completely blocking. Transistor Q9. When Q8 is cut off, the potential between the emitters of these transistors becomes approximately OV, and transistors Q9. This is to prevent this differential pair from malfunctioning due to the QIO collector potential becoming ○■.

Further, in this differential circuit, the PNPNP transistors Q9Q10 function only as a constant current bias circuit and do not serve as a signal path for the input signal Vl. Generally speaking, when comparing NPN transistors and PNP transistors, NPN transistors have electrons as majority carriers, while PNP transistors have electrons as majority carriers.
In transistors, holes serve as majority carriers, so NPN transistors are more suitable for high-speed operation due to their mobility.

In this differential circuit, PNP transistors are not used in the signal path, so high speed is determined only by the characteristics of the NPN transistors, which is advantageous.

The currents I, , I2 created in this way are passed through the current mirror Q7. Through transistor Q8, transistor Q9. It flows to Q6. The relationship between the input voltages Vl, r, and I2 is the same as that of the conventional differential pair circuit as shown in FIG.
Since the connections of ~Q4 and R, , R2 are the same as in the conventional Gilbert multiplier, they are mutually connected to the Gilbert multiplier with the relationship between the inputs V, , V2 and the output Vo, and analog multiplication characteristics can be obtained.

FIG. 3 is a circuit diagram of a second embodiment of the invention. In this embodiment, a resistor R3 is connected to a differential pair of transistors Ql and Q2.
The configuration is exactly the same as that shown in FIG. 1 except that R4 is inserted.

The configuration is exactly the same as the one shown in FIG. 1 except that the resistors R3 and R4 are inserted in this way.

It is widely known that by inserting the resistors R3 and R4 in this manner, the dynamic range for the input voltage Vl can be widened.

FIG. 4 is a circuit diagram of a third embodiment of the present invention. When a differential pair circuit composed of transistors Q21 to Q26 is used, the dynamic range can be expanded with better linearity than when resistors R3 and R4 are inserted as shown in FIG.

Here, so that the output currents I, I2 do not become zero,
PNP transistor Q 27+ Q 2g, Q 14
The emitter area ratio was set to 3:3:1.

In both of these Figures 3 and 4, the multiplication block 1
As in FIG. 1, the multiplier function is realized by controlling the constant current source in the lower stage of 0.

〔Effect of the invention〕

As explained above, the present invention uses a transconductance amplifier to control the current in the lower stage of the conventional Gilbert multiplier, and furthermore, by not using a PNP transistor in the signal path of the transconductance amplifier, the power supply voltage can be reduced. This has the effect of providing a high-speed analog multiplier that can operate at a voltage as low as IV.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, and FIG. 2 is a circuit diagram of a first embodiment of the present invention.
FIGS. 3 and 4 are circuit diagrams of the second and third embodiments of the present invention, and FIG. 5 is a diagram of the conventional multiplication circuit. FIG. 2 is an example circuit diagram. Q】〜(L+・Q10・Q16・Q21〜Q26・Q
31. Q32...NPN transistor, Q12 to Q14.
Q27゜Q28...PNP transistor, R,, R2
...Load resistance, R3, R4...Emitter resistance, IQ
I, IQ2...constant current source, Vl, V2...input voltage, VO...output voltage, ■cc...power supply voltage, 10.
...Multiplication block, 11... Multiplier upper stage block.

Claims (2)

[Claims] (1) A transconductance amplifier that converts a first input voltage into a current, a current mirror circuit controlled by the output current of this transconductance amplifier, and an upper part of a Gilbert-type multiplier circuit in which this current mirror circuit is connected to the lower part. An analog multiplication circuit characterized by comprising: (2) The analog multiplier according to claim (1), wherein the transconductance amplifier comprises an NPN transistor differential pair and a PNP transistor constant current source connected to the collector of the transistor differential pair.