JPH06181108A - Semiconductor ceramic having positive resistance-temperature characteristic - Google Patents

Abstract

PURPOSE:To provide semiconductor ceramic which can be reduced in resistance fluctuation while the resistance of the porcelain at the room temperature is reduced, can be improved in quality reliability, and has a positive resistance- temperature characteristic. CONSTITUTION:At the time of constituting the title semiconductor ceramic 1 composed of semiconducting ceramic layers 2 and electrodes 3, the layers 2 are formed by using a ceramic material consisting essentially of barium titanate and containing SiO2 as an additive. The adding amount of SiO2 is controlled to 0.1-5mol%. In addition, the layers 2 and electrodes 3 are simultaneously and integrally baked.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated semiconductor porcelain having a positive resistance-temperature characteristic in which an electric resistance value changes with temperature, and more specifically, while lowering the resistance at room temperature,
The present invention relates to a structure in which variations in resistance value are reduced to improve reliability in quality.

[0002]

2. Description of the Related Art BaTiO ₃ having a positive resistance temperature characteristic
The system semiconductor porcelain has a characteristic that the resistance value sharply increases above the Curie point. There is. Further, in order to cope with the recent low resistance, a laminated semiconductor ceramic has been proposed as an alternative to the disk type. In this laminated semiconductor ceramic, semiconductor ceramic layers and internal electrodes are alternately laminated and integrally sintered, and external electrodes are formed on the left and right end faces of the sintered body. It has a structure in which one end face of is connected alternately.

In such a laminated semiconductor ceramic, as a semiconductor ceramic layer, conventionally, BaTiO ₃ has been the main component,
A ceramic material obtained by adding Y or La to this is used (Japanese Patent Laid-Open Nos. 55-88304 and 57-6.
(See Japanese Patent No. 0802).

[0004]

However, in the above-mentioned conventional semiconductor ceramics, although the resistance value at room temperature is low, there is a problem that the resistance value varies widely and the reliability of the quality is low.

The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor ceramic having a positive resistance-temperature characteristic capable of reducing resistance variation while achieving a reduction in resistance. I am trying.

[0006]

The inventors of the present invention have studied the composition of a semiconductor ceramic layer in order to improve the above-mentioned problem of resistance variation, and have found that the barium titanate forming the ceramic layer contains SiO ₂ It was found that the above-mentioned variation can be reduced by adding a predetermined amount of the above, and the present invention has been accomplished.

Therefore, in the invention of claim 1, in a semiconductor porcelain having a positive resistance temperature characteristic composed of a semiconductor ceramic layer and an electrode, the semiconductor ceramic layer contains barium titanate as a main component, and SiO ₂ is added thereto. It is characterized in that it is made of a ceramic material. Further, the invention of claim 2 is such that the added amount of SiO ₂ is 0.1 to 5
The present invention is characterized in that the semiconductor ceramic layer and the electrode are co-fired.

The amount of SiO ₂ added is defined here because the effect of improving the variation of the resistance value cannot be obtained at 0.1 mol% or less, and a remarkable effect can be obtained by adding more than this. . Further, even if the above-mentioned addition amount exceeds 5 mol%, the variation can be improved, but the resistance value is increased on the contrary, which is not preferable. Further, when the ceramic layer and the electrode are fired at the same time, the effect of reducing the variation is great.

The semiconductor porcelain of the present invention includes the following. A structure in which semiconductor ceramic layers and internal electrodes are alternately laminated and the laminated bodies are simultaneously sintered together. On the upper surface of the ceramic sheet, a paste obtained by mixing ceramic powder, carbon, varnish, etc. is printed to form an electrode portion corresponding to the internal electrode, which is laminated and then integrally sintered to form the electrode portion. A porous layer is formed on the inner surface of the sintered body, and electrodes are injected into the porous layer of this sintered body to form internal electrodes. Further, the ceramic sheet is sintered to form a sintered plate, an electrode paste for internal electrodes is printed on the sintered plate, the sintered plates are laminated and laminated, and then heat treated to obtain the above. The internal electrode is baked and integrated with the sintered plate. Further, a so-called disc type in which electrodes are formed on both main surfaces of a single-plate ceramic sintered plate is included.

[0010]

According to the semiconductor porcelain having the positive resistance-temperature characteristic according to the present invention, since SiO ₂ is added to barium titanate which constitutes the semiconductor ceramic layer, the variation in the resistance value is reduced while the resistance is reduced. It is possible to improve the reliability of quality.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 are views for explaining a semiconductor ceramic having a positive resistance temperature characteristic according to an embodiment of the present invention.
In this embodiment, a laminated semiconductor ceramic will be described as an example. In the figure, reference numeral 1 is a laminated semiconductor ceramic of this embodiment. The semiconductor porcelain 1 has a rectangular parallelepiped shape and is formed by alternately stacking semiconductor ceramic layers 2 and internal electrodes 3 made of Ni, and simultaneously sintering the stacked bodies to form a sintered body 4. There is. One end surface 3a of each internal electrode 3 is alternately exposed to the left and right end surfaces 4a and 4b of the sintered body 4, and the remaining end surfaces are located inside the ceramic layer 2 and inside the sintered body 4. It is buried in.

External electrodes 5 made of Ag are coated on the left and right end surfaces 4a and 4b of the sintered body 4, and the external electrodes 5 and one end surfaces 3a of the internal electrodes 3 are electrically connected to each other. It is connected.

The semiconductor ceramic layer 2 is B
It is composed of a ceramic material containing aTiO ₃ as a main component and SiO ₂ added thereto, and the addition amount of the SiO ₂ is within a range of 0.1 to 5 mol%.

Next, one of the laminated semiconductor porcelain 1 of this embodiment is manufactured.
The manufacturing method will be described. First, as a raw material, BaCO
₃, CaCO₃, TiO₂, La₂O₃, MnO ₂, S
iO₂To prepare the following composition. (Ba
_0.848Ca_0.15La_0.002)_1.01TiO₃+0.01 SiO₂+0.
001 MnO₂Pure water and zirconia balls
Put it in a polyethylene pot and crush and mix for 5 hours
After that, it is dried and calcined at 1100 ° C. for 2 hours.

Next, the calcined body is pulverized again to form a calcined powder, and the calcined powder is mixed with an organic binder, a solvent, and
And a dispersant are mixed to form a ceramic green sheet having a thickness of 0.1 mm. Next, add this green sheet to 7.5 x
A large number of semiconductor ceramic layers 2 are formed by punching into a rectangular shape so as to have a size of 6.5 mm ² .

Next, an electrode paste prepared by mixing varnish with Ni powder is prepared. This electrode paste is screen-printed on the upper surface of each ceramic layer 2 to form the internal electrodes 3. In this case, only one end surface 3a of each internal electrode 3 extends to the end edge of the ceramic layer 2, and the other end surface is located inside.

As shown in FIG. 2, the ceramic layers 2 and the internal electrodes 3 are alternately overlapped with each other, and the one end faces 3a of the internal electrodes 3 are alternately located on the left and right end faces of the ceramic layer 2. Ten layers are stacked, and ceramic layers 6 and 6 as dummy are stacked and stacked on the upper and lower surfaces thereof. Then
This is pressed and pressed by a press to form a laminate. As a result, only one end surface 3a of the internal electrode 3 is on the left side of the laminated body,
It is exposed on the right end face, and the remaining part is enclosed in the laminated body.

Next, the above-mentioned laminated body is heated in the atmosphere to burn the binder, and then fired at 1350 ° C. for 2 hours in a reducing atmosphere of H ₂ / N ₂ = 3% to obtain a sintered body 4. To get Then, this sintered body 4 is subjected to reoxidation heat treatment at 800 ° C. for 2 hours in the atmosphere.

Finally, the left and right end surfaces 4a of the sintered body 4 are
After coating the Ag paste on 4b, it is baked at 650 ° C. in the atmosphere to form the external electrode 5. As a result, the laminated semiconductor ceramic 1 of this embodiment is manufactured.

[0020]

[Table 1]

Table 1 shows the results of tests conducted to confirm the effects of the laminated semiconductor ceramics of this embodiment. This test is carried out in the above-mentioned manufacturing method by using the S of the above-mentioned ceramic raw material.
A large number of samples were prepared by changing the amount of iO ₂ in the range of 0 to 0.10. The resistance value (Ω) at room temperature of each sample was measured, and the variation of the resistance value (σ / average%) was examined. .

As is clear from Table 1, in the case of the samples in which the amount of SiO ₂ is 0 or 0.0005, which is below the claimed range, the resistance value is as low as 0.22,0.25 Ω, but the variation is greatly improved to 30,65%. Not effective. Further, in the sample in which the amount of SiO ₂ is 0.10 which is more than the claimed range, the variation can be reduced to 5%, but the resistance value is increased to 1.5Ω.
On the other hand, in the case of the samples in which the amount of SiO ₂ is within the claimed range, the resistance value of all the samples is low at 0.15 to 0.20Ω and the variation of the resistance values is small at 5 to 8%. ing. Thus, it is understood that by adding a predetermined amount of SiO ₂ , it is possible to significantly reduce the variation in the resistance value while lowering the resistance.

[0023]

[Table 2]

Table 2 shows the results of tests conducted to confirm the effects when applied to the disk type semiconductor porcelain.
In this test, the same ceramic raw material as in the above-mentioned example was adopted, and after the raw material powder was calcinated, an organic binder was mixed to form a green sheet, and a 15 mmφ × 1 mm ceramic plate was punched from the green sheet. After forming
A sintered plate was formed by firing, and a single-plate-shaped semiconductor porcelain was prepared. Then, the resistance value at room temperature and variations in the resistance value when the amount of SiO ₂ was changed in the range of 0 to 0.10.

In Table 2, even in the single-plate semiconductor porcelain, the variation of the resistance value is 5 to 7% by setting the above-mentioned SiO ₂ amount within the claimed range, which is 8% of the sample not added.
A slight reduction effect is obtained compared to%. However, this is not a significant effect of reducing 65% of the laminated type to 5%, but the present invention shows that a marked effect can be obtained only when applied to the laminated semiconductor ceramics.

[0026]

As described above, according to the semiconductor porcelain having the positive resistance temperature characteristic according to the present invention, since SiO ₂ is added to barium titanate, the variation in the resistance value can be achieved while lowering the resistance at room temperature. Can be reduced, and the reliability of quality can be improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view illustrating a semiconductor ceramic having a positive resistance temperature characteristic according to an embodiment of the present invention.

FIG. 2 is an exploded perspective view of a laminated semiconductor ceramic according to the above embodiment.

[Explanation of symbols]

 1 semiconductor porcelain 2 semiconductor ceramic layer 3 electrode

Claims (3)

[Claims] 1. A semiconductor porcelain having a positive resistance temperature characteristic comprising a semiconductor ceramic layer and an electrode, wherein the semiconductor ceramic layer is composed of barium titanate as a main component and SiO ₂ is added to the ceramic material. A semiconductor porcelain having a positive temperature coefficient of resistance characterized by being configured. _2. The semiconductor ceramic according to claim 1, wherein the SiO ₂ content is in the range of 0.1 to 5 mol%. 3. The semiconductor porcelain according to claim 1, wherein the semiconductor ceramic layer and the electrode are integrally fired at the same time.