JPH08222468A - Ceramic element and manufacture thereof - Google Patents
Ceramic element and manufacture thereofInfo
- Publication number
- JPH08222468A JPH08222468A JP2187495A JP2187495A JPH08222468A JP H08222468 A JPH08222468 A JP H08222468A JP 2187495 A JP2187495 A JP 2187495A JP 2187495 A JP2187495 A JP 2187495A JP H08222468 A JPH08222468 A JP H08222468A
- Authority
- JP
- Japan
- Prior art keywords
- ceramic element
- ceramic
- plating
- paste
- laminate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Landscapes
- Ceramic Capacitors (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、例えばコンデンサなど
のセラミック素子とその製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic element such as a capacitor and a method for manufacturing the same.
【0002】[0002]
【従来の技術】セラミック素子としてバリスタ特性とコ
ンデンサ特性とを併せ持つ粒界絶縁型半導体セラミック
コンデンサを例に説明する。2. Description of the Related Art A grain boundary insulating semiconductor ceramic capacitor having both varistor characteristics and capacitor characteristics as a ceramic element will be described as an example.
【0003】粒界絶縁型半導体セラミックコンデンサ
は、特開平3−1516号公報等にも示されるように、
まず出発原料として、Sr(1-x)BaxとTiのモル比が
0.95≦Sr(1-x)Bax/Ti<1.00となるよう
に過剰のTiを含有したSr(1 -x)BaxTiO3(ただ
し、0<x≦0.3)にNb2O5,Ta2O5,V2O5,
W2O5,Dy2O3,Nd2O3,Y2O3,La2O3,Co
O2の内の少なくとも一種類以上を0.05〜2.0m
ol%と、MnとSiをそれぞれMnO2とSiO2に換
算して合計量で0.2〜5.0mol%と、NaAlO
2を0.05〜4.0mol%含ませてなる組成物の混
合粉末を準備する。The grain boundary insulation type semiconductor ceramic capacitor is disclosed in Japanese Patent Application Laid-Open No. 3-1516, etc.
First, as starting materials, Sr (1-x) Ba x to Ti molar ratio of 0.95 ≦ Sr (1-x) of Ba x /Ti<1.00 become so contained an excess of Ti Sr (1 -x) Ba x TiO 3 (where 0 <x ≦ 0.3) is added to Nb 2 O 5 , Ta 2 O 5 , V 2 O 5 ,
W 2 O 5, Dy 2 O 3, Nd 2 O 3, Y 2 O 3, La 2 O 3, Co
At least one kind of O 2 is 0.05 to 2.0 m
ol%, Mn and Si are converted to MnO 2 and SiO 2 , respectively, and the total amount is 0.2 to 5.0 mol%, NaAlO
A mixed powder of a composition containing 0.05 to 4.0 mol% of 2 is prepared.
【0004】次にその混合粉末を粉砕、混合、乾燥した
後、空気中または窒素雰囲気中で仮焼し、さらに仮焼
後、再度粉砕した粉末を有機バインダーとともに溶媒中
に分散させて生シートにする。その後、図3に示すよう
に、この生シート4の上に、内部電極ペースト5を交互
に対向する端縁に至るように印刷し(ただし最上層およ
び最下層の生シートには印刷せず)この内部電極ペース
ト5の印刷された生シート4を積層、加圧、圧着して成
型体を得、その後この成型体を空気中で仮焼する。仮焼
後、還元雰囲気または窒素雰囲気中で焼成した後、空気
中で再酸化し、さらに内部電極2を露出させた両端に外
部電極ペーストを塗布し焼付けて外部電極3を形成す
る。そして、その上にハンダ等のメッキを行う。このよ
うにして、図2に示すようなチップタイプの積層型の粒
界絶縁型半導体セラミックコンデンサは製造される。Next, the mixed powder is pulverized, mixed and dried, then calcined in air or in a nitrogen atmosphere, further calcined, and then the pulverized powder is dispersed in a solvent together with an organic binder to form a green sheet. To do. After that, as shown in FIG. 3, the internal electrode paste 5 is printed on the green sheet 4 so as to reach the opposite edges alternately (however, not printed on the green sheets of the uppermost layer and the lowermost layer). The green sheet 4 on which the internal electrode paste 5 is printed is laminated, pressed and pressed to obtain a molded body, and then this molded body is calcined in air. After calcination, after firing in a reducing atmosphere or a nitrogen atmosphere, reoxidation is performed in air, and external electrode paste is applied to both ends where the internal electrodes 2 are exposed and baked to form external electrodes 3. Then, plating such as solder is performed on it. In this way, the chip type laminated grain boundary insulation type semiconductor ceramic capacitor as shown in FIG. 2 is manufactured.
【0005】[0005]
【発明が解決しようとする課題】しかしながら、この様
な製造方法で得られた積層型セラミック素子において
は、表面にオープンポアが形成されてしまうのでメッキ
時にイオンが素子内部に侵入したり、表面に付着したり
してセラミックスの成分を変化させたりあるいは素子表
面からの水分の侵入により電流負荷時に内部電極のマイ
グレションを引き起こしたりして静電容量、バリスタ電
圧の特性が劣化するなどの問題がしばしば起こってい
た。そこで本発明は、特性の劣化がほとんどない耐候
性、信頼性に優れたセラミック素子を提供することを目
的とするものである。However, in the multilayer ceramic element obtained by such a manufacturing method, open pores are formed on the surface, so that ions may penetrate into the element during plating or the surface may be exposed. Problems such as deterioration of capacitance and varistor voltage characteristics are often caused by adhesion and change of ceramic composition, or migration of water from element surface causing migration of internal electrodes during current load. It was happening. Therefore, an object of the present invention is to provide a ceramic element excellent in weather resistance and reliability with almost no deterioration in characteristics.
【0006】[0006]
【課題を解決するための手段】この目的を達成するため
に、本発明はセラミック素子表面の少なくともオープン
ポアをメタリン酸シリコンとシリカ粉とを混合したペー
ストで覆い、このペーストを硬化させるものである。To achieve this object, the present invention covers at least open pores on the surface of a ceramic element with a paste in which silicon metaphosphate and silica powder are mixed, and the paste is cured. .
【0007】[0007]
【作用】この構成により、不必要なイオン、水分がセラ
ミック素子表面及び内部に付着、侵入するのを防止する
ことができ、静電容量、バリスタ電圧などの特性劣化を
防ぐことができる。With this structure, it is possible to prevent unnecessary ions and water from adhering to and entering the surface and the inside of the ceramic element, and prevent characteristic deterioration such as capacitance and varistor voltage.
【0008】[0008]
【実施例】以下、本発明の第1の実施例について具体的
に説明する。EXAMPLE A first example of the present invention will be specifically described below.
【0009】図1は、本発明の一実施例における積層型
セラミック素子の一部切欠斜視図である。FIG. 1 is a partially cutaway perspective view of a laminated ceramic element according to an embodiment of the present invention.
【0010】まず、SrTiO3,CaCO3,BaCO
3,MgCO3,TiO2を(表1)のNo.1〜No.16に
示す第1成分の組成となるように秤量しボールミルなど
で20時間混合する。First, SrTiO 3 , CaCO 3 , and BaCO
3 , MgCO 3 , and TiO 2 are weighed so as to have the composition of the first component shown in No. 1 to No. 16 of (Table 1) and mixed with a ball mill for 20 hours.
【0011】[0011]
【表1】 [Table 1]
【0012】次に、乾燥した後、1100℃で4時間焼
成し、再びボールミルなどで75時間粉砕した後、乾燥
し第1成分とした。Next, after drying, it was baked at 1100 ° C. for 4 hours, pulverized again by a ball mill or the like for 75 hours, and then dried to obtain the first component.
【0013】次に、第1成分、第2成分、第3成分を
(表1),(表2)のNo.1〜No.16に示したモル比に
なるように秤量し、ボールミルなどで20時間混合した
後乾燥し、ブチラール系の樹脂および酢酸ブチルなどの
有機溶剤と混合してスラリーを作製する。Next, the first component, the second component, and the third component are weighed so as to have the molar ratios shown in Nos. 1 to 16 of (Table 1) and (Table 2), and are then ball milled. After mixing for 20 hours, it is dried and mixed with a butyral resin and an organic solvent such as butyl acetate to prepare a slurry.
【0014】[0014]
【表2】 [Table 2]
【0015】このスラリーを用いてドクターブレード法
などにより、50μmの厚みの生シートに成形した後乾
燥し、所定の大きさに切断する。次に最上層および最下
層となる生シート4には内部電極ペースト5を印刷せ
ず、その他の生シート4上に図3に示すようにAg−P
dからなる内部電極ペースト5を一方が端縁まで至るよ
うにスクリーン印刷し、これらを内部電極ペースト5が
交互に対向する端縁に至るように例えば30層積層す
る。そして加圧、圧着して所定の大きさに切断する。Using this slurry, a raw sheet having a thickness of 50 μm is formed by a doctor blade method or the like, dried, and cut into a predetermined size. Next, the inner electrode paste 5 is not printed on the green sheets 4 which are the uppermost layer and the lowermost layer, and Ag-P is formed on the other green sheets 4 as shown in FIG.
The internal electrode paste 5 made of d is screen-printed so that one reaches the edge, and 30 layers are laminated so that the internal electrode paste 5 reaches the edge where the internal electrode paste 5 is alternately opposed. Then, pressure and pressure are applied to cut into a predetermined size.
【0016】次に、空気中で700℃で脱脂し、さらに
空気中で1150℃で仮焼した後、内部電極2を露出さ
せた両端面にNiOからなる外部電極ペーストを塗布
し、たとえばN2:H2=10:1の還元性雰囲気中で1
250℃で3時間焼成し、さらに空気中で900℃で2
時間再酸化する。その後、Niの外部電極を露出させた
両端面にAg−Ptからなる外部電極ペーストを塗布
し、空気中で850℃で10分間焼付け外部電極3を形
成し、図1に示すような積層型セラミック素子を得る。
次にこの素子表面に平均粒径約0.5μmのSiO2と
メタリン酸シリコンを十分に混合したシリカペーストを
塗布する。[0016] Then, degreased at 700 ° C. in air, further after calcination at 1150 ° C. in air, coating the external electrode paste comprising NiO on both end surfaces to expose the internal electrodes 2, for example, N 2 : H 2 = 10: 1 in a reducing atmosphere
Bake at 250 ° C for 3 hours, and then in air at 900 ° C for 2 hours.
Reoxidize for hours. After that, an external electrode paste made of Ag—Pt is applied to both end surfaces of the exposed Ni external electrode, and the external electrode 3 is baked in air at 850 ° C. for 10 minutes to form the external electrode 3, and the multilayer ceramic as shown in FIG. Get the element.
Next, a silica paste in which SiO 2 having an average particle diameter of about 0.5 μm and silicon metaphosphate is sufficiently mixed is applied to the surface of the device.
【0017】その後350℃で約60分間熱処理を行
い、外部電極3を形成した部分以外の素子の表面に高抵
抗層6を形成する。Thereafter, heat treatment is performed at 350 ° C. for about 60 minutes to form the high resistance layer 6 on the surface of the element other than the portion where the external electrode 3 is formed.
【0018】その後例えば外部電極3上にNiメッキを
し、さらに半田メッキを施す。このようにして得られた
素子の特性および湿中負荷試験の結果を(表3)に示
す。After that, for example, Ni plating is performed on the external electrodes 3 and solder plating is further performed. The characteristics of the element thus obtained and the results of the humidity and mid-load test are shown in (Table 3).
【0019】[0019]
【表3】 [Table 3]
【0020】なお、V0.1mAは0.1mAの直流電流を
流した時に素子の両端にかかる電圧である。また本実施
例で示した積層型セラミック素子の形状は、通常212
5と呼ばれる大きさである。V 0.1 mA is a voltage applied to both ends of the device when a direct current of 0.1 mA is applied. Further, the shape of the multilayer ceramic element shown in this embodiment is usually 212.
It is a size called 5.
【0021】また、(表4)に湿中課電試験後の静電容
量の変化率とバリスタ電圧の変化率とを示す。Further, (Table 4) shows the rate of change in capacitance and the rate of change in varistor voltage after a voltage test in humidity.
【0022】[0022]
【表4】 [Table 4]
【0023】また、メッキの種類については一部の金属
についてのみ示したが、どのような種類の金属のメッキ
であっても構わず、また、その方法も酸性メッキでも塩
基性メッキでも、また電解メッキでも無電解メッキでも
構わない。The types of plating are shown only for some metals, but any type of metal may be used, and the method may be acidic plating, basic plating, or electrolytic plating. Either plating or electroless plating may be used.
【0024】さらに、内部電極2の材料としてAg−P
dなど一部の例を示したがAg,Pd,Pt,Ni,C
u,Zn,Inのうち1種類以上の金属や合金あるいは
酸化物であっても構わない。Further, Ag-P is used as a material for the internal electrodes 2.
Some examples such as d are shown, but Ag, Pd, Pt, Ni, C
It may be one or more kinds of metals, alloys or oxides of u, Zn and In.
【0025】なお、本実施例においては素子表面の外部
電極3の形成部分以外に約4μmの厚みになるように高
抵抗層を形成した。In this example, the high resistance layer was formed so as to have a thickness of about 4 μm except the portion where the external electrode 3 was formed on the surface of the device.
【0026】また、本実施例においては積層型のセラミ
ック素子を例に示したがディスク型など他の形状のセラ
ミック素子においても同様の効果が得られる。In this embodiment, a laminated ceramic element is shown as an example, but the same effect can be obtained with a ceramic element having another shape such as a disk type.
【0027】[0027]
【発明の効果】以上、本発明によるとセラミック素子表
面のポアにシリカを充填し目止めするので、水分や不必
要なイオンのセラミック素子内部への侵入を防ぐことが
できる。As described above, according to the present invention, since the pores on the surface of the ceramic element are filled with silica to seal the pores, moisture and unnecessary ions can be prevented from entering the inside of the ceramic element.
【0028】また、メタリン酸シリコンとシリカ粉を混
合したものは耐溶剤性、耐酸性、耐アルカリ性、耐熱性
を有しているので、セラミック素子の電極形成部分を除
く表面にシリカを主成分とする高抵抗層を形成すること
により、目止めした部分を補強できるとともに、さらに
不必要なイオン、水分のセラミック素子表面への付着、
内部への侵入をより防ぐことができる。そしてメッキや
はんだ付けの際、セラミック素子が侵されるのを防ぐこ
とができる。また、電流負荷時に内部電極がマイグレイ
ションを引き起こさないので、静電容量、バリスタ電圧
等の特性の劣化を防ぐことができる。Further, since a mixture of silicon metaphosphate and silica powder has solvent resistance, acid resistance, alkali resistance and heat resistance, silica is the main component on the surface of the ceramic element excluding the electrode forming portion. By forming a high-resistance layer that protects the sealed part, it is possible to reinforce the part that has been stopped and also to attach unnecessary ions and water to the surface of the ceramic element,
It is possible to further prevent intrusion into the interior. Then, it is possible to prevent the ceramic element from being damaged during plating or soldering. Further, since the internal electrodes do not cause migration when a current is loaded, it is possible to prevent deterioration of characteristics such as capacitance and varistor voltage.
【0029】さらに、本発明はプロセス的にも容易であ
るので、実用上の効果はきわめて大きい。Further, since the present invention is easy in terms of process, the practical effect is extremely large.
【図1】本発明の一実施例における積層型セラミック素
子の一部切欠斜視図FIG. 1 is a partially cutaway perspective view of a multilayer ceramic element according to an embodiment of the present invention.
【図2】本発明の一実施例積層型セラミック素子の製造
工程図FIG. 2 is a manufacturing process diagram of a multilayer ceramic element according to an embodiment of the present invention.
【図3】本発明の一実施例におけるセラミック素子の分
解斜視図FIG. 3 is an exploded perspective view of a ceramic element according to an embodiment of the present invention.
1 セラミック層 3 外部電極 6 高抵抗層 1 Ceramic layer 3 External electrode 6 High resistance layer
Claims (2)
表面の少なくともオープンポアに埋設したメタリン酸シ
リコンとシリカ粉よりなるペーストを硬化させたものと
を備えたセラミック素子。1. A ceramic element comprising: a ceramic element; and a hardened paste of silicon metaphosphate and silica powder embedded in at least open pores on the surface of the ceramic element.
プンポアをメタリン酸シリコンとシリカ粉とを混合した
ペーストで覆い、次にこのペーストを硬化させるセラミ
ック素子の製造方法。2. A method of manufacturing a ceramic element in which at least open pores on the surface of the ceramic element are covered with a paste in which silicon metaphosphate and silica powder are mixed and then the paste is cured.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2187495A JPH08222468A (en) | 1995-02-09 | 1995-02-09 | Ceramic element and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2187495A JPH08222468A (en) | 1995-02-09 | 1995-02-09 | Ceramic element and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH08222468A true JPH08222468A (en) | 1996-08-30 |
Family
ID=12067281
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2187495A Pending JPH08222468A (en) | 1995-02-09 | 1995-02-09 | Ceramic element and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH08222468A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016031992A (en) * | 2014-07-28 | 2016-03-07 | 株式会社村田製作所 | Ceramic electronic component and method of manufacturing the same |
JP2016031988A (en) * | 2014-07-28 | 2016-03-07 | 株式会社村田製作所 | Ceramic electronic component and method of manufacturing the same |
KR20160064260A (en) * | 2014-11-27 | 2016-06-08 | 홍익대학교 산학협력단 | Multi-Layer Ceramic Chip Component having Nano Thin Film Oxide Layer and Method of Manufacturing of the Same |
-
1995
- 1995-02-09 JP JP2187495A patent/JPH08222468A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016031992A (en) * | 2014-07-28 | 2016-03-07 | 株式会社村田製作所 | Ceramic electronic component and method of manufacturing the same |
JP2016031988A (en) * | 2014-07-28 | 2016-03-07 | 株式会社村田製作所 | Ceramic electronic component and method of manufacturing the same |
KR20160064260A (en) * | 2014-11-27 | 2016-06-08 | 홍익대학교 산학협력단 | Multi-Layer Ceramic Chip Component having Nano Thin Film Oxide Layer and Method of Manufacturing of the Same |
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