JPH06177864A - Fault detecting circuit - Google Patents

Abstract

PURPOSE:To realize the discrimination of the intermittent fixed fault and normality being a specific state transition by the circuit of a hardware by detecting the occurrence of a fault in communication information at the reception side of a communication line which transmits fixed length information from the arithmetic result of a fault detection code added to the fixed length information. CONSTITUTION:This circuit is provided with a means which receives and decodes a data signal including an error check code for detecting the error of the communication information of the fixed length, and a means which operates an error correction encoding based on the information of the decoded error check code, and outputs an abnormal or normal state signal. The circuit is provided with a first counting means 13 which inputs the abnormal state signal and counts the number of times of the abnormality, a second counting means 19 which inputs the normal state signal and counts the number of times of the normality, a discrimination value setting means 11 which sets a threshold value for the count value of the first counting means 13, and a means 16 which resets the second counting means 19 when the abnormal state signal is inputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault detection circuit on the receiving side of a data communication line using an exchange, a communication device or the like, and particularly, when a data signal including an error correction code is received, the error correction code The present invention relates to a failure detection circuit that can determine, based on information, whether the failure status is an intermittent failure belonging to an initial abnormality or a continuous fixed failure such as equipment failure.

[0002]

2. Description of the Related Art Generally, a digital data signal transmitted through a data communication line is added to the data signal in order to improve the reliability of the data signal, such as a parity check code or a cyclic code. A redundant code represented by a generator polynomial is added, but a method is known. On the other hand, on the receiving side of the data communication line, as shown in FIG.
As shown in, it is necessary to discriminate between an initial abnormality that occurs intermittently in the initial stage (rising) of data transmission and a fixed failure caused by a device failure and the like, and switch to a standby device if at least the device failure.

Conventionally, as a means for detecting a failure on the receiving side of this type, as shown in FIG. 4, an input received signal 34 is decoded by a decoding circuit 30 and a data signal 35 including an error check code is output. . Error correction coding circuit 31
Performs error detection and outputs the information signal 36 of the detection result. For example, in the case of a parity check coded signal, the error correction coding circuit 31 inputs an input data signal in which a parity check code 1 bit is added to a data signal, and outputs an information signal 36 of an error detection result. Alternatively, when the error correction coding circuit 31 is a cyclic coding system, the data signal 35 in which a plurality of block codes are added to the data signal is input and the information signal 36 of the error detection result is output. The processing device 33 inputs this information signal 36 under software control, and determines the state transition of whether it is an initial abnormality, a fixed abnormality, or a normal state.

Here, the software control of the processing device 33 counts the number of error detections of the information signal 36, and, for example, FIG.
As shown in, if the fault (error) detection code abnormality from the normal state is detected once in a short cycle (for example, 1 minute), it is determined to be an initial abnormality. Further, if the normality is detected continuously m times thereafter, it is determined to be normal. Further, if the number of abnormalities due to a failure is detected once or more consecutively n times from this normal state, it is determined as a fixed abnormality.

[0005]

Since this conventional fault detection circuit uses a processor such as a computer and software for instructing a processing procedure to determine a state transition, it has a state transition confirmation function. There is a major drawback. Therefore, as a communication line, at least the hardware does not judge the state transition. An object of the present invention is to provide a fault detection circuit that can constantly determine a state transition by providing a fault detection circuit configured with simple hardware instead of the above-described processing device.

[0006]

The fault detection circuit of the present invention includes means for receiving and decoding a data signal containing an error check code for detecting an error in fixed-length communication information, and this decoded error check. In a fault detection circuit having means for performing error correction coding based on code information and outputting an abnormal or normal state signal, a first count for inputting the abnormal state signal and counting the number of abnormalities Means, second counting means for inputting the normal state signal and counting the number of normal times, and judgment value setting for setting a threshold value for the count value of the first counting means by a setting signal from the outside. And means for resetting the second counting means when the abnormal state signal is input.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention, which includes a decoding circuit 30, an error correction coding circuit 31A, and a state transition management unit 1. 1, the same reference numerals as those in the conventional example of FIG. 4 have the same functions. That is, the present invention is provided with the state transition management unit 1 configured by hardware described later. FIG. 2 shows a state transition management unit 1 which is a main part of this embodiment.
It is a block diagram of.

Next, the operation of this embodiment will be described. In FIG. 1, the decoding circuit 30 decodes the data signal 35 from the received signal 34. The error correction coding circuit 31A calculates a failure detection code based on the added error correction code.
This calculation result is used as a failure detection code calculation result, and the abnormal signal 15 and the normal signal 20 are notified to the state transition management unit 1 to that effect. The state transition management unit 3 manages a state transition of a failure as shown in FIG.

Next, the processing function of the state transition management unit 1 will be described with reference to FIG. First, the fixed fault detection condition setting register 11 for setting a threshold value for judging the detected fault as a fixed fault is initialized by the register value setting signal 14. In the present embodiment, the fixed fault detection condition setting register 11
Is a 4-bit register and the set value is 3. Fault detection state management counter 13 and failure recovery monitoring counter 19
Are reset by the initial setting signal 17. In this embodiment,
The failure detection state management counter 13 is a 4-bit counter, the failure recovery monitoring counter 19 is a 2-bit counter, and the failure recovery monitoring counter 19 stops counting operation when the counter value = 3.

When the abnormal signal 15 is received as the failure detection code, the counter value of the failure detection state management counter 13 is incremented by 1 and the counter value of the failure recovery monitoring counter 19 is changed by
It resets via the counter reset signal 21. When the normal signal 20 is received as the failure detection code, the counter value of the failure recovery monitoring counter 19 is incremented by one. When the most significant bit of this counter value becomes '1', the counter value of the failure detection state management counter 13 is reset via the counter reset signal 16. When the set value of the fixed fault detection condition setting register and the counter value of the fault detection state management counter 13 match, it is determined that a fixed fault has occurred, and the fixed fault detection signal 12 detects the fixed fault as the next function. Notify the department. Further, the failure detection state management counter 13 stops the counting operation at the time of coincidence. In the failure state transition diagram of FIG. 3, m indicating the number of normal detections after abnormality detection and n indicating the number of abnormal fault detections from the normal detection state are m = 2 and n = 3. When the counter value of the fault detection state management counter 13 is 0, the normal state shown in FIG. 3 is obtained. When the counter value of the fault detection state management counter 13 is 1 or more and less than the set value of the fixed fault detection condition setting register 11, the initial abnormal state shown in FIG. 3 is set. This state is the intermittent failure occurrence state. When the counter value of the fault detection state management counter 13 and the set value of the fixed fault detection condition setting register 11 match, the abnormal state shown in FIG. 3 is set. This state is the fixed fault occurrence state. By thus configuring the state transition management unit 1 with the hardware circuit of FIG. 2, the function of the processing device 33 of the conventional example can be realized.

[0011]

As described above, the present invention is
By configuring the state transition management unit that determines the state transition of the initial abnormality and the fixed abnormality with simple hardware, the failure of the communication information at a specific state transition can be performed without using the large-scale processing device of the conventional example. The effect is that it is possible to identify whether it is intermittent or fixed.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a state transition management unit of this embodiment.

FIG. 3 is a state transition diagram of the present embodiment.

FIG. 4 is a block diagram of a conventional example.

[Explanation of symbols]

 1 State Transition Management Unit 11 Fixed Fault Detection Condition Setting Register 12 Fixed Fault Detection Signal 13 Fault Detection State Management Counter 14 Register Value Setting Signal 15 Fault Detection Code Abnormal Signal 16 Counter Reset Signal 17 Initial Setting Signal 18 Fault Recovery Signal 19 Fault Recovery Monitoring Counter 20 Fault detection code Normal signal 21 Counter reset signal

Claims (1)

[Claims] 1. A means for receiving and decoding a data signal containing an error check code for detecting an error in fixed length communication information, and error correction coding based on the information of the decoded error check code. In a fault detection circuit having a means for outputting an abnormal or normal state signal while performing, a first counting means for inputting the abnormal state signal, counting the number of abnormalities, and the normal state signal are inputted. ,
Second counting means for counting the normal number of times, judgment value setting means for setting a threshold value for the count value of the first counting means by a setting signal from the outside, and time point when the abnormal state signal is input. And a means for resetting the second counting means.