KR950005939B1 - Error correction and error identification device of asynchronous transfer mode cell header - Google Patents

Abstract

In the ATM(Asynchronous Transfer Mode) physical layer, the method processes the error correction and error type identification of ATM cell header. The error type identifies that error is correctable or uncorrectable. The method employs a control block(1) that provides the time information, an error identification block(2) that outputs the error identification number, a buffer(3), a verification block(4) and an error correction block(5).

Description

Error correction and error type identification device of asynchronous transmission mode cell header

1 is a block diagram according to the present invention.

2 is a structural diagram of a control unit.

3 is a structural diagram of a buffer.

4 is a structural diagram of an error identification unit.

5 is a circuit diagram showing the detailed configuration of the verification circuit section (4).

6 is a circuit diagram showing the detailed configuration of the correction circuit section (5).

* Explanation of symbols for main parts of the drawings

1 control unit 2 error identification unit

3: buffer 4: verification circuit

5: crystal circuit part

The present invention provides an apparatus for error correction and error type identification of an asynchronous transfer mode cell header that performs a function of determining and correcting an error type of an ATX cell received by an asynchronous transfer mode subscriber (ATM) subscriber matching unit. It is about.

In general, the physical layer receiver of the ATX network matching unit should have a function of correcting an error for a cell header of 40 bits and correcting an error when an error of one bit occurs. In order to perform such a function, a cell is encoded and transmitted. The receiver performs the above function through decoding. If an error occurs, the receiver must also have an error type identification function that can determine whether the error is a correctable error. An object of the present invention, which is devised to satisfy the above condition, is to provide an apparatus capable of processing error type identification and error correction of an ATM cell header in parallel in an ATM physical layer receiver.

In order to achieve the above object, the present invention provides a control means for providing time information, a buffer for receiving a control signal from the control means and storing an input signal input in parallel in N bits until 40 bits are input, and Verification means for checking whether an error has occurred by inputting 40-bit data of the buffer, and if an error has occurred, an 8-bit output outputs a non-zero value and has a specific value according to the occurrence position of the error; Correction means for informing an error position when an error of one bit occurs and transmitting information about the error position to the buffer to correct an error at the position where the error occurred, and a control signal from the control means. And error identification means for receiving an error identification signal.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram according to the present invention, where 1 is a control unit, 2 is an error identification unit, 3 is a buffer, 4 is a verification circuit unit, and 5 is a correction circuit unit.

Referring to the effects of the error correction and error type identification device of the ATM cell header configured and operated as shown in the drawings as follows.

A control unit 1 for providing time information to each block, and a buffer for receiving the control signal from the control unit 1 and storing the input signal input in parallel in N bits until the 40 bits are input by the control signal 3 ), And receives and decodes 40-bit data output through the buffer 3 and checks whether an 8-bit error has occurred. If an error occurs, the 8-bit output outputs a non-zero value at the error occurrence position. Therefore, the output of the verification circuit section 4 and the output data values of the verification circuit section 4 to have a specific value applies 40 outputs when an error of one bit occurs among the 40 bits of data stored in the buffer 3. 1 is outputted to the output corresponding to the error position to inform the error occurrence position and the information about the error occurrence position to the buffer (3) to correct the error where the error occurs It consists of the portion 5 and the error identifying section (2) for receiving a control signal from the control unit 1 outputs an error identification signal.

Looking at the identification method of the error type by the above configuration.

The verification circuit section 4 checks whether an error occurs with respect to the input signal contained in the buffer 3 and inputs the result to the error identification section 2.

The correction circuit section 5 provides the error identification section 2 with information indicating the error position only when an error of one bit occurs in the input data.

Then, the error identification unit 2 outputs the types of errors as shown in the following <Table 1> with the two pieces of information (here, uncorrectable errors refer to cases where several errors occur).

TABLE 1

[Error type]

2 is a structural diagram of a controller, in which 6 is a counter and 7 is a logic circuit.

It consists of a logic circuit (7) for providing time information to each block by using the output of the counter (6). When looking at the signal to be output, a signal, a buffer (40) to store 40 bits of information in the buffer (3). The error correction timing signal of 3) and a timing signal are output so that the error identification part 2 can output in a correct time.

3 is a structural diagram of a buffer, in which 8 and 10 are multiplexers, 9 is a latch, 11 is an AND gate, and 12 is an inverter.

Looking at the configuration, the buffer 3 is composed of 40 identical buffers.

The multiplexer 8 selects one of the preceding buffer outputs and the new input signal (one of A or B) by the control signal C, and the latch 9 is multiplexed by the multiplexer 8 The signal is input and stored using the control signal D until information of 40 bits is received.

The multiplexer 1 inputs and multiplexes that the output signal of the latch 9 is inverted or left unchanged by the inverter 12, and the AND gate 11 controls the multiplexed signal by the multiplexer 10. In order to multiply the timing signal E from the controller 1 as one input and input the signal F provided from the correction circuit unit 5 as a type force stage, the multiplexer 10 Apply a control signal to determine whether to invert the output signal.

4 is an exemplary configuration diagram of the error identification unit 5, where 14 and 15 are OR gates and 13 are latches, respectively. As shown in the figure, the error identification unit 2 receives an 8-bit output of the verification circuit unit 4 as an input, an OR gate l5 for notifying whether an error occurs, and 40 bits in the correction circuit unit 5. An OR gate 14 for receiving an output and indicating whether or not an error of 1 bit has occurred and a latch 13 for outputting the two signals in accordance with the timing information G of the controller 1.

FIG. 5 is a circuit diagram showing the detailed configuration of the verification circuit section 4. As shown in the drawing, 40 bits of data contained in the buffer 3 are received as inputs and configured with a plurality of exclusive OR gates. Output 8 bits through logic circuit.

FIG. 6 is a circuit diagram showing the detailed configuration of the correction circuit section 5. As shown in the figure, the 8-bit data received by the verification circuit section 4 is received as an input. The number of cases that can be represented by the input 8-bit data is 2 ^{8 in} total. Of these, 40 logic values are used to locate the error when one error occurs among the 40-bit data. The correction circuit unit 5 uses the logic circuit configured to receive the input 8-bit data and combine it with a plurality of inverters and AND gates to identify one error and correct the data correctly.

Therefore, the effect obtained by the present invention having the above-described configuration is not only possible to perform parallel processing of error detection and correction functions in the ATM cell header using a CMOS process, but also to perform an error type identification function. .

Claims (4)

A control means (1) for providing time information, a buffer (3) for receiving a control signal from the control means (1) and storing an input signal coming in N bits in parallel until 40 bits are input, and the buffer Verification means (4) for inputting the 40-bit data of (3) to check whether an error has occurred and if an error has occurred, an 8-bit output outputs a non-D value and has a specific value depending on the error occurrence position; When an error of one bit occurs using the output of the verification means 4, the error position is informed and information about the error position is transmitted to the buffer 3 so as to correct an error at the position where the error occurred. And an error identification means (2) for receiving an control signal from the control means (1) and outputting an error identification signal. 2. The control unit (1) according to claim 1, wherein the control means (1) comprises a counter (6) for counting the number of bits and a logic circuit (7) for providing time information to each block using the output of the counter (6). And an error correction and error type identification device for an ATM cell header. 2. The buffer (3) according to claim 1, wherein the buffer (3) comprises a first multiplexer (8) for selectively outputting the output of the front end buffer and an input signal from the outside by an external control signal, and the first multiplexer (8). A latch means 9 for storing information until the 40-bit information is input using the control signal D as the input of the multiplexed output signal, and the output signal of the latch means 9 is inverted. The control to control the multiplexed signal by the inverter 12, the second multiplexer 10 for multiplexing by applying the inverted output and the pure output of the latching means 9, and the second multiplexer 10 The timing signal E of the means 1 is input as one input, and the signal F provided from the correction means 5 is inputted as a type force stage to perform an AND operation, and then an output signal from the second multiplexer 10. To determine whether to invert And (AN] D) and the error of the ATM cell header modification and error type identification device, characterized in that a gate (11) for outputting the call. 2. The error identifying means (5) according to claim 1, wherein the error identifying means (5) comprises a first OR (OR) gate (15) for notifying whether an error occurs by inputting an 8-bit output of the verifying means (4), and the correcting means ( A second OR gate 14 for receiving a 40-bit output from 5) to indicate whether an error of one bit has occurred, and outputting the output signals of the first and second OR gates l4 and 15 to the control means 1; And a latch means (13) for outputting in accordance with the timing information (G) of the ATM cell header.