JPH02230833A - Data error detecting system for optical interface - Google Patents

Abstract

PURPOSE:To avoid the detection of an error in the case of occurring the blurring of padding data by comparing the counted value of a transmission data sent from a reception circuit side with a counted value detected with a detection circuit detecting a header part to detect an error. CONSTITUTION:A transmission circuit 4 sends a data selected by a selector 5, a transmission data among data is detected by a detection circuit 14 to send the counted value of the transmission data with a counter 15 is sent to a part of a header part. The comparator 17 in a reception circuit 8 compares the counted value counting the transmission data among data sent from the transmission circuit 4 with the counted value from the header part and detects a data error when the counted values are discordant. Thus, when the blurring of the processed data occurres in the padding data during the transmission of data, since no error is detected, it is not required to apply retrial and then no unnecessary time and labor is saved. Consequently, the processing efficiency is improved.

Description

[Detailed Description of the Invention] [Summary] Regarding a data error detection method for an optical interface, we have developed a data error detection method that does not detect an error even if one bit is garbled during data transfer if it is padding data. A selector for selecting a header part indicating the beginning of a frame, a data part having bits indicating the content of the frame and dividing data, and a cyclic check part indicating the end of the frame, and A transfer data detection circuit that detects the transfer data of the header section, and a counter that counts the detected transfer data for each frame and sends the count value as part of the header section. a header part detection circuit that detects the header part, a transfer data detection circuit that detects the transfer data, a counter that counts the detected transfer data, and a comparison circuit that compares the output value of the counter with the output value of the header part detection circuit. and,
is provided to detect normality or abnormality of data transfer based on the output value of the comparison circuit.

[Industrial Application Field] The present invention relates to a data error detection method for an optical interface.

In recent years, with the increase in CPU processing power, the CPU and I/
The number of channels connecting O's continues to increase.

However, such an increase in the number of channels is approaching its limit due to limitations such as installation area. For this reason, channel interfaces are shifting from electrical ones to optical ones, which are smaller and have higher transfer capabilities.

However, current light-emitting elements and light-receiving elements have error rates as high as about 1o-14, so a detection method that efficiently detects data errors is required.

[Prior Art] FIG. 3 shows the type of data transferred on an optical interface. In FIG. 3, one frame includes a header part {FH) 1 indicating the beginning of the frame and containing control data, a data part 2 in which control code or transfer data and padding data are added to the remaining part, and a frame. The cyclic check code section (hereinafter referred to as CRC) is used to indicate the end of the frame and check the normality of one frame of data
)3. Note that the data section has bits for classifying data. Furthermore, if there is no control information or transfer data in the data section, or if the frame is less than one frame, padding data is added and transferred.

Here, FIG. 4 shows a conventional example.

In FIG. 4, 4 is a transmitting circuit, 5A is provided in the transmitting circuit 4, and a selector 5B, which is controlled by a frame counter 6 and sends out a header pattern (FH pattern), data, and CRC at a fixed cycle, is a padding data This is a selector that selects control data or transfer data.There is a C between selector-5A and selector-5B.
A CRC generation circuit 7 for generating an RC code is provided.

8 is a receiving circuit, and the receiving circuit 8 includes a frame counter 9, a frame header section Ft-1 detection circuit 10, and a CRC.
A check circuit 11, a control code detection circuit 12, and a transfer data detection circuit 13 are provided, respectively.

When performing data transfer, the selector 5B selects the transfer data from the padding data, and the transfer data is sent to the receiving circuit 8 via the selector 5A. Further, the CRC generated by the CRC generating circuit 7 is also sent to the receiving circuit 8 via the selector 5A. Receiving circuit 8
On the side, the transfer data is detected by the transfer data detection circuit 13,
The CRC check circuit 11 detected a CRC error.

[Problems to be Solved by the Invention] However, in such a conventional data error detection method, the receiving circuit side detects a CRC error during data transfer in units of one frame, and data is not detected in the padding data. A CRC error is also detected when a garbled image occurs.

For this reason, retries have to be performed, which takes time and effort, and there is a problem in that processing efficiency deteriorates. The present invention has been made in view of such conventional problems, and is a data error detection method that does not detect a CRC error when the data is padding data even if bit corruption occurs during data transfer. The purpose is to provide a method.

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

In FIG. 1, 4 is a transmitting circuit, 5 is a header section provided in the transmitting circuit 4, which indicates the beginning of the frame, a data section having bits that indicate the contents of the frame and separate data, and a cyclic check that indicates the end of the frame. 14 is a transfer data detection circuit that detects the transfer data in the data section; 15 is a transfer data detection circuit that counts the detected transfer data for each frame and sends the count as part of the header section; a counter; 8 is a receiving circuit; 10 is a header detection circuit provided in the receiving circuit 8 and detects the header; 13 is a transfer data detection circuit that detects transfer data free of abnormalities such as parity errors; 16
17 is a counter that counts the detected transfer data, and 17 is a comparison circuit that compares the output value of the counter 16 with the output value of the header portion detection circuit 10.

[Operations] In the present invention, the transmitting circuit transmits the selected data, detects the transferred data among the data, and transmits the count value of the transmitted data as part of the header section, and the receiving circuit transmits the selected data The count value obtained by counting the transferred data among the data sent from the header section is compared with the count value from the header section, and if they do not match, a data error is detected.

Therefore, if garbled data occurs in the padding data during data transfer, no error is detected, so there is no need to perform a retry, which saves time and effort. As a result, processing efficiency can be improved.

[Example] Embodiments of the present invention will be described below based on the drawings.

FIG. 2 is a diagram showing an embodiment of the present invention.

In FIG. 2, 4 is a transmitting circuit, and the transmitting circuit 4 includes a frame counter 6, a first selector 5A, a second selector 58, a CRC generation circuit 7, and a transfer data detection circuit 14.
and a counter 15 are provided, respectively. Second
Selector 5B selects padding data, control code or transfer data. The CRC generating circuit 7 generates a CRC signal indicating the end of the frame based on the output of the second selector 58.
Generates RC (cyclic check section).

The frame counter 6 controls the first selector 5A, and the first selector 5A sends out a head pattern (FH pattern) indicating the beginning of a frame, data, and CRC at regular intervals.

14 is a transfer data detection circuit, and the transfer data detection circuit 14 detects transfer data based on the output of the second selector 5B. 15 is a counter, and the counter 15 receives the input from the frame counter 6 and the transfer data detection circuit 1.
Transfer data is counted based on the input from 4, and this count value is sent out as part of the FH pattern for each frame.

8 is a receiving circuit, and the receiving circuit 8 includes a frame counter 9, an FH detection circuit 10, a CRC check circuit 11, a control code detection circuit 12, a transfer data detection circuit 13, a first counter 16, a comparison circuit 17, and a second counter. 18 are provided respectively.

Frame counter 9 controls FH detection circuit 10 and counter 16, respectively. The FH detection circuit 10 detects the FH pattern and also detects the count 1 to value of transfer data sent as part of the FH pattern. The CRC check circuit 11 checks the CRC in each frame, and if the check result is normal, a normal signal (OK) is sent.
If an error occurs, an error signal (NG) is output. The control code detection circuit 12 detects a control code and outputs the control code. Further, the transfer data detection circuit 13 detects that the transferred data is transfer data based on the identifier added to each byte, which is the transfer unit in one frame, and if it is transfer data, performs a parity check. If the data is determined to be normal, the transferred data is output.

The counter 16 counts the normal transfer data detected by the transfer data detection circuit 13 in units of bytes for each frame and outputs the counted data to the comparison circuit 17 . Comparison circuit 17 includes counter 1
The byte count value of the transfer data for each frame from 6 is compared with the byte count value of the transfer data detected by the FH detection circuit 10, and if they do not match, an error signal is output.

The counter 18 counts up when the result of checking each frame from the CRC check circuit 11 is a CRC error (NG), and the counter 18 counts up when the check result for each frame from the CRC check circuit 11 is normal (OK>
It will be reset if

That is, in the present invention, the CRC check circuit 11
A CRC error is not immediately recognized as an error, but is determined as a CRC error only when a CRC error occurs multiple times, for example, in three consecutive frames.

With this configuration, a CRC error is not detected when data is garbled during data transfer, and a CRC error occurs only when a hardware error occurs.

Next, the operation will be explained.

Normally, the second selector 5B selects and outputs the padding data. If transfer data exists, the second selector 5B selects and outputs the transfer data. Transfer data is sent to the receiving circuit 8 via the first selector 5A.
will be sent to.

The transfer data detection circuit 14 determines whether the output of the second selector 5B is transfer data, and if it is transfer data, it detects this and outputs it to the counter 15. The counter 15 sends out the counter value of transfer data as part of the FH pattern for each frame.

On the receiving circuit 8 side, a transfer data detection circuit 13 determines whether or not the transmitted data is transfer data, based on an identifier added to the beginning of each byte, and if it is transfer data, it is detected.

In other words, at the beginning of the byte-by-byte data in the transmitted frame, there is an identifier bit that distinguishes whether the padding data is a control code or transfer data, and by detecting this, it can be determined whether it is transfer data or not. are distinguished and detected.

Then, as it was detected that the data was transferred,
A parity check is performed, and if normal, this data is sent.

On the other hand, the FH detection circuit 10 detects the count value (number of bytes) of transfer data present in the frame sent as part of the FH pattern provided at the beginning of each frame, and this byte count value is , and is sent to the comparison circuit 17, which compares the byte count value from the FH detection circuit 10 and the byte count value from the counter 16, and outputs an error signal if they do not match.

In this way, instead of detecting software errors using conventional CRC errors, the count value of the transfer data on the transmitting circuit 4 side and the count value of the transfer data on the receiving circuit 8 should match, and if they do not match, It is determined that an error has occurred in the transferred data.

Therefore, if one bit is garbled during data transfer,
Conventionally, even if it is padding data, it is detected as a CRC error, but in the present invention, since it is not counted as transfer data, no error signal is output. That is, if garbled data occurs in the padding data during data transfer, it will not be detected as an error.

Therefore, in this case, since a trial is not performed, which is conventionally performed, it is possible to save time and effort and improve processing efficiency.

[Effects of the Invention] As explained above, according to the present invention, the transmitting circuit side sends the count value of the transferred data as part of the header section, and the receiving circuit side transmits the count value of the transferred data. Since error detection is performed by comparing the count value detected by the detection circuit that detects the header portion, no error will be detected if garbled data occurs in the padding data during data transfer.

Therefore, in this case, there is no need to perform a beam trial, which saves time and effort, so that processing efficiency can be improved.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a block diagram showing an embodiment of the invention, Fig. 3 is a diagram showing the format of data transferred on the optical interface, and Fig. 4 is a conventional example. FIG. In the figure, 1... Header part, 2... Data part, 3... Cyclic check part, 4... Transmission circuit, 5... Selector 5A... First selector 5B... First 2 Selector 6... Frame counter, 7... CRC generation circuit, 8... Receiving circuit, 9... Frame counter, 10... Header section detection circuit, 11... CRC check circuit, 12. ...Control code detection circuit, 13.14...Transfer data detection circuit, 15.16...
・Counter, 7... Comparison circuit.

Claims (1)

[Claims] A transmitting circuit (4) is provided with a selector (5) for selecting a header section indicating the beginning of the frame, a data section having bits indicating the content of the frame and dividing data, and a cyclic check section indicating the end of the frame, and the data section. A transfer data detection circuit (14) for detecting the transfer data of the data, and a counter (15) for counting the detected transfer data for each frame and transmitting the count value as part of the header section are provided. The circuit (8) includes a header part detection circuit (10) for detecting the header part, a transfer data detection circuit (13) for detecting normal transfer data, and a counter (16) for counting the detected transfer data. A comparison circuit (17) is provided to compare the output value of the counter (16) and the output value of the header part detection circuit (10), and the output value of the comparison circuit (17) is used to determine whether the data transfer is normal or abnormal. A method for detecting data errors in optical interfaces.