JPH06177728A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To reduce the rising time while employing a resistor having a large resistance without increasing the circuit scale. CONSTITUTION:When the state of an input signal 100 transits to the low level state, a P-channel transistor(TR) T12 is turned on and an N-channel TR T11 is turned off. While an output 101 of an inverter circuit 2 transits to a high level after the input signal 100 transits to a low level, P-channel TRs 10 and 12 are turned on and an output 102 reaches a high level. When the inverter circuit 2 reaches a high level, the P-channel TRs 10 and 12 and an N-channel TR 11 are all turned off. In this case, the output 102 has already be in the high level and the high level state is held by an external pull-up resistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit, and more particularly to an open drain type output buffer circuit in a CMOS integrated circuit.

[0002]

2. Description of the Related Art Conventionally, in this type of output buffer circuit, as shown in FIG. 3A, the source side is composed of only an N-channel transistor T41 whose ground is connected to the low potential side (GND) of the power supply. , The N-channel transistor T41 is controlled by the input signal 400.

Since the N-channel transistor T41 is on when the input signal 400 is in the high level state, the output 401 which is the drain thereof is in the low level state. After that, when the input signal 400 transits from the high level state to the low level state, the N-channel transistor T41 is turned off and the output 401 becomes the high impedance state.

In the above open drain type output buffer circuit 5, as shown in FIG. 3B, the outputs 401 of the plurality of output buffer circuits 5a to 5c are wire-connected to be connected to another input buffer 3. Is the common usage. However, at that time, when all the output buffer circuits 5a to 5c are turned off, the wired signal line W is in a high impedance state, and a through current is generated in the input buffer 3. In order to prevent this, at this time, the signal line W is set to the high level state by the pull-up resistor Ru.

In the output buffer circuit 5 described above, if a pull-up resistor Ru having a large resistance value is used, the output 401 changes from a low level state to a high level state as shown in FIG. 3 (c). Takes a long time, and may lead to malfunction when applied to a circuit that operates at high speed.

On the other hand, when a pull-up resistor Ru having a small resistance value is used, a through current becomes large when the output 401 is in a low level state, which causes deterioration of the output level and increase of power consumption. . That is, there is a conflicting requirement that the resistance value must be reduced in order to operate at high speed, but the resistance value must be increased in order to prevent deterioration of the output level and increase in power consumption.

To solve this problem, Japanese Patent Laid-Open No. 62-
The technique disclosed in Japanese Patent No. 249522 has been proposed. That is, according to this technique, in the output buffer circuit 6, as shown in FIG. 4A, the source side is connected to the high potential side (VDD) of the power supply, and the source side is connected to the low potential side of the power supply. The drains of the N-channel transistors T51 grounded to (GND) are connected to each other, and this connection point is used as the output 502.

Both the N-channel transistor T51 and the pulse generation circuit 7 are controlled by the input signal 500, and the P-channel transistor T50 is controlled by the output 501 of the pulse generation circuit 7. The pulse generation circuit 7 generates a low level pulse only when the input signal 500 transits from a high level state to a low level state,
In other states, it is always in the high level state.

Here, when the input signal 500 is in the high level state, the P-channel transistor T50 is in the off state and the N-channel transistor T51 is in the on state, so that the output 502 is in the low level state. afterwards,
When the input signal 500 transits from the high level state to the low level state, the N-channel transistor T51 is turned off and the pulse generation circuit 7 generates a low level pulse.

When the pulse generation circuit 7 outputs a low level pulse, the P-channel transistor T50
Is turned on, the output 502 is in a high level state. Then, when the output 501 of the pulse generation circuit 7 becomes the high level state and the low level pulse disappears, the P-channel transistor T50 is turned off again, so that the output 502 is not driven at either the high level or the low level. Since it is in the high level state, the external pull-up resistor Ru holds this state.

A method of using the above output buffer circuit 6 is shown in FIG. 4 (b), and its operation waveform is shown in FIG. 4 (c). Similar to the method shown in FIG. 3B, the method of use is to wire-connect the outputs 502 of the plurality of output buffer circuits 6a to 6c and connect them to another input buffer 3. Also in this case, in order to prevent the wired signal line W from being in a high impedance state and causing a through current in the input buffer 3, the pull-up resistor Ru holds the signal line W in a high level state.

[0012]

In the above-mentioned conventional output buffer circuit, the rise time is increased while the pull-up resistor having a large resistance value is used by driving the output signal once to the high level by using the pulse generating circuit. Making it short.

Considering the simplest configuration of this pulse generating circuit, the circuit is as shown in FIG. 5 (a). That is, the pulse generating circuit 7 is composed of a NOR circuit 8 and an inverter circuit 9 whose operating speed is sufficiently slower than the operating speed of the NOR circuit 8. The input signal 500 is directly input to one of the NOR circuits 8 and the signal 601 obtained by inverting the input signal 500 by the inverter circuit 9 is input to the other. The output of the NOR circuit 8 becomes the output 501 of the pulse generating circuit 7.

Here, the input signal 5 to the pulse generation circuit 7
When 00 is in the high level state, its output 501 is also in the high level state. After that, when the input signal 500 to the pulse generation circuit 7 transits from the high level state to the low level state, the output 501 corresponding to the delay of the inverter circuit 9 is output.
Becomes a low level state, but thereafter, the output 501 stabilizes in a high level state [see FIG. 5 (c)]. When the input signal 500 to the pulse generation circuit 7 transits from the low level state to the high level state, no pulse is generated.

Considering the transistor level equivalent circuit of the pulse generation circuit 7, the circuit is as shown in FIG. 5 (b). That is, the pulse generation circuit 7 includes N-channel transistors T60, T62, T63, T66, P
Channel transistors T61, T64, T65, T6
7 and 7.

In the output buffer circuit described above, the pulse generating circuit is used to shorten the rise time while using the pull-up resistor having a large resistance value. Therefore, even if the pulse generating circuit is the simplest, the pulse generating circuit is used. The generation circuit alone requires 8 transistors, the entire output buffer circuit requires 10 transistors,
There is a problem that the circuit scale is increased.

Therefore, an object of the present invention is to provide an output buffer circuit which can shorten the rise time while using a resistor having a large resistance value without increasing the circuit scale.

[0018]

SUMMARY OF THE INVENTION An output buffer circuit according to the present invention is of a reverse conductivity type in which an input signal is applied by serially connecting one to one of power supply terminals and commonly connecting control electrodes to each other. An output signal of the delay means, which is connected in series between the first and second transistors, a delay means for inverting and delaying the input signal, and the other of the power supply terminal and the first and second transistors. A third transistor that delays the same operation as the transistor connected to one of the power supply terminals of the first and second transistors, and connects the first and second transistors in series. I am trying to output points.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1A is a circuit diagram showing an embodiment of the present invention. In the figure, in the output buffer circuit 1, P-channel transistors T10, T12 and N-channel transistor T11 are connected in series between the high potential side (VDD) of the power source and the low potential side (GND) of the power source.

In this case, the P-channel transistor T1
The source side of 0 is connected to the high potential side of the power supply, and the source side of the N-channel transistor T11 is grounded to the low potential side of the power supply. In addition, the P-channel transistor T12
The drains of the N-channel transistor T11 and the N-channel transistor T11 are connected to each other, and the connection point serves as the output 102.

The P-channel transistor T12 and the N-channel transistor T11 are controlled by the input signal 100, and the P-channel transistor T10 is controlled by the output 101 of the inverter circuit 2. Also,
The inverter circuit 2 is also controlled by the input signal 100.

The gate width of the inverter circuit 2 is sufficiently smaller than the gate widths of the P-channel transistors T10 and T12 and the N-channel transistor T11. The gate length of the inverter circuit 2 is sufficiently longer than the gate lengths of the P-channel transistors T10 and T12 and the N-channel transistor T11.

That is, the operating speed of the inverter circuit 2 is sufficiently slower than the operating speeds of the P-channel transistors T10 and T12 and the N-channel transistor T11.

FIG. 1B is a block diagram showing a usage example of the output buffer circuit 1 shown in FIG. In the figure, the outputs 102 of the plurality of output buffer circuits 1 a to 1 c are wired-connected and connected to another input buffer 3.

When all the output buffer circuits 1a to 1c are turned off, the wired signal line W is in a high impedance state to prevent a through current from being generated in the input buffer 3. A pull-up resistor Ru is connected to W. As a result, even in the above-mentioned state, the signal line W has the pull-up resistance Ru.
Holds the high level state.

FIG. 1 (c) is a time chart showing the operation of the output buffer circuit 1 in the use example shown in FIG. 1 (b). The operation of the embodiment of the present invention will be described with reference to FIGS.

First, when the input signal 100 is in the high level state, the P-channel transistor T12 is in the off state and the N-channel transistor T11 is in the on state, so that the output 102 is in the low level state. At this time,
The P-channel transistor T10 is on.

Thereafter, when the input signal 100 transits from the high level state to the low level state, the P channel transistor T12 is turned on and the N channel transistor T11 is turned off.

In response to the transition of the input signal 100 to the low level state, the output 101 of the inverter circuit 2 slowly transitions from the low level state to the high level state, so that the inverter circuit after the input signal 100 transits to the low level state. Until 2 transits to the high level state,
Both P-channel transistors T10 and T12 are turned on. As a result, the output 102 quickly goes to the high level state.

When the inverter circuit 2 transits to the high level state, the P channel transistor T10 is turned off in response to the output 101 thereof. In this state, the P-channel transistors T10 and T12 and the N-channel transistor T11 are all turned off.

For this reason, the output 102 is not driven to either the high level or the low level, but the output 102 is already in the high level state, and this high level state is held by the pull-up resistor Ru.

FIG. 2A is a circuit diagram showing another embodiment of the present invention. In the figure, in the output buffer circuit 4, a P-channel transistor T12 and N-channel transistors T11 and T21 are connected in series between the high potential side (VDD) of the power source and the low potential side (GND) of the power source.

In this case, the P-channel transistor T1
The source side of 2 is connected to the high potential side of the power supply, and the source side of the N-channel transistor T21 is grounded to the low potential side of the power supply. In addition, the P-channel transistor T12
The drains of the N-channel transistor T11 and the N-channel transistor T11 are connected to each other, and the connection point serves as the output 202.

The P-channel transistor T12 and the N-channel transistor T11 are controlled by the input signal 200, and the N-channel transistor T21 is controlled by the output 201 of the inverter circuit 2. Also,
The inverter circuit 2 is also controlled by the input signal 200.

The gate width of the inverter circuit 2 is the P channel transistor T12 and the N channel transistor T.
It is sufficiently smaller than the gate width of 11 and T21. The gate length of the inverter circuit 2 is the P channel transistor T12 and the N channel transistor T1.
It is sufficiently longer than the gate length of T21.

That is, the operating speed of the inverter circuit 2 is sufficiently slower than the operating speeds of the P-channel transistor T12 and the N-channel transistors T11 and T21.

FIG. 2B is a block diagram showing a usage example of the output buffer circuit 4 shown in FIG. In the figure, the outputs 202 of the plurality of output buffer circuits 4 a to 4 c are wired-connected and connected to another input buffer 3.

When all the output buffer circuits 4a to 4c are turned off, the signal line W connected to the wiring is prevented from being in the high impedance state and the through current is generated in the input buffer 3. A pull-down resistor Rd is connected to W. As a result, even in the above-described state, the signal line W has the pull-down resistor Rd.
Holds the low level state.

FIG. 2C is a time chart showing the operation of the output buffer circuit 4 in the use example shown in FIG. 2B. The operation of another embodiment of the present invention will be described with reference to FIGS. 2 (a) to 2 (c).

First, when the input signal 200 is in the low level state, the N-channel transistor T11 is in the off state and the P-channel transistor T12 is in the on state, so that the output 202 is in the high level state. At this time,
The N-channel transistor T21 is on.

After that, when the input signal 200 transits from the low level state to the high level state, the N-channel transistor T11 is turned on and the P-channel transistor T12 is turned off.

In response to the transition of the input signal 200 to the high level state, the output 201 of the inverter circuit 2 slowly transits from the high level state to the low level state, so that the input signal 200 transits to the high level state. Until the inverter circuit 2 transits to the low level state,
Both N-channel transistors T11 and T21 are turned on. As a result, the output 202 quickly goes to the low level state.

When the inverter circuit 2 transits to the low level state, the N channel transistor T21 is turned off in response to its output 201. In this state, the P-channel transistor T12 and the N-channel transistors T11 and T21 are all turned off.

Therefore, the output 202 is not driven to either the high level or the low level, but since the output 202 is already in the low level state, this low level state is held by the pull-down resistor Rd.

In this way, the P-channel transistor T12 and the N-channel transistor T11 of opposite conductivity type, which are connected in series with each other, one of which is connected with one of the power supply terminals and whose control electrodes are commonly connected with each other, and the control electrodes thereof are input. An inverter circuit 2 that inverts and delays the input signals 100 and 200 that are input, the other of the power supply terminals, a P-channel transistor T12 and an N-channel transistor T11
Is connected in series with the output signal 1 of the inverter circuit 2.
01, 201 allows P-channel transistor T12
And N-channel transistor T11 and a P-channel transistor T10 or an N-channel transistor T21 that delays the same operation as the transistor connected to one of the power supply terminals, and the P-channel transistor T12 and the N-channel transistor T11 are connected to each other. By using the outputs 102 and 202 at the serial connection points, it is possible to configure with 5 transistors when the CMOS transistors are entirely configured. Therefore, even if the configuration is the simplest, compared with the conventional example that requires 10 transistors. The circuit scale can be reduced.

Further, with the above configuration, the time for the low level state to transition to the high level state in the N-channel open drain type output buffer circuit 1 or the high time in the P-channel open drain type output buffer circuit 4. It is possible to shorten the time required for the outputs 102 and 202 indicating the time required to transit from the level state to the low level state to the disabled state.

Therefore, without increasing the circuit scale,
The rising time can be shortened while using the pull-up resistor Ru or the pull-down resistor Rd having a large resistance value.

Although the MOS transistor is used in the above embodiment, a bipolar transistor may be used. In that case, the P channel transistor may be a PNP transistor and the N channel transistor may be an NPN transistor. Good.

[0050]

As described above, according to the present invention, the reverse conductivity type first electrodes are connected in series with each other, one of them is connected to one of the power supply terminals, the control electrodes are commonly connected with each other, and an input signal is applied. 1 and 2 transistors, a delay means for inverting and delaying the input signal thereof, and a series connection between the other of the power supply terminals and the 1st and 2nd transistors,
A first transistor and a second transistor which are connected to one of the power supply terminals of the first and second transistors by delaying the same operation by the output signal of the delay means, and the first and second transistors are connected to each other. By using the serial connection point of as an output, it is possible to shorten the rise time without increasing the circuit scale while using a resistor having a large resistance value.

[Brief description of drawings]

FIG. 1A is a circuit diagram showing an embodiment of the present invention,
(B) is a block diagram showing a usage example of the output buffer circuit shown in (a), and (c) is an operation waveform diagram of the output buffer circuit in the usage example shown in (b).

2A is a circuit diagram showing another embodiment of the present invention, FIG.
(B) is a block diagram showing a usage example of the output buffer circuit shown in (a), and (c) is an operation waveform diagram of the output buffer circuit in the usage example shown in (b).

FIG. 3A is a circuit diagram showing a conventional example, and FIG.
Block diagram showing an example of use of the output buffer circuit shown in
(C) is an operation waveform diagram of the output buffer circuit in the usage example shown in (b).

FIG. 4A is a circuit diagram showing a conventional example, and FIG. 4B is a circuit diagram.
Block diagram showing an example of use of the output buffer circuit shown in
(C) is an operation waveform diagram of the output buffer circuit in the usage example shown in (b).

5A is a circuit diagram showing the pulse generating circuit shown in FIG. 4A, FIG. 5B is a transistor-level equivalent circuit diagram of the pulse generating circuit shown in FIG. 4A, and FIG. 6 is an operation waveform diagram of the pulse generation circuit shown in FIG.

[Explanation of symbols]

1 N-channel open drain type output buffer circuit 2 Inverter 3 Input buffer 4 P-channel open drain type output buffer circuit T10, T12 P-channel transistor T11, T21 N-channel transistor Ru Pull-up resistor Rd Pull-down resistor

Claims (4)

[Claims] 1. Reverse-conductive first and second transistors connected in series, one of which is connected to one of power supply terminals, control electrodes of which are commonly connected to each other, and an input signal is applied, and the input signal. Delay means for inverting and delaying
A transistor connected in series between the other of the power supply terminals and the first and second transistors, and connected to one of the power supply terminals of the first and second transistors according to the output signal of the delay means; A third transistor performing the same operation with a delay, the first and second transistors
An output buffer circuit, wherein the series connection point between the transistors is output. 2. The output buffer circuit according to claim 1, wherein the first and second transistors and the third transistor are each composed of a MOS transistor. 3. The output buffer circuit according to claim 2, wherein the third transistor is a P-channel transistor, and the transistor connected to one of the power supply terminals is an N-channel transistor. . 4. The output buffer circuit according to claim 2, wherein the third transistor is an N-channel transistor, and the transistor connected to one of the power supply terminals is a P-channel transistor. .