JPH06177248A - Automatic method for block layout of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To hold a delay from an external clock terminal to a clock terminal of an internal flip-flop at a minimum limit and prevent a skew of a clock signal to be applied to the clock terminal of each flip-flop. CONSTITUTION:A clock generator 104 having a plurality of different clock output signals to a clock input terminal 101 is provided. The clock output signal having a large skew delay of the generator 104 is connected to a flip-flop 101 disposed near the generator 104. The clock output signals (b), (c) having small skew delay of the generator 104 are connected to the flip-flops 102, 103 disposed at a long distance from the generator 104.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit designed by an automatic layout method, and more particularly to a method of arranging blocks of a semiconductor integrated circuit for driving a plurality of flip-flop circuits with the same clock signal.

[0002]

2. Description of the Related Art Conventionally, a method called an equal-length wiring method for clock signals is known as one of automatic layout methods for semiconductor integrated circuits. This is to prevent malfunction of the circuit due to the wiring delay of the metal wiring. FIG. 3 shows an example of a circuit that malfunctions due to the wiring delay of the metal wiring. As shown in the waveform diagram of FIG. 3B, the clock signal 31 and the clock signal 32 delayed by the wiring resistance 35 and the wiring capacitance 36 rise and fall of the clock due to the influence of the wiring resistance 35 and the wiring capacitance 36. There is a time difference between the timings (hereinafter, this timing is referred to as skew). Therefore, the clock signal input to the flip-flop 38 lags behind the clock signal input to the flip-flop 37.

In the circuit shown in FIG. 3A, a malfunction occurs when the shift register is operated. That is, the flip-flop 38 stores the data (FIG. 3B) before it is changed by the clock signal of the flip-flop 37.
However, since the clock signal is delayed, there is a problem in that the data (DATA2 in FIG. 3B) after being changed by the clock signal is read.

In order to prevent such an erroneous operation, conventionally, a layout method using equal-length wiring as shown in FIG. 4 has been used.

In FIG. 4, in a semiconductor integrated circuit 300 according to the automatic layout method, a clock signal is transmitted from the external clock input terminal 111 to the semiconductor integrated circuit via the input buffer 302.

Clock signal buffer circuits 303 to 32
3, the buffers 303 are arranged symmetrically with respect to the buffer 303 as shown in FIG. 4. Further, in the buffer arranged in the left half portion, the buffers 304 and 305 are symmetrical in the vertical direction and the wiring length is They are arranged so that they are equal.

Next, the buffer 3 is symmetrical with respect to the left and right with respect to the buffer 304 and has the same wiring length.
12 and buffer 314, buffer 313 and buffer 31
5 are arranged, and the buffer 312, the buffer 314, the buffer 313, and the buffer 315 are arranged vertically symmetrically and have the same wiring length. Further, a flip-flop 326 is provided at the output end of the buffer 314.
If necessary, other flip-flops are connected to the output terminals of the buffers 312, 313, 315.

Further, the buffer 308 and the buffer 310 and the buffer 309 and the buffer 3 are symmetrically arranged with respect to the buffer 305 so that the wiring lengths are equal to each other.
11 are arranged respectively, and the buffer 308 and the buffer 31 are arranged.
0, the buffer 309 and the buffer 311 are symmetrical in the vertical direction and are arranged so that the wiring lengths are equal. Further, flip-flops are connected to the output terminals of the buffers 308 to 311 as needed.

The wiring of the right half of the buffer 303 is performed in the same manner as the arrangement of the left half described above, and these arrangements are first forcibly arranged and wired. Flip-flops 324, 3
25 and 326 are buffers 314 and 32 as described above.
It is connected only from the unend portion of 0,321.

In the semiconductor integrated circuit manufactured by the conventional equal layout wiring method such as the automatic layout method, the buffers 308 to 311 and 312 from the input buffer 302 to the unfinished buffers irrespective of the location inside the semiconductor integrated circuit. ~ 3
The delay times from 15,316 to 319 and 322 to 325 are the same.

Therefore, the flip-flops 324, 32
Also at the clock input terminals of 5,326, no phase difference between the clock signals occurs, and malfunction does not occur.

[0012]

However, although this conventional equal-length wiring method can prevent the skew of the clock signal connected to each flip-flop, the clock input of the input buffer of the first stage and the clock input of the flip-flop are prevented. Since a plurality of buffers are inserted between the terminals, there is a problem that the delay from the input buffer at the first stage to the clock input terminal of the flip-flop becomes very large.

In particular, when the external clock signal is supplied to a plurality of semiconductor integrated circuits and the data of the flip-flop is transferred between the plurality of semiconductor integrated circuits in synchronization with the clock signals, the above-mentioned operation is performed. If the delay time is long, there is a drawback that a malfunction is likely to occur in timing.

An object of the present invention is to eliminate the above-mentioned conventional drawbacks and to apply it to the clock terminal of the flip-flop while keeping the delay time from the external clock terminal to the clock terminal of the internal flip-flop to a minimum. It is an object of the present invention to provide a method for arranging blocks in a semiconductor integrated circuit, which prevents generation of skew of a clock signal to be generated.

[0015]

SUMMARY OF THE INVENTION An object of the present invention is to provide a block input method for a semiconductor integrated circuit by an automatic layout method having a plurality of flip-flop circuits and a clock generation circuit for driving the flip-flop circuits. On the other hand, a flip-flop circuit having a clock generating circuit for generating a plurality of clock output signals having different rising and falling timings of the clock is provided in the flip-flop circuit arranged close to the clock generating circuit. A clock output signal with a large timing delay is connected, and a clock output signal with a small timing delay of the clock generation circuit is connected to a flip-flop circuit wired at a position where the wiring length is long from the clock generation circuit. It was arranged as follows.

Further, the clock generation circuit can be arranged at the center of the semiconductor integrated circuit.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing the layout of layout blocks according to the first embodiment of the present invention.

According to FIG. 1, the external clock terminal 111 of the semiconductor integrated circuit 100 with automatic wiring is connected to the input end of the clock generation circuit 104, and the delay circuit 109 and the inverter are connected from the input end of the oscillator circuit 104 through the inverter 105. Connected to 106.

The output terminal of the delay circuit 109 is connected to the delay circuit 110 and the inverter 107, and the delay circuit 11
The output terminal of 0 is connected to the inverter 108. Furthermore,
The output end of the inverter 108 has a wiring length a and is connected to the flip-flop 102, and the output end of the inverter 107 has a wiring length b.
The flip-flop 103 and the output terminal of the inverter 106 are connected to the flip-flop 101 with the wiring length c. Here, the relationship of wiring length is a <b <c
Is.

Next, a description will be given of a clock signal line and a block layout design procedure for the block layout method of the semiconductor integrated circuit according to the automatic layout method of the present invention.

First, the basic function blocks are arranged based on the circuit connection information, which is the connection data between the respective functional blocks, created from the circuit diagram. The basic function block is a block in a basic logic element unit such as a NAND gate, a NOR gate, an inverter in addition to a flip-flop, and the layout is performed using these basic function blocks.

Next, the clock generation circuit 104 is arranged. The clock generating circuit 104 has a plurality of clock output terminals, and the signal at each clock output terminal has a skew slightly different from that of the input signal of the clock generating circuit 104.

For example, the output of the inverter 107 is delayed in phase with respect to the clock signal by the delay time of the delay circuit 109, and the output signal of the inverter 108 is different in skew by the delay time of the delay circuits 109 and 110.

Next, the arranged flip-flops 101
-10 to calculate the distance between the clock generation circuit 104,
The circuit connection information between the clock generation circuit 104 and the clock terminals of the flip-flops 101 to 103 is changed according to the distance.

That is, to the flip-flop 102 located at a short distance, the clock output terminal of the clock generation circuit 104 having a large skew delay is connected (wiring a).

Further, clock output terminals with a small skew delay are connected to the flip-flops 101 and 103 located at long distances (wirings b and c).

Based on such circuit connection information, automatic wiring is performed using an automatic layout tool.

In the semiconductor integrated circuit 100 designed by the method described above, the skew of the clock signal is adjusted inside the clock generation circuit. Therefore, when viewed from the clock terminal side of the flip-flops 101 to 103, no skew occurs in the input clock signal.

From the external clock input terminal 111,
The signal delay to the clock terminals of the flip-flops 101 to 103 can be suppressed to the minimum.

Next, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a diagram showing the layout of layout automatic wiring blocks according to the second embodiment.

The second embodiment differs from the first embodiment shown in FIG. 1 in that the clock oscillator circuit 202 is arranged in the central portion of the semiconductor integrated circuit 200.

According to FIG. 2, the flip-flop 203 has a wiring length d, the flip-flop 204 has a wiring length e, and the flip-flop 20 has an output terminal of the clock oscillation circuit 202.
5 is a wiring length f + g, and the flip-flop 206 is a wiring length f + h. Here, the relationship of the wiring length is d <e <(f + g) <(f + h).

Therefore, the maximum value of the wiring length when the clock generating circuit 202 is arranged at the non-end portion of the semiconductor integrated circuit 200 is smaller than that of the first embodiment shown in FIG. That is, the relationship is c> (f + h).

As a result, in order to correct the delay time due to the metal wiring connecting these flip-flops,
The number of delay circuits built in the clock generation circuit 202 can be reduced.

[0037]

As described above, according to the present invention, in the automatic layout wiring of the semiconductor integrated circuit, there is provided the clock generation circuit for distributing the clock input from the outside to the clock terminal of the flip-flop arranged inside. However, a clock output signal with a large skew delay of the clock generation circuit is connected to the flip-flop arranged close to the clock generation circuit, and a flip-flop arranged long from the clock generation circuit is connected to the clock generation circuit. By connecting the clock output signals b and c having a small skew delay, the number of buffers connected between the clock signal input from the outside and the clock terminal of the flip-flop can be reduced.

Therefore, it is possible to prevent the skew of the clock signal due to the wiring length from the clock generation circuit to each flip-flop while keeping the delay from the external clock terminal to the flip-flop terminal to a minimum. Have.

[Brief description of drawings]

FIG. 1 is a diagram showing a block layout of an automatic layout according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a block layout of an automatic layout according to a second embodiment of the present invention.

3A and 3B are an example of a circuit diagram (a) and an operation waveform diagram (b) for explaining a malfunction due to a delay of a metal wiring in a conventional example.

FIG. 4 is a diagram showing a block layout of an automatic layout of a conventional example.

[Explanation of symbols]

100, 200, 300 Semiconductor integrated circuit 111 External clock terminal 101, 102, 103, 203, 204, 205, 2
06 flip-flop 104,202 clock oscillation circuit 105-108 inverter 109,110 delay circuit a, b, c, d, e, f, g, h wiring length

Claims (2)

[Claims] 1. A method for arranging blocks in a semiconductor integrated circuit according to an automatic layout method comprising a plurality of flip-flop circuits and a clock generation circuit for driving the flip-flop circuits, wherein clock rising and falling timings with respect to a clock input signal. Of the clock generation circuit for generating a plurality of different clock output signals, and the flip-flop circuit arranged close to the clock generation circuit is provided with a clock output signal having a large timing delay of the clock generation circuit. The flip-flop circuit connected to the flip-flop circuit having a long wiring length from the clock generation circuit is arranged so that the clock output signal with the small timing delay of the clock generation circuit is connected. Automatic layout method for semiconductor integrated circuit Lock placement method. 2. The method for arranging blocks in a semiconductor integrated circuit according to claim 1, wherein the clock generation circuit is arranged in a central portion of the semiconductor integrated circuit.