JPH05206792A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To eliminate the metallic skews caused by the delay of a wiring by omitting the need to confirm the holding time of an FF that is always required for development of a gate array. CONSTITUTION:The signals inputted to a clock C of a flip-flop FF 1 are outputted to the outside via the inverters 10 and 11. When a shift register consists of plural pieces of FF 1, the CO output of each FF is inputted to the clock C of the FF of the precedent stage. Thus the FF of the next stage always starts first. Thus it is possible to omit the need to confirm the FF holding time and to evade the malfunctions due to the metallic skews. Therefore it is not required to confirm the holding time in a development state nor to confirm the metallic skew after the wiring. As a result, the designing of a flip-flop circuit is extremely facilitated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a flip-flop (F
F) The present invention relates to a circuit, and more particularly to a logic circuit of a special purpose semiconductor integrated circuit represented by a gate array standard cell.

[0002]

2. Description of the Related Art Conventional FF circuits are often used in shift register circuit configurations as shown in FIGS.

In FIG. 4, this shift register has D-type flip-flops 14 and 15, an input signal IN1 is applied to the D input of the flip-flop 14, and its Q output is passed through the C point to the D input of the next stage. Applied to. A clock input signal IN2 is applied to each C input. Output O
UT is obtained as the Q output of flip-flop 15.

In FIG. 5, a D-type flip-flop 1
6 and 17, the C input of the flip-flop 16 is
The clock input signal IN2 is applied via the buffer 18.

In FIG. 6, the Q of the flip-flop 19 is shown.
The output is output from the flip-flop 20 via the buffer 21.
Applied to the D input of.

Next, the operation of FIGS. 4, 5, and 6 will be described with reference to FIG. In FIG. 7, the data input signal IN
1, the clock input signal IN2, and the signal at the point C are shown. In FIG. 7, a time difference TH is a time difference between clock input and data input signal transmission.

First, in order for the 2-bit shift register structure of FIG. 4 to operate normally, the time difference between the data (D) input of the flip-flop (FF) 15 and the signal transmitted to the clock input is FF15. If the hold time is longer than the hold time, the normal operation is performed.

That is, in the timing chart of FIG. 7, the difference between the rising time of the input signal IN2 and the falling time of the point C TH
Is larger than the Hold time of FF15,
The circuit configuration of FIG. 4 is used.

Next, FIGS. 5 and 6 will be described.

First, the difference in circuit configuration between FIG. 4 and FIGS. 5 and 6 is that a buffer 18 is inserted between the clock (C) inputs of the clock signal IN2 and the FF 16 in FIG. , Q output of FF19 and FF in FIG.
The point is that the buffer 21 is inserted between 20 data inputs.

This is because the time difference between the signals transmitted to the data input and the clock input of FF17 / FF20 is FF17 / FF20.
This is because it is smaller than the Hold time time that each FF 20 has. That is, the buffers 18 and 21 act as a delay circuit, and delay the data input transmission time of the FFs 17 and 20 to hold the hold time.
And the circuit is operating normally.

[0012]

The problems in the above-mentioned conventional technique will be described by taking a gate array as an example.

First, the problems in the circuit configuration of FIG.
Will be explained. In FIG. 8, when designing the circuit, FF2
The time difference between the signal transmitted to the data (D) input of 3 and the signal transmitted to the clock (C) input is held by the FF23.
It is assumed to be larger than time.

Next, when the semiconductor chip 25 is actually placed and wired, the wiring length from the buffer 24 to the clock input of the FF 22 is very short, and the buffer 24 to the FF is short.
When the wiring length up to the clock input of 23 becomes long, the circuit malfunctions (this is called metal skew).

This is because the process speed of the gate array has been miniaturized year by year, and the operating speed of the block itself has increased. On the other hand, the wiring width has become narrower, and the resistance has increased. Buffer 24 to FF rather than signal transmission time to clock input
This is because the signal transmission time up to the clock input of 23 is delayed. Next, two metal skew countermeasure plans will be described.

Countermeasure 1: A delay circuit is inserted between the Q output of the FF22 and the data input of the FF23 or before the clock input of the FF22 so as not to be influenced by the wiring length after the placement and wiring.

Countermeasure 2: Place and route again.

However, there are several problems with this countermeasure.

Problem 1: Regarding the insertion of the delay circuit, it is necessary to insert the delay circuit having the optimum value, not simply inserting the delay circuit. In addition, the design becomes complicated, for example, delay circuits must be inserted in all high-risk areas.

Problem 2: Re-arrangement / wiring: When the re-arrangement / wiring is performed, the arrangement positions of other logic circuits also change, and therefore the normally arranged circuit malfunctions as a result of the last arrangement. There is.

5 and 6, the problem 1 is similarly raised, and the problems 3 and 4 described later are further raised.

Problem 3: If there are many places where there is a high risk of metal skew, more delay circuits will be inserted, and the worst chip size will be changed. In the gate array, the number of blocks used is limited for each chip size.

Problem 4: The maximum operating frequency is lowered by inserting the delay circuit.

An object of the present invention is to provide a flip-flop circuit which solves the above problems, is easy to design, does not malfunction, and operates at high speed without increasing the chip size. ..

[0025]

The structure of the flip-flop of the present invention is characterized by including a data input terminal, an output terminal, a clock input terminal, and a clock output terminal.

[0026]

1 is a circuit diagram showing a flip-flop circuit according to an embodiment of the present invention. 2 is a block diagram showing an example of using the shift register of the flip-flop circuit of FIG. 1, FIG.
FIG. 3 is a timing diagram showing the operation of FIG.

In FIG. 1, the flip-flop circuit 1 of this embodiment comprises transfer gates 2, 4, 6, 8 and
Inverters 3, 5, 7, 9, 10, 11 are provided. The data (D) input is connected to the inverter 3 and the transfer gate 6 via the transfer gate 2, the output of the inverter 3 is connected to the inputs of the transfer gate 4 and the inverter 7, and the output of the inverter becomes the Q output and the inverter. 9 is connected to the input, and the output of the inverter 9 is connected to the input of the inverter 5 via the transfer gate 8. The output of the inverter 9 is Q
(Inverted value) output.

The clock (C) input obtains a C (inverted value) output via the inverter 10, and further obtains a C output via the inverter 11, and the output of the inverter 11 is C.
It becomes 0 output and can be pulled out. C, C (inverted value)
The output is applied to the transfer gates 2, 4, 6, 8.

In FIG. 2, the clock input signal IN2
Is applied to the C input of the D-type flip-flop 13 in the next stage, and the C0 output from the inverters 10 and 11 is applied to the C-input of the D-type flip-flop 12 in the first stage.

3, the data input signal IN1, the clock input signal IN2, the A point which is the C0 output point of the flip-flop 13 in FIG. 2, the B point which is the Q output point of the flip-flop 12, and the Q output of the flip-flop 13 are shown. Each waveform of the output OUT is shown. TH in FIG. 3 indicates a signal transmission time difference between the clock input, the data input and the data input.

As shown in FIG. 2, by connecting the C0 output of the flip-flop (FF) 13 to the clock input of the previous FF 12, the FF 13 always operates first, and then the FF 12 operates. This makes it possible to solve all of the above-mentioned problems such as metal skew, complicated design, and insertion of a delay circuit.

As described above, according to this embodiment, regarding the basic function block of the FF circuit, in particular, the FF circuit in which the gate array or the like which is automatically arranged and wired is used,
The present invention is characterized by providing a clock output terminal that can output the signal input to the clock input terminal to the outside of the FF circuit as well as supplying it to the inside of the FF circuit.

[0033]

As described above, the present invention has the following effects by providing the external terminal so that the output of the signal input to the clock of the FF circuit can be output to the outside of the FF circuit. ..

Malfunction due to metal skew is eliminated.

It is not necessary to take measures against malfunction due to metal skew at the time of design or after placement / wiring.

Since there is no need to insert a delay circuit, there is an increased possibility that the performance of the circuit will be improved or the chip size will be reduced to reduce the cost.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a flip-flop circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a shift register including the flip-flop circuit shown in FIG.

FIG. 3 is a timing diagram illustrating the operation of FIG.

FIG. 4 is a block diagram showing a first example of a conventional shift register.

FIG. 5 is a block diagram showing a second example of a conventional shift register.

FIG. 6 is a block diagram showing a third example of a conventional shift register.

FIG. 7 is a timing diagram showing the operation of FIGS. 4, 5 and 6.

8 is an arrangement diagram showing an example in which the circuit of FIG. 4 is arranged on a semiconductor chip.

[Explanation of symbols]

1, 12, 13, 14, 15, 16, 17, 19, 20
D-type flip-flop 2, 4, 6, 8 Transfer gate 18, 21, 24 Buffer IN1 Data input signal IN2 Clock input signal 25 Semiconductor chip

Claims (2)

[Claims] 1. A flip-flop circuit comprising a data input terminal, an output terminal, a clock input terminal, and a clock output terminal. 2. The flip-flop circuit according to claim 1, wherein two inverters are interposed between the clock input terminal and the clock output terminal.