JP2003256361A - Data transmission mechanism between lsi - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data transmission mechanism between LSIs, which is capable of reducing an effect of change in an operating environment in data transmission between the LSIs without arranging a dedicated circuit inside or outside of an LSI, and avoiding occurrence of a setup error and hold error. <P>SOLUTION: In the LSI1 of data transmission side, a source clock CLK102 before being distributed in a clock tree is directly supplied to a final flip flop 107 for passing data to an output driver 108. In the LSI2 of data receiving side, a source clock CLK201 before being distributed in the clock tree is directly supplied to an initial flip flop 207 for receiving data from an input driver 206. Consequently, a delay of the clock supplied to the flip flop 107 and 207 to a system clock SYSCLK 1 is made small. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention includes a plurality of LSI mounted on the wiring board (L arge S cale I nte
In a system in which the same system clock is supplied to each of the LSIs and data is mutually transmitted between the LSIs, the influence of changes in the operating environment such as the operating temperature on the data transmission is reduced, and the data is reliably transferred between the LSIs. The present invention relates to a data transmission mechanism between LSIs capable of performing.

[0002]

2. Description of the Related Art A plurality of Ls mounted on a wiring board will be described below.
Conventional data transmission in a system in which the same system clock is supplied to SI and data is mutually transmitted between LSIs will be described with reference to the drawings. As shown in FIG. 3, the LSI 3 and the LSI 4 have the same system clock S
YSCLK2 is supplied. Inside each LSI, the system clock SYSCLK2 is divided a plurality of times by a clock tree so that data is normally transmitted between the internal logic circuits, and the system clock SYSCLK2 is distributed and supplied to each internal logic circuit.

FIG. 4 shows an example of a timing chart when data is transmitted from the LSI 3 to the LSI 4. In FIG. 4, t1 is a delay value of the clock CLK307 distributed and supplied to the final flip-flop 305 that transfers the data 308 to the output driver (data output cell) 306 which is an input / output cell of the LSI3 with respect to the system clock SYSCLK2, and , T3 are system clocks S of the clock CLK 408 distributed and supplied to the first flip-flop 404 which receives the data 407 from the input driver (data input cell) 403 which is the input / output cell of the LSI 4.
It is a delay value for YSCLK2. Also, t2 is L
It is a delay value of data transmission between LSIs by the additional capacitance 600 obtained by summing the additional wiring capacitance of the data transfer wiring 500 between the SI 3 and the LSI 4, the additional output capacitance of the output driver 306, etc., and the placement and wiring of the LSI on the board is determined. It is a value determined by doing. Here, it is assumed that the operation speed of the LSI 3 is slower than the operation speed of the LSI 4 (t1>
t3).

As shown in FIG. 4, an LSI on the data transmission side
The data output from 3 is the system clock SYSCL
K2 is delayed by a delay value t1, and a delay due to the additional capacitance 600 (delay value t2) is added to this delay, and the system clock SYSCLK2 is supplied to the LSI 4 on the data receiving side.
Then, the data is transmitted with a delay value (t1 + t2).

The clock C supplied to the final flip-flop 306 which passes the data 308 to the output driver 306.
The delay value t1 of the LK307 with respect to the system clock SYSCLK2 and the delay value t3 of the clock CLK408 supplied to the first flip-flop 404 that receives the data 407 from the input driver 403 with respect to the system clock SYSCLK2 are circuit-dependent values, unlike t2.
It fluctuates due to changes in operating environment (operating temperature, power supply voltage). Above all, there is a large fluctuation range for changes in operating temperature,
In some cases, a setup error or a hold error may occur, normal data transmission between LSIs may not be possible, and the system may malfunction. In particular, in recent years, the frequency of the system clock has increased due to the demand for high-speed data transmission, and there is a high possibility that setup errors and hold errors will occur.

As shown in FIG. 4, in this conventional example, an LSI is used.
3 is slower than the LSI 4 operating speed (t
1> t3), a setup error may occur. Therefore, in FIG. 5, the delay value t1 due to a change in the operating environment,
7 shows a timing chart when a setup error occurs in data transmission between LSI3 and LSI4 due to a change in t3. When the operating temperature changes, the delay value t1,
Although t3 varies, the delay value t1 has a larger absolute value than the delay value t3, and therefore the variation value due to the temperature change also becomes larger than the delay value t3. As a result, as shown in FIG. 5, the setup time of the data 407 is insufficient, the output timing of the flip-flop 404 is deviated, and normal data transmission cannot be performed.

As described above, the fluctuation of the delay value due to the change of the operating environment (operating temperature, power supply voltage) of the clock supplied to each logic circuit in the LSI is, as described above, that is, the system speed increases. It becomes more remarkable as the frequency of the clock increases. Therefore, there are the following conventional techniques for stably performing high-speed data transmission between LSIs.

First, in order to suppress the clock skew between the LSIs, the clock system of the LSI on the data receiving side has P
A technique is known in which an LL (phase locked loop) is provided and the internal clock of the LSI on the data receiving side is forcibly synchronized with the transmission clock of the received data.

Second, in Japanese Patent Laid-Open No. 6-110575, a hold error in data transmission between LSIs caused by manufacturing variations of LSIs and fluctuations in operating environment (operating temperature, power supply voltage) is eliminated. Therefore, there is described a mechanism in which a delay measuring circuit provided inside or outside the LSI measures a delay time of a clock between the LSIs and delays the data to an optimum value by a delay variable device.

Third, in Japanese Unexamined Patent Publication No. 8-249275, data transmission between LSIs is performed by synchronous transmission of 1.5 clock latency, so that a hold time in data transmission between LSIs is guaranteed and a system clock is ensured. A mechanism for increasing the data transmission rate between LSIs up to 1.5 times the upper limit of the frequency is described.

However, conventionally, in order to perform stable data transmission between LSIs without being affected by variations in LSI manufacturing and changes in operating environment (operating temperature, power supply voltage), as described above, Since a dedicated circuit has to be provided inside or outside the LSI, and the configuration becomes complicated, there is a problem that the burden on the designer increases. Further, if the LSI designer and the base designer are different, the LSI designer must consider which LSIs are connected to each other on the board, and the base designer is
There is a problem in that the number of design steps is increased because it is necessary to grasp the SI circuit configuration.

[0012]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides a final flip-flop that transfers data to a data output cell in a data transmission side LSI, with a source clock before being distributed in a clock tree. In the LSI on the data receiving side, the source clock before being distributed in the clock tree is directly supplied to the first flip-flop which receives the data from the data input cell, and the final flip-flop of the LSI on the data transmitting side is directly supplied. The delay of the clock supplied to the system clock with respect to the system clock and the delay of the clock supplied to the first flip-flop of the LSI on the data reception side with respect to the system clock are minimized together, so that the delay is dedicated to the inside or outside of the LSI. Operation in data transmission between LSIs without providing circuits And to provide a data transmission mechanism between an LSI to reduce the influence of the boundary change can avoid occurrence of the setup error or hold error. With such a configuration, it is not necessary to provide a dedicated circuit inside or outside the LSI, so that the burden on the designer of the LSI can be reduced as compared with the conventional case. Further, even when the designer of the base and the designer of the LSI are different, the designer of the LSI can design without considering the positional relationship of the connected LSIs, and the designer of the base can design the circuit configuration of the LSI. It is not necessary to grasp and the design man-hour can be reduced compared to the conventional case.

Further, as described above, the LS on the data transmitting side is
In I, when the source clock is directly supplied to the final flip-flop, the delay value of the clock supplied to the final flip-flop with respect to the system clock becomes small, whereas the data received by the final flip-flop is reduced. Since the clock supplied to the preceding flip-flop for output is divided a plurality of times in the clock tree, the delay value of this clock with respect to the system clock is larger than the delay value of the final flip-flop. Therefore, for example, if a logic circuit exists between the final flip-flop and the previous flip-flop and a delay occurs in data transmission, a setup error may occur in data transmission during this period.

Therefore, in the LSI on the data transmission side,
By directly wiring between the final flip-flop and the preceding flip-flop, the delay in data transmission between the final flip-flop and the preceding flip-flop is minimized to avoid the occurrence of a setup error, and to be sure Provided is a data transmission mechanism between LSIs capable of passing data.

As described above, the LS on the data receiving side
In I, when the source clock is directly supplied to the first flip-flop, the delay value of the clock supplied to the first flip-flop with respect to the system clock becomes small, while the output data from the first flip-flop is reduced. Since the clock supplied to the flip-flop of the next stage receiving the clock is divided a plurality of times in the clock tree, the delay value of this clock with respect to the system clock is larger than the delay value of the first flip-flop. Therefore, when the delay of the clock supplied to the next-stage flip-flop with respect to the system clock becomes large due to, for example, a change in operating temperature, the data transmission between the first flip-flop and the next-stage flip-flop is held. An error may occur.

Therefore, in the LSI on the data receiving side,
By inserting a flip-flop supplied with a clock obtained by inverting the source clock between the first flip-flop and the next-stage flip-flop and delaying the data received by the next-stage flip-flop, the clock delay Is provided, a hold error does not occur, and a data transmission mechanism between LSIs is provided in which data can be reliably transferred between the first flip-flop and the next-stage flip-flop.

Further, if a logic circuit is present between the first flip-flop and the flip-flop to which the clock obtained by inverting the source clock is present and a delay occurs in the data transmission, in the data transmission during this period. A setup error may occur.

Therefore, in the LSI on the data receiving side,
By directly wiring between the first flip-flop and the flip-flop supplied with the clock obtained by inverting the source clock, between the first flip-flop and the flip-flop supplied with the clock obtained by inverting the source clock. (EN) Provided is a data transmission mechanism between LSIs which minimizes the data transmission delay to avoid the occurrence of a setup error and can reliably transfer data.

[0019]

According to the data transmission mechanism between LSIs according to claim 1 of the present invention, the same system clock is supplied to a plurality of LSIs mounted on a wiring board, and the LSIs mutually communicate with each other. In a system that performs data transmission, the last flip-flop that passes data to the data output cell of the LSI on the data transmission side has the L on the data transmission side.
Before being distributed by the clock tree of the data receiving side LSI, the first flip-flop that directly supplies the source clock before being distributed by the SI clock tree and receives data from the data input cell of the data receiving side LSI The feature is that the source clock is directly supplied.

With this configuration, the delay of the clock supplied to the final flip-flop with respect to the system clock and the delay of the clock supplied to the first flip-flop with respect to the system clock can be reduced, and the internal of the LSI can be reduced. Alternatively, it is possible to avoid the occurrence of setup errors and hold errors by reducing the influence of changes in the operating environment in data transmission between LSIs without providing an external dedicated circuit. In addition, since it is not necessary to provide a dedicated circuit inside or outside the LSI, the burden on the designer of the LSI is reduced as compared with the conventional one, and even if the designer of the base and the designer of the LSI are different, the designer of the LSI It is possible to design without considering the positional relationship of the LSI to be connected, and it is not necessary for the designer of the board to grasp the circuit configuration of the LSI, and the number of design steps can be reduced as compared with the conventional case.

A data transmission mechanism between LSIs according to claim 2 of the present invention is the data transmission mechanism between LSIs according to claim 1, wherein the LS on the data transmitting side is
In I, the data transfer line between the final flip-flop and the preceding flip-flop for outputting the data received by the final flip-flop is directly wired to directly transmit the data.

In this way, it is possible to avoid the occurrence of a setup error between the final flip-flop and the preceding flip-flop and reliably transfer the data.

A data transmission mechanism between LSIs according to claim 3 of the present invention is the data transmission mechanism between LSIs according to claim 1 or 2.
In the LSI on the data receiving side, the source clock of the LSI on the data receiving side is inverted and supplied between the first flip-flop and the next-stage flip-flop receiving the output data from the first flip-flop. It is characterized in that a flip-flop is inserted.

With this configuration, even if the delay of the clock supplied to the flip-flop of the next stage is maximum and is delayed by a half cycle of the system clock, the flip-flop supplied with the source clock inverted and the next flip-flop. It is possible to reliably transfer data by avoiding the occurrence of a hold error between the flip-flops of the stages.

A data transmission mechanism between LSIs according to claim 4 of the present invention is the data transmission mechanism between LSIs according to claim 3, wherein the LS on the data receiving side is
In I, the data transfer line between the first flip-flop and the flip-flop to which the source clock is inverted and supplied is directly wired so that data is directly transmitted.

With this configuration, it is possible to avoid the occurrence of a setup error between the first flip-flop and the flip-flop to which the clock obtained by inverting the source clock is supplied and to reliably transfer the data. .

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION The LS of the embodiment of the present invention will be described below.
The data transmission mechanism between I will be described with reference to the drawings. FIG. 1 is a schematic diagram of a data / clock system in this embodiment. As shown in FIG. 1, LSI1, LSI
2 is supplied with the system clock SYSCLK1.
Also, the system clock SYSC supplied to the LSI 1
LK1 is divided into source clocks CLK101 and CLK102 by the non-inverting clock driver 100,
The system clock SYSCLK1 supplied to I2 is the source clock C by the non-inverting clock driver 200.
It is divided into LK201, CLK202, and CLK203.

The source clock CLK101 divided by the non-inverting clock driver 100 is further divided several times via a plurality of non-inverting clock drivers and distributed and supplied to the flip-flops 104 and 106 which are internal logic circuits. Further, the source clock CLK102 is directly supplied to the flip-flop 107.

The source clock CLK 201 divided by the non-inverting clock driver 200 is directly supplied to the flip-flop 207. Source clock C
The LK 202 is connected to the inverting clock driver 205, and the clock CLK 212 which is the output of the inverting clock driver 205 is supplied to the flip-flop 208 as it is. Further, the source clock CLK203 is further divided several times via a plurality of non-inverting clock drivers, and flip-flops 209 and 21 which are internal logic circuits.
1 and the like are distributed and supplied.

Next, the data flow will be described.
First, the data output from the flip-flop 104 of the LSI 1 passes through the logic block 105 including a logic circuit and a combination circuit, and finally is input to the flip-flop 106. The data 110, which is the data output of the flip-flop 106, is directly input to the flip-flop 107. The data 111 that is the data output of the flip-flop 107 is input to the output driver (data output cell) 108 that is an input / output cell. The output of the output driver 108 is input to the input driver (data input cell) 206 which is an input / output cell of the LSI 2 via the wiring 500.

The data 214, which is the data output of the input driver 206, is directly input to the flip-flop 207. The data 215, which is the data output of the flip-flop 207, is directly input to the flip-flop 208. The data 216, which is the data output of the flip-flop 208, is directly input to the flip-flop 209.
Entered in. The output of the flip-flop 209 passes through the logic block 210 including a logic circuit and a combination circuit, and is finally input to the flip-flop 211.

As described in the conventional example, the LSI 1 and the LSI
Wiring additional capacitance of the wiring 500 between the two and the output driver 108
The additional capacitance 600, which is the sum of the output additional capacitances, is a value determined by determining the layout and wiring of the LSI on the substrate.
That is, this delay value is a value that does not depend on the circuit mechanism inside the LSI. Therefore, in order to perform stable data transmission between the LSIs, the source clock C obtained by dividing the system clock SYSCLK1 into the final flip-flop 107 that transfers data to the output driver 108 and the first flip-flop 404 that receives data from the input driver 206.
The LK 102 and 201 are supplied to the flip-flop 107.
By minimizing the delay value of the clock supplied to the flip-flop 404 with respect to the system clock, a data transmission mechanism between LSIs that is not easily affected by changes in the operating environment (particularly changes in operating temperature) is constructed.

FIG. 2 shows the LSI 1 and L in the present embodiment.
As an example of a timing chart of data transmission between SI2, an example in which data is transmitted from LSI1 to LSI2 is shown. As shown in FIG. 2, the flip-flop 1 at the previous stage that transfers data to the final flip-flop 107
The clock CLK109 supplied to 06 is obtained by dividing the source clock CLK101 into a plurality of parts, and the clock rises after a delay of t01 with respect to the system clock SYSCLK1. On the other hand, the source clock CLK obtained by dividing the system clock SYSCLK1
102 is t0 with respect to the system clock SYSCLK1
A delay of 2 occurs.

Since the wiring until the clock CLK109 is divided many times is longer than the wiring for the source clock CLK102, the relation between them is always t01> t02.
Becomes Therefore, for example, if a logic circuit exists between the flip-flop 106 and the flip-flop 107 and a delay due to the logic circuit is added, a setup error may occur.

Therefore, in the data transmission mechanism between LSIs according to the present embodiment, the wiring between the flip-flop 106 and the flip-flop 107 is directly wired so that the data delay between the flip-flop 106 and the flip-flop 107 can be minimized. Of the flip-flop 106 and the flip-flop 1
Ensure the data transfer between 07.

Further, the source clock CLK of the final flip-flop 107 for passing data to the output driver 108.
102 and the source clock C of the first flip-flop 207 that receives data from the input driver 206
Since the LK201 is obtained by dividing the system clock SYSCLK1, the absolute values of the delay values t02 and t04 are small. Therefore, the fluctuation range of the delay values t02 and t04 due to the change of the operating environment, especially the change of the operating temperature is small,
Data transmission between LSIs can be made less susceptible to changes in operating environment.

Further, t03 is a delay value of the data signal transmitted between the LSIs by the additional capacitance 600, which is the sum of the additional wiring capacitance of the wiring 500 between the LSI1 and the LSI2, the additional output capacitance of the output driver 108, and the like. It is a value that is determined when the layout and wiring of the LSI are determined, and is a value that does not depend on the circuit mechanism inside the LSI.

The system clock SYSCLK1 of the clock CLK213, which is supplied to the flip-flop (next stage flip-flop) 209 after being divided into a plurality of pieces.
Is larger than the divided source clock CLK201 of the system clock SYSCLK1.
Therefore, if the flip-flop 207 and the flip-flop 209 are directly wired, a hold error may occur when the delay of the clock CLK213 with respect to the source clock CLK201 increases due to a change in operating temperature, for example. Therefore, the source clock CLK2
By inserting the flip-flop 208 supplied with the clock CLK212, which is the inverted 02 cycle, between the flip-flop 207 and the flip-flop 209, the flip-flop 208 receives the data with a delay value t05 behind the source clock CLK201 and receives the data. 209, the clock CLK213 supplied to the flip-flop 209 is the system clock SY.
A hold error can be avoided even if delayed by a half cycle of SCLK1, and data can be reliably transferred.

If, for example, a logic circuit exists between the flip-flop 207 and the flip-flop 208 to cause a delay in data transmission, a setup error may occur in the data transmission during this period.

Therefore, by directly connecting the flip-flop 207 and the flip-flop 208, the delay of the data transmission between the flip-flop 207 and the flip-flop 208 is minimized to avoid the occurrence of a setup error and to reliably transfer the data. Will be able to.

Further, a logic circuit can be inserted between the flip-flop 208 and the flip-flop 209.
When the logic circuit is inserted, the data transmission between the flip-flop 208 and the flip-flop 209 is further delayed. Therefore, it is possible to cope with the delay value of the clock CLK213 being equal to or more than the half cycle of the system clock SYSCLK1.

[0042]

As described above, according to the data transmission mechanism between LSIs according to claim 1 of the present invention, the operating environment in the data transmission between LSIs can be realized without providing a dedicated circuit inside or outside the LSIs. It is possible to reduce the influence of changes and avoid the occurrence of setup errors and hold errors. Also, because it is not necessary to provide a dedicated circuit inside or outside the LSI, the burden on the designer of the LSI is reduced compared to the past. Therefore, even if the base designer and the LSI designer are different, the LSI designer is connected to the LSI
It is possible to design without taking into consideration the positional relationship of the above, and it is not necessary for the designer of the base board to grasp the circuit configuration of the LSI, and the number of design steps can be reduced as compared with the conventional case.

According to the data transmission mechanism between LSIs according to claim 2 of the present invention, the LSI on the data transmission side is
In the data transmission between the flip-flop that passes the data to the data output cell and the flip-flop that outputs the data received by the flip-flop, it becomes possible to avoid the occurrence of a setup error and reliably deliver the data. The effect of the data transmission mechanism between LSIs according to the first aspect can be made more reliable.

Further, according to the data transmission mechanism between LSIs according to the third aspect of the present invention, the delay of the clock supplied to the flip-flops after the flip-flop to which the clock obtained by inverting the source clock is supplied is maximum, and the system is maximized. Even if the clock is delayed by half a cycle, in the data transmission between the flip-flop to which the clock that is the source clock is inverted and the next flip-flop of this flip-flop, the hold error is avoided and the data can be reliably delivered. As a result, the effect of the data transmission mechanism between the LSIs described in claim 1 can be made more reliable.

According to the data transmission mechanism between LSIs according to claim 4 of the present invention, the LSI on the data receiving side is
In the data transmission between the flip-flop receiving the data from the data input cell and the flip-flop supplied with the clock obtained by inverting the source clock, it becomes possible to avoid the occurrence of the setup error and reliably deliver the data, The effect of the data transmission mechanism between LSIs described in claim 1 can be made more reliable.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a data / clock system according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a timing chart of data transmission between LSIs according to the embodiment of the present invention.

FIG. 3 is a schematic diagram of a conventional data / clock system.

FIG. 4 is a diagram showing an example of a timing chart of data transmission between conventional LSIs.

FIG. 5 is a diagram showing an example of a timing chart when a setup error occurs in data transmission between conventional LSIs.

[Explanation of symbols]

100, 103, 200, 204, 300, 400
Non-inverting driver 104, 106, 107, 207 to 209, 211, 3
03, 305, 404, 406 Flip-flop 105, 210, 304, 405 Logic block 108, 306 Output driver 205 Inversion type driver 206, 403 Input driver 500 Wiring between LSIs 600 Additional capacitance

Claims (4)

[Claims] 1. In a system in which the same system clock is supplied to a plurality of LSIs mounted on a wiring board and data is mutually transmitted between the LSIs, an L on the data transmission side is provided.
The first flip-flop that transfers data to the data output cell of the SI is directly supplied with the source clock before being distributed in the clock tree of the LSI on the data transmitting side, and the data is first received from the data input cell of the LSI on the data receiving side. The data transmission mechanism between LSIs, wherein the source clock before being distributed by the clock tree of the LSI on the data receiving side is directly supplied to the flip-flop of FIG. 2. In the data transmission side LSI, data is directly transmitted by directly wiring a data transfer line between the final flip-flop and a preceding flip-flop that outputs data received by the final flip-flop. The data transmission mechanism between LSIs according to claim 1, characterized in that. 3. The L according to claim 1 or 2.
A data transmission mechanism between SIs, wherein in the LSI on the data receiving side, between the first flip-flop and the next-stage flip-flop receiving the output data from the first flip-flop, A data transmission mechanism between LSIs, characterized by inserting a flip-flop to which an LSI source clock is inverted and supplied. 4. In the LSI on the data receiving side, a data transfer line between the first flip-flop and the flip-flop to which the source clock is inverted and supplied is directly wired so that data is directly transmitted. 4. A data transmission mechanism between LSIs according to claim 3.