JPS6235197B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal transmission system for semiconductor integrated circuits, and more particularly to a signal transmission system that can reliably perform in-phase transfer within an integrated circuit.

2. Description of the Related Art Data processing devices such as digital computers use a method of synchronizing the operation of logic circuits with timing signals in order to simplify design and adjustment. Now, using the timing signal T0 shown in FIG. 1b as a reference, the signal repetition time (machine cycle) T _c (seconds) is divided into n equal parts, and a different timing signal T1, T2, T3
is often provided and operated as an n-phase clock. Here, n (integer) is called the phase number.

FIG. 1a is a diagram showing a conventional logic circuit when the number of phases is four, and FIG. 1b is a timing chart thereof.

In FIG. 1a, latches 1, 2, 3, and 4 are latches housed in different integrated circuits, respectively, and have timings T0, T1, T2, and T3, respectively.
operates in sync with OR gate 10 and NAND gates 11, 12, 15 are circuits provided between each latch to perform logic operations, respectively.
This is a circuit that inverts the input to the

The signal A applied to the D input terminal of latch 1 is
It is captured into latch 1 at timing T0. The output of latch 1 is applied to the D input terminal of latch 2 via gates 11 and 12. Latch 2
The signal applied to the D input terminal of
1 into latch 2. On the other hand, the signal applied to the D input terminal of latch 4 is
External signals C and D have passed through the gate 15 and are taken into the latch 4 at timing T2.
Next, the outputs of latch 2 and latch 4 are gate 1
3 and 14 to the D input terminal of latch 3, and is taken into latch 3 at timing T3. Furthermore, the output of latch 3 is applied to the D input terminal of latch 1 via OR gate 10. Hereafter, in the same way, timing T0,
T1, T2, and T3 sequentially operate latches 1 to 4 to perform a logic operation.

By the way, since signal transmission between each latch goes through printed wiring boards, coaxial lines, gates, etc., it naturally takes time for the signal to be transmitted. If the inter-latch transmission time is less than or equal to the timing interval of the latches, the signal sent from the source latch will be in time with the timing of the receiving latch and will be received by the receiving latch in a normal state. That is, the first
In the case of FIG. b, the timing interval is T _c /4, so if the transmission time between each latch is less than T _c /4, each latch will normally capture the data.

On the other hand, if the inter-latch transmission time is longer than the timing interval of each latch, the signal from the transmitting latch will not be transmitted to the D input terminal of the receiving latch when the timing of the receiving latch operates. The receiving latch cannot receive normal data.

On the other hand, in the case where each of the latches 1 to 4 in FIG. 1 are housed in one integrated circuit, the transmission time between the latches is so small that it can be ignored, so there is no problem with the signal transmission time. It should work properly. In this case, it is only necessary to consider the maximum value of the inter-latch transmission time at the time of design. That is, T0~
Between T1, between T0 and T2, between T0 and T3, between T1 and T
2, between T1 and T3, between T1 and T0, between T2 and T3
between, between T2 and T0, between T2 and T1, between T3 and T0
For signal transmission between different timings, such as between latches, between T3 and T1, and between T3 and T2, it is sufficient that the maximum signal transmission time between each latch is equal to or less than a predetermined value.

On the other hand, as each timing interval becomes narrower,
Two phases are more desirable than four phases, and since only one phase is more desirable in terms of performance than two phases, in-phase transfer is often used. Between T0 and T0, T1 and T
In the case of in-phase transfer such as between T1 and T2, between T3 and T3, etc., the latch output on the signal source side is transferred to the receiving side latch within the valid time (within the pulse width) of the timing signal of the receiving side latch. If the signal reaches the D input terminal, the receiving latch does not capture the signal at the D input terminal at the same timing as the signal source latch, instead of taking the signal into the receiving latch at the originally expected timing one cycle later. This causes the inconvenience of incorporating the .

FIGS. 2a and 2b are a logic circuit diagram and a time chart showing the operation of conventional in-phase transfer.

Signal source side latch 2 housed in the same integrated circuit
1 and receiver latch 22, respectively, as shown in FIG. 2b.
Timings 201, T0 (A) and 202, T0 shown in
(B) works. Gates 31, 32, and 33 are for transmitting signals from latch 21 to latch 22, and input signals from other signal sources are omitted. Also, 34 is the latch 21, 2
This is an amplifier for supplying a timing signal T0 to the second circuit. The outputs of this amplifier 34 are 201, 202
One of the signals 201 has the signal name T0(A) and is supplied to the latch 21, and the other signal 202 has the signal name T0(B) and is supplied to the latch 22.

As shown in FIG. 2b, there is a feeding error (commonly referred to as timing or skew) ΔT in the signals 201 and 202. Signal source side latch 2
If the timing 201 of the signal source latch 22 is in the advanced phase and the timing 202 of the receiving latch 22 is in the delayed phase, the receiving latch may malfunction to take in the signal at the same timing as the signal source latch, as described above. easy.

The relationship between 203, 204, and 205 shown in FIG. 2b indicates such a malfunction.

Because the transmission times of gates 31, 32, and 33 are small, there is almost no delay between the output signal 203 of latch 21 and the output signal 204 of gate 33, and the output signal 204 of gate 33 is delayed by the timing of latch 22. It reaches the D input terminal of latch 22 within the existing time. Therefore, latch 22 provides an output waveform such as signal 205, but the originally expected waveform is a waveform that rises at the time of signal 205'. After all, in order to successfully perform such in-phase transfer, it is necessary to design the system to satisfy the conditions shown in the following equation.

t _Dnio > T _Wnax + △T _nax ...(1) Here, t _Dnio is the minimum transmission time between latch 21 and latch 22, T _Wnax is the maximum value of the timing pulse width, and △T _nax is the timing・This is the maximum value of skew.

In other words, equation (1) above requires that the minimum transmission time t _Dnio required to guarantee normal operation be greater than or equal to the algebraic sum of the maximum timing pulse width T _Wnax and the maximum timing skew value ΔT _nax . Indicates that it must be the transmission time. Also, it goes without saying that the maximum transmission time between latch 21 and latch 22 must be less than or equal to the machine cycle _Tc . Ultimately, the transmission time t _d between latches 21 and 22 must satisfy the following equation.

T _c > t _d > T _Wnax + △T _nax ...(2) Timing skew △T _nax can be brought close to 0 by finely adjusting the transmission time of the timing power supply system, but the timing pulse The width T _Wnax cannot exceed a certain level in order to guarantee the operation of the latch (for example, an ECL type latch requires a pulse width of 4 to 5 nS or more), and when pulse width variations are included, the width is quite large. This value becomes a large value, and it is necessary to guarantee this value as the transmission time between latches 21 and 22.

Modern digital computers employ methods such as pipeline control and shortening of machine cycles in order to operate at high speeds. As machine cycles become shorter, the number of timing phases is becoming two even though the division of one machine cycle is reduced. This reduction in the number of timing phases has the disadvantage of significantly increasing in-phase transfer and increasing the number of nets (paths) that must guarantee a minimum transmission time between latches during design, resulting in a significant increase in design effort. be. Furthermore, in recent years,
As the degree of integration of semiconductors increases, it becomes necessary to incorporate common-mode transfer logic inside semiconductor chips, and in this case, gates are used as delay elements to guarantee a minimum transmission time between latches. is used. However, if a gate as a delay element is incorporated on a semiconductor chip in addition to a gate for logic, there is a drawback that the chip area increases and power consumption increases.

The purpose of the present invention is to eliminate these conventional drawbacks by easily realizing in-phase transfer on a highly integrated semiconductor chip, and by eliminating the need to set a minimum transmission time between latches that perform in-phase transfer. An object of the present invention is to provide a signal transmission method for semiconductor integrated circuits that can eliminate the limitations of the above.

In order to achieve the above object, a signal transmission system for a semiconductor integrated circuit according to the present invention includes a logic operation element and first, second and third latch groups that temporarily store logic signals operated by the logic operation element. , has an inverter circuit that outputs the same timing pulse as it is and at the same time inverts and outputs the pulse, and has an inverter circuit that outputs the same timing pulse as it is, and at least one of the first and second latch groups or between the second and third latch groups. , inserting the logic operation element, supplying the same timing output of the inverter circuit to the first and third groups of latches, and supplying the inverted timing output of the inverter circuit to the second group of latches, A feature is that same-time transfer is performed between the first and third latch groups.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.

FIG. 3a shows a part of a logic circuit constructed on a semiconductor chip, and FIG. 3b is an operation time chart of the logic circuit shown in FIG. 3a. The first latch 41 has a timing 101,T
The third latch 43 is a receiving latch that operates at the same timing 101 and T0 as above, and the second latch 43 operates at the same timing 101 and T0 as above.
2 is timing 10 which is opposite to the above timing.
It is an intermediate latch operating at 2,0. An amplifier 44 is connected to the input terminal 52 at timing T0, and in response to timing T0, outputs 101,
Generate T0 and 102,0. Note that the output 106 of the third latch 43 is connected from the data output terminal 53 to the outside of the chip or to the next latch within the chip.

In FIG. 3a, the signal 103 applied to the data input terminal 51 becomes "1" at time t ₀₀ and remains "1" until time t ₅₀ , as shown in FIG. 3 b _. After that, it becomes "0". This signal 10
3 is taken into the latch 41 in synchronization with timing 101 when it becomes "1" at time _t10 . The output 104 of latch 41 becomes "1" at time _t11 , delayed by the characteristic transmission time of latch 41. At time _t11 , the timing 102 input to the intermediate latch 42 becomes "0", so the latch 42 becomes inactive, that is, it does not accept data input, and the output 105 of the intermediate latch 42 changes at time _t11. do not. At time _t20 , the timing signal 101 becomes "0", and the timing signal 102 becomes "0".
becomes “1”. At this point, latch 41 has set the time
The state of the signal 103 applied to the data input terminal of the latch 41 between _t10 and _t20 is held, and the output is not changed until the next timing _t60 to _t70 . Intermediate latch 42 receives timing signal 1 at time _t20 .
02 becomes "1", the signal 104 applied to the data input terminal D is taken in. intermediate latch 42
The output 105 becomes "1" at time _t21 , delayed by the characteristic transmission time of the intermediate latch 42. At time _t21 , the timing signal of the latch 43 is "0", so the signal 105 applied to the data input terminal D cannot be taken in at this time, and the output 106 of the latch 43 does not change. Time t ₃₀ ,
At _t40 , since there is no change in the state of the signal, each latch 41, 42, 43 does not change. At time _t50 , the input signal 103 changes from "1" to "0", but the timing signal of the latch 41 changes to "0".
Therefore, the state of latch 41 does not change. time
At _t60 , the timing signals 101 and 102 change from "0" to "1" and from "1" to "0", so the states of latches 41 and 43 change, and the characteristic transmission time of each latch 41, 43 changes. time delayed by
At _t61 , the output 104 of latch 41 changes from "1" to "0" and the output 106 of latch 43 changes from "0" to "1".

At time _t60 , the timing signal 102 of intermediate latch 42 changes from "1" to "0", so the state of latch 42 does not change from time _t60 to time _t70 .
The previous state is retained. At time _t70 , when the timing signal 102 changes from "0" to "1", the intermediate latch 42 takes in the state of the signal 104 applied to the data input terminal D and changes to "0", but the output of the latch 42 105 changes to "0" at time _t71 with a delay of the characteristic transmission time of latch 42, as described above.

In this way, the signal 103 applied to the input terminal 51 appears at the output terminal 53 one timing later, and the desired operation is performed. Note that even if the pulse width of the timing signal T0 applied to the input terminal 52 changes, the timing signals 101 and 10
2 are in a complementary relationship, so the timing state changes always occur at the same time, and stable operation that does not exist in the pulse width of the timing signal can be ensured. Furthermore, timing 1 on the semiconductor chip
01, 102, timing 101
The timing skew between and 102 is very small and can be ignored, ensuring stable operation.

In FIG. 3a, the logic gates between the first latch 41 and the intermediate latch 42 and between the intermediate latch 42 and the third latch 43 are omitted for the sake of simplicity; , 43, it is of course possible to insert a logic gate between them. When a logic gate is inserted, it is necessary to place the intermediate latch at a position such that the number of other intermediate latch groups that perform the same operation as intermediate latch 42 is minimized, but this has not been known in the art. This can be easily achieved using the following method.

As explained above, according to the present invention, an intermediate latch is installed between the in-phase transfer latches, and a timing signal that is complementary to the timing signal supplied to the in-phase transfer latch is supplied to the intermediate latch. The in-phase transfer logic can be constructed on a semiconductor chip without considering the minimum transmission time of the latch, and the in-phase transfer can be performed stably even if the pulse width of the timing signal supplied to the latch group changes.

[Brief explanation of the drawing]

Figure 1 is a logic circuit diagram and its time chart showing a conventional signal transmission method using multiphase transfer. Figure 2 is a logic circuit diagram and its time chart showing a conventional signal transmission method using in-phase transfer. 1 is a logic circuit diagram of a signal transmission system using in-phase transfer showing an embodiment of the present invention and a time chart thereof. 1, 2, 3, 21, 22, 41, 42, 43:
Latch, 34, 44: Amplifier, 101, 102,
201, 202: timing signal, 10 to 15,
31-33: Logic gates.

Claims (1)

[Claims] 1. A logic operation element group that connects a plurality of logic operation elements in multiple stages to perform a desired logical operation, and a first and second logic operation element group that temporarily stores the logic signals operated by the logic operation element group. and a third latch group, and an inverter circuit that outputs the same timing pulse as it is and at the same time inverts and outputs the same timing pulse, and has an inverter circuit that outputs the same timing pulse as it is, and between the first and second latch groups or between the second and third latch groups.
The logical operation element group is inserted into at least one of the latch groups, and the same timing output of the inverter circuit is supplied to the first and third latch groups, and the inverted timing output of the inverter circuit is supplied to the first and third latch groups. 1. A signal transmission system for a semiconductor integrated circuit, characterized in that the signal is supplied to two groups of latches, and in-phase transfer is performed between the first and third groups of latches. 2. A signal transmission system for a semiconductor integrated circuit according to claim 1, wherein the first, second, and third latch groups are connected in multiple stages as a set.