KR100224759B1 - Input buffer of semiconductor memory device having serial comment - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input buffer of a semiconductor memory device in which a serial command signal is applied, thereby synchronizing by an external synchronizing clock to have a fast application speed into a chip. A clock generator comprising: a clock generator for generating an internal clock in response to an external synchronization clock; a control buffer unit for buffering and generating a predetermined control signal in response to a serial command signal generated in synchronization with the external synchronization clock; A transmission unit for receiving a signal through a predetermined delay circuit and controlling a delay time and supplying the delay to the chip; an output terminal is connected to a control terminal of the transmission unit, and the control unit responds to an output signal of the control buffer unit and the clock generator. The transmitter of the signal is turned on by a first control signal and the transmitter by a second control signal. It has a logic combination section for outputting a predetermined logic signal for turning off.

Description

Input buffer of semiconductor memory device with serial command

The present invention relates to a semiconductor memory device, and more particularly, to an input buffer of a synchronous semiconductor memory device having a serial command.

In general, the trend of the memory device used in the system (System) is a trend that changes from Asynchronous to Synchronous (Synchronous). The address and control signals CS and WE of the prior art are controlled by a clock signal input from the system. Therefore, the speed of the applied signal depends on the external synchronization clock XCLK. In addition, as the system becomes more complex, the signal is applied as a serial signal. 1 is a circuit diagram of an input buffer of a synchronous semiconductor memory device according to an embodiment of the prior art. Referring to FIG. 1, a structure for receiving an input signal with two transmission gates is shown. That is, the first transmission gate 10 and the second transmission gate 20 are configured. That is, the first transmission gate 10 is controlled by the first clock signal CLK1 and the second transmission gate 20 is controlled by the second clock signal CLK2. In addition, before the input signal XAI is applied, the control signal XCTRL must be enabled in a logic low state in the previous cycle. That is, the control signal XCTRL is a serial command signal preceding the input signal XAI. However, the circuit structure here uses two transfer gates similarly to the structure of a normal synchronous input buffer even when a serial command signal is received. FIG. 2 is an operation timing diagram of FIG. 1. Referring to FIG. 2, when the second clock signal CLK2 formed by the time T1 becomes logic high, the input signal XAI is applied through the second transmission gate 20. However, in general, since the input signal of the synchronous semiconductor memory device is applied 0.5NS4NS before the clock, the input signal waits until the second clock signal CLK2 is applied. Therefore, there is a problem that the same delay is required for the serial command input as the command that is not the serial input signal.

An object of the present invention is to provide an input buffer of a semiconductor memory device which speeds up the application of an input signal using a serial command signal into a chip.

1 is a circuit diagram of an input buffer of a synchronous semiconductor memory device according to an embodiment of the prior art.

2 is an operation timing diagram of FIG. 1.

3 is a circuit diagram of an input buffer of a synchronous semiconductor memory device according to an embodiment of the present invention.

4 is an operation timing diagram of FIG. 3.

According to the technical idea of the present invention for achieving the above objects, in the input buffer of the semiconductor memory device having a serial command, a clock generator for generating an internal clock in response to an external synchronization clock, and the synchronization with the external synchronization clock; A control buffer unit for buffering and generating a predetermined control signal in response to the generated serial command signal, a transmission unit for receiving an input clock signal through a predetermined delay circuit and controlling a delay time to supply the chip to the chip; An output terminal is connected to a control terminal of the transmission unit, and in response to an output signal of the control buffer unit and the clock generation unit, to turn on the transmission unit by a first control signal of the control signals and to turn off the transmission unit by a second control signal. A logic combination unit for outputting a predetermined logic signal is featured.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings. It should be noted that like elements and parts in the figures represent the same numerals wherever possible.

3 is a circuit diagram of an input buffer of a synchronous semiconductor memory device according to an embodiment of the present invention. Referring to FIG. 3, a clock buffer and a clock generator 13 generating an internal clock CLK0 'by inputting an external synchronous clock XCLK, and a control buffer 15 generating a control signal CTRL in response to a control signal XCTRL which is a serial command signal. And a logic combination unit for outputting an inverted and logically output signal in response to the output signals of the control buffer unit 15 and the clock generation unit 13, for example, a NOA gate 19 and a delay circuit 3-1 having an input signal XAI. And a transmission unit for inputting the output signal of the delay circuit 3-1, the control terminal being controlled as the output signal of the logic combination unit 19 and its inverted signal, for example, the transmission gate 10-1. And a latch circuit 5-1 for latching the output of the transfer gate 10-1 for a predetermined time and an inverter 7-1. 4 is an operation timing diagram of FIG. 3. Referring to FIG. 4, the clock buffer and the clock generator 13 generate an internal clock CLK0 'by detecting a high edge or a low edge of the external synchronization clock XCLK. The control buffer unit 15 generates the control signal CTRL by the XCTRL which is the first serial command signal, thereby determining whether to apply the input signal XAI which is the second serial command signal. The XCTRL is also a clock signal synchronized with the clock signal. When XCTRL is applied as a synchronous input at time T0, it is assumed that the output terminal of logic combination unit 19 transitions to a logic low state. At this time, since the clock signal CLK0 is a logic low state, the transistors constituting the control terminal of transfer gate 10-1 are NMOS transistors. The gate of the N1 and the PMOS transistor P1 may be turned on to apply an external command of the second clock signal XAI to the chip. In addition, since the timing T1, which is the logic high of XAI, is sensed, the clock signal CLK0 goes to the logic high to control the external wrong command from being applied. At this time, as the signal XCTRL is applied to the logic high, the signal goes to the logic high, thereby preventing the wrong operation from occurring because the external wrong signal is prevented from being applied even when the clock signal CLK0 goes to the logic low state next time. Accordingly, the speed increase by the time Tup can be obtained as compared with the conventional art.

According to the present invention, even when the serial command signal is used, the application speed of the external input signal to the chip can be increased, and the malfunction of the serial command signal due to the wrong serial command signal can be prevented by only one transmission gate to the transmitter. have.

Although the present invention described above has been limited to, for example, the drawings, the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the technical spirit of the present invention.

Claims (4)

In the input buffer of a semiconductor memory device having a serial command, A clock generator for generating an internal clock in response to an external synchronization clock; A control buffer unit for buffering and generating a predetermined control signal in response to a serial command signal generated in synchronization with the external synchronization clock; A transmission unit for receiving an input clock signal through predetermined delay circuits and controlling the delay time to supply the internal clock signal to the chip; An output terminal is connected to a control terminal of the transmission unit, and in response to an output signal of the control buffer unit and the clock generation unit, to turn on the transmission unit by a first control signal of the control signals and to turn off the transmission unit by a second control signal. And a logic combination unit for outputting a predetermined logic signal. The input buffer of claim 1, wherein the transfer unit is connected to a control terminal of the logic combination unit and controlled by an output signal of the logic combination unit and an inverted signal thereof. The input buffer of claim 1, wherein the transfer unit comprises one transfer gate. The input buffer of claim 1, wherein the logic combination unit comprises no gates.