JPH06177153A - Fabrication of thin film transistor - Google Patents

Abstract

PURPOSE:To achieve high operational characteristics by forming a metal compound layer on a low resistance semiconductor layer thereby ensuring positive electrical connection between an amorphous silicon thin film and source and drain electrodes even when the low resistance semiconductor layer is formed by ion implantation. CONSTITUTION:A gate electrode 12, a gate dielectric film 13, an amorphous silicon thin film 14, a low resistance semiconductor layer 17, an inorganic protective film 15, a source electrode 20, and a drain electrode 21 are formed on an insulating substrate 11 thus fabricating a thin film transistor. In this regard, the inorganic protective film 15 is formed on the amorphous silicon thin film 14 while being patterned and ion species containing impurity element ions are implanted in the amorphous silicon thin film 14 using the inorganic protective film 15 as an implantation stopper thus forming the low resistance semiconductor layer 17. A high melting point metal layer 18 is then formed on the low resistance semiconductor layer 17 with a metal compound layer 19 being formed on the interface thereof. Subsequently, the high melting point metal layer 18 is exfoliated to expose the metal compound layer 19 which is then partially removed by etching.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor used as an active element of an active matrix type liquid crystal display element.

[0002]

2. Description of the Related Art As a display device using a liquid crystal, a large-capacity and high-density active matrix type liquid crystal display device directed to a television display, a graphic display or the like has been developed and put into practical use. In such a display device, a semiconductor switch is used as a means for driving and controlling each pixel so that high-contrast display without crosstalk can be performed. As the semiconductor switch, a thin film transistor formed on a transparent insulating substrate is usually used because it can be used for transmissive display and can be easily enlarged. Among them, a thin film transistor using amorphous silicon is the most common because it can be formed on a large area substrate and can be processed at a low temperature.

The structure of a thin film transistor is roughly classified into a coplanar type or a staggered type depending on the relative positional relationship between the gate electrode, the semiconductor thin film layer, the source electrode and the drain electrode. In the case of an amorphous silicon thin film transistor formed on an insulating substrate, the latter, which has many beneficial aspects in the manufacturing process, is often used. Above all, as shown in FIG. 2, the gate electrode 2 and the gate insulating film are formed on the insulating substrate 1. The reverse staggered type is generally used in which the film 3, the amorphous silicon thin film 4, the low resistance semiconductor layer 5, the source electrode 6 and the drain electrode 7 are formed in this order.

In particular, as shown in FIG. 2, an inorganic protective film 8 made of, for example, silicon nitride is formed between the amorphous silicon thin film 4 and the low resistance semiconductor layer 5 and processed into a predetermined shape. By doing so, a structure having a structure that improves the workability of the low resistance semiconductor layer 5 is also used.

Generally, in an active matrix type liquid crystal display device, two substrates each subjected to an alignment treatment by rubbing are arranged parallel to each other so that their alignment directions are 90 degrees. A twisted nematic (TN) type liquid crystal device in which a nematic type liquid crystal composition is sandwiched between the two is widely used.

By the way, in this type of amorphous silicon thin film transistor, as shown in FIG. 2, a low resistance semiconductor layer 5 is formed between the amorphous silicon thin film 4 and the source and drain electrodes 6 and 7. It is common. This low resistance semiconductor layer 5 plays a role of electrically connecting the amorphous silicon thin film 4 and the source and drain electrodes 6 and 7 in an ohmic state.
The low-resistance semiconductor layer is formed by plasma CVD using a gas containing an element that can serve as a donor for silicon, such as phosphorus, as a raw material, and is stacked on the amorphous silicon thin film, and FIG. ), The resistance of the amorphous silicon thin film itself is reduced by a technique called so-called ion implantation in which an element that can serve as a donor to silicon, such as phosphorus, is ionically injected from the outside, and ohmic contact with the upper source and drain electrodes is achieved. A method of forming a contact layer or the like is common. (For example, RUUD EISCHROPP et.al. "On th
e Quality of Contacts in a-Si: H Staggered Electrod
eThin-Film Transisters "IEEE TRANSACTIONS ON ELECT
RON DEVICES, VOL.ED-32, NO.9, SEPTEMBER 1985)

As in the former case, the method of stacking the low resistance semiconductor layer on the upper portion of the amorphous semiconductor thin film by CVD is a method that has been performed before. However, the plasma CVD method used for film formation is This method includes many problems such as (1) generation of dust and (2) poor operating rate. on the other hand,
In the ion implantation method, since the amorphous silicon thin film itself formed in the previous step is reformed into the low resistance semiconductor layer by ion implantation, the problem such as the plasma CVD method is not included in principle. Further, ion implantation can be performed on the amorphous silicon thin film and can be performed in a self-aligned manner by using the inorganic protective film processed into a desired shape as a mask, which enables high performance and miniaturization of the thin film transistor.

FIG. 3 is a sectional view showing a thin film transistor formed by using an ion implantation method, and FIG. 4 is a sectional view showing a manufacturing process of the thin film transistor shown in FIG. 3, which corresponds to FIG. 2 in FIGS. The same reference numerals are given to the parts to be marked. This conventional example will be described according to the manufacturing process. First, as shown in FIG. 4A, the gate electrode 2 is formed on the insulating substrate 1, and then, as shown in FIG. 4B, the gate electrode 2 is formed. A gate insulating film 3 is formed so as to cover the. Next, as shown in FIG. 4C, the amorphous silicon thin film 4 and the inorganic protective film 8 are sequentially formed on the gate insulating film 3. Subsequently, as shown in FIG. 4D, ion implantation is performed from above the gate insulating film 3, the amorphous silicon thin film 4 and the inorganic protective film 8.
By this ion implantation, as shown in FIG. 4E, the surface of the amorphous silicon thin film 4 exposed from the inorganic protective film 8 changes into the low resistance semiconductor layer 5, and the source electrode 6 and the drain electrode 7 are formed.
By forming the above, a thin film transistor as shown in FIG. 3 is obtained.

[0009]

However, in the conventional ion implantation method, as shown in FIGS. 3 and 4, the inorganic protective film 8 formed on the amorphous silicon thin film 4 and processed into a predetermined shape. Is used as a mask in a self-aligned manner, as shown in FIG.
In the ion implantation into the source / drain regions in the state as shown in (3), ions are directly implanted into the surface of the amorphous silicon thin film 4. This has caused physical or scientific damage to the connection interface between the source electrode 6 and the drain electrode 7, which is important for ohmic connection. For example, along with the ion implantation, silicon that is a constituent atom of the implanted layer is sputtered from the surface of the amorphous silicon thin film 4 that is the implanted layer.

Phosphorus is used as the ion-implanted species, crystalline silicon is used as the ion-implanted layer, and the density of the crystalline silicon is 2.3210 g / c.
m ³ Assuming that the surface binding energy is 4.7 eV and the number of constituent atoms of the implanted layer sputtered from the surface of the implanted layer due to ion implantation is calculated, an acceleration voltage of 30
(KV), the sputtering rate of silicon atoms is 0.614
(Atoms [Si] / ion [P]), that is, about 60%, and it can be seen that the surface of the ion-implanted layer is significantly damaged by the ion implantation. In the case of the conventional example shown in FIG. 3, since the layer to be ion-implanted is made of amorphous silicon, there is no suitable means for removing the damaged portion of the surface due to ion implantation. Therefore, when the conventional ion implantation method is used, the influence on the transistor characteristics, which has not occurred in the structure and the manufacturing method using plasma CVD for forming the low resistance semiconductor layer 5 as shown in FIG. 2, becomes a problem.

The present invention has been conceived in view of such conventional circumstances, and even when the low resistance semiconductor layer is formed by the ion implantation method, the electrical conductivity between the amorphous silicon thin film, the source electrode and the drain electrode is high. It is an object of the present invention to provide an amorphous silicon thin film transistor that can be reliably connected and can obtain high operating characteristics.

[0012]

The present invention is a thin film transistor having a gate electrode, a gate insulating film, an amorphous silicon thin film, a low resistance semiconductor layer, an inorganic protective film, a source electrode and a drain electrode formed on an insulating substrate. The process of forming and shaping an inorganic protective film on an amorphous silicon thin film, and implanting an ion species containing impurity element ions into the amorphous silicon thin film using the inorganic protective film as an injection stopper. To form a low resistance semiconductor layer, a step of forming a refractory metal layer on the low resistance semiconductor layer, and a step of forming a metal compound layer at the interface between the low resistance semiconductor layer and the refractory metal layer; A step of peeling the layer to expose the metal compound layer and etching away a part of the metal compound layer.

[0013]

According to the present invention, by forming a metal compound layer on a low resistance semiconductor layer, the surface of the low resistance semiconductor layer damaged by ion implantation can be smoothed by etching. It is possible to form a contact with the source and drain electrodes in a region having a high concentration of implanted ion species, and to form an amorphous silicon thin film transistor that ensures reliable electrical connection and high operating characteristics.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing an embodiment of the present invention. To explain according to the manufacturing process using FIG. 1, first,
As shown in FIG. 1A, after forming the gate electrode 12 on the insulating substrate 11, C such as plasma, normal pressure and reduced pressure is applied.
A gate insulating film 13 is formed so as to cover the gate electrode 12 by forming a silicon nitride film with a thickness of 4000 angstrom using monosilane as a raw material by the VD method. Then, as shown in FIG. 1B, the gate insulating film 1
An amorphous silicon thin film 14 having a film thickness of 500 angstroms and an inorganic protective film 15 having a film thickness of 3000 angstroms are formed on the substrate 3, and the inorganic protective film 15 is processed into a predetermined shape. Subsequently, as shown in FIG. 1C, ions of an element that can serve as a donor, for example, phosphorus ions, are applied at an acceleration voltage of 30 kV,
Dose amount 1E16 / cm ² Inject. At this time, since the inorganic protective film 15 can serve as an implantation stopper at the time of phosphorus ion implantation, ions are not implanted into the channel region 16 of the thin film transistor, resulting in self-alignment. As a result, the resistance of a part of the amorphous silicon thin film 14 is lowered, and the source region 17a and the drain region 17b are formed as the low resistance semiconductor layer 17 in addition to the channel region 16. After that, as shown in FIG. 1D, the refractory metal layer 1
As molybdenum 8, for example, molybdenum is deposited to a thickness of 1000 angstrom. At this time, the metal compound layer 19 is formed at the interface between the low-resistance semiconductor layer 17 and the refractory metal layer 18 by heat treatment or the like. Then, as shown in FIG.
After processing the low resistance semiconductor layer 17 and the refractory metal layer 18 into a predetermined shape, the refractory metal layer 18 is peeled off from the inorganic protective film 15 and the low resistance semiconductor layer 17 through a peeling step. Then, after the peeling, a hydrofluoric acid treatment is further applied to the low resistance semiconductor layer 1
The surface of the metal compound layer 19 formed on 7 is removed by tens to hundreds of angstroms by etching. Then, Figure 1
As shown in (f), the source electrode 20 and the drain electrode 21 are formed by sequentially forming an electrode material that can serve as the source and drain electrodes, for example, molybdenum and aluminum, and processing the shape. Thus, an array substrate provided with the thin film transistor is obtained, and the desired active matrix liquid crystal display device is obtained by combining the array substrate with the counter substrate on which the counter electrode and the like are formed and sandwiching the liquid crystal in this gap. Be done.

In this embodiment, a part of the surface of the metal compound layer 19 formed on the low resistance semiconductor layer 17 is removed by etching, so that the surface of the low resistance semiconductor layer 17 damaged by the ion implantation is smoothed. In addition, it is possible to make contact with the source electrode 20 and the drain electrode 21 in a region in the low resistance semiconductor layer 17 where the concentration of implanted ion species is high. As a result, the electrical connection between the low resistance semiconductor layer 17 and the source electrode 20 and the drain electrode 21 was improved.

The present invention can be applied not only to the active matrix type liquid crystal display device but also to the manufacture of various sensors. The material used for the refractory metal layer is not limited to molybdenum, but may be titanium, tantalum, tungsten, or the like.

[0018]

According to the present invention, after a low resistance semiconductor layer is formed by ion implantation, a refractory metal layer is deposited on the low resistance semiconductor layer to form a metal compound at the interface between the low resistance semiconductor layer and the refractory metal layer. By forming a layer, peeling off the refractory metal layer, and etching away a part of the exposed surface of the metal compound layer on the low resistance semiconductor layer, the low resistance semiconductor layer and the source and drain electrodes are separated. In addition to smoothing the connection interface, it is possible to make contact with the source / drain electrode 21 in a region having a high concentration of implanted ion species in the low resistance semiconductor layer. As a result, the low resistance semiconductor layer can be reliably electrically connected to the source and drain electrodes, and an amorphous silicon thin film transistor having high operating characteristics can be formed.

[Brief description of drawings]

FIG. 1 is a sectional view showing a manufacturing process of an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing an example of a conventional thin film transistor.

FIG. 3 is a cross-sectional view showing another example of a conventional thin film transistor.

FIG. 4 is a cross-sectional view showing a manufacturing process of the conventional example shown in FIG.

[Explanation of symbols]

 11 ... Insulating substrate 12 ... Gate electrode 13 ... Gate insulating film 14 ... Amorphous silicon thin film 15 ... Inorganic protective film 17 ... Low resistance semiconductor layer 18 ... Refractory metal layer 19 ... Metal compound layer 20 ... Source electrode 21 ... Drain electrode

Claims (1)

[Claims] 1. A method of manufacturing a thin film transistor, which comprises forming a gate electrode, a gate insulating film, an amorphous silicon thin film, a low resistance semiconductor layer, an inorganic protective film, a source electrode and a drain electrode on an insulating substrate, wherein the amorphous A step of forming and shaping the inorganic protective film on a silicon thin film, and implanting an ion species containing an impurity element ion into the amorphous silicon thin film as an implantation stopper of the inorganic protective film to form the low resistance semiconductor layer. A step of forming, a step of forming a refractory metal layer on the low resistance semiconductor layer, a step of forming a metal compound layer at the interface between the low resistance semiconductor layer and the refractory metal layer, and peeling of the refractory metal layer And exposing the metal compound layer to remove a part of the metal compound layer by etching.