JPH06169247A - Analog switch - Google Patents

Abstract

PURPOSE:To attain the normal operation of the analog switch even at a low power supply voltage by selecting a threshold voltage of MOS transistors(TRs) to be 0.1-0.4V in absolute value or adopting a depletion TR for the MOS TR to specify a parameter gamma of a base bias effect to be 0.8<gamma<1.5. CONSTITUTION:A threshold voltage of PMOS TRs 3, 7-9 is set smaller than a usual threshold voltage as -0.1 to -0.4V and a threshold voltage of NMOS TRs 4, 10-12 is set smaller than a usual threshold voltage as 0.1 to 0.4V. As a result, since a gate-source voltage to conduct the MOSTRs is enough to be the low threshold voltage, the MOSTRs are sufficiently conducted even when the power supply voltage is decreased and the internal resistance for the case is much decreased. Furthermore, the concentration of the base of the MOSTRs (impurity concentration of epitaxial layer for PMOSTRs and impurity concentration of well for NMOSTRs) is set higher than the usual impurity concentration. Then a parameter gamma of a base bias effect is selected larger as 0.8<gamma<1.5 (usually gamma<0.6).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog switch which operates normally even at a low power supply voltage.

[0002]

2. Description of the Related Art In a single MOS transistor, an analog switch has a non-linear characteristic of conduction resistance / input voltage. To solve this, as shown in FIG. A P-type MOS transistor 3 and an N-type MOS transistor 4 are connected in parallel between the input / output terminal 2 and the input / output terminal 2. In this analog switch, the control signal applied to the control terminal 5 is supplied to one MO
When the control signal is "H", both MOS transistors are applied by directly applying to the gate of the S transistor 4 and inverting and applying to the other MOS transistor 3 by the inverter 6.
Transistors 3 and 4 are turned on at the same time and turned off at the same time when they are "L".

In this analog switch, the threshold value V _TH of the MOS transistors 3 and 4 is an absolute value of 0.6 to 0.8 V, and a voltage higher than this value is applied between the gate and source of the MOS transistors 3 and 4. By applying, conduction is established between the drain and the source. The conduction resistance at this time is several tens Ω to several hundreds Ω. When the voltage between the gate and the source is less than the above voltage, the gate is cut off, and the resistance between them is in the order of hundreds to thousands of Ω.

[0004]

However, the above operation is guaranteed when the voltage difference between the power supply voltages V _dd and V _ss is about 1.5 V or more. There is a problem that the internal resistance between the source and the drain becomes large and the loss of the signal passing therethrough becomes large. Therefore, it was considered to reduce the threshold value V _TH , but if this is done, the cut-off resistance will decrease and a relatively large leak current will flow between the source and drain.

An object of the present invention is to provide an analog switch which has a small internal resistance when conducting even at a low power supply voltage and has a small leak current when shutting off.

[0006]

To this end, the present invention provides P
Type N-type MOS transistor and N-type MOS transistor are connected in parallel, the substrate bias when the P-type MOS transistor is conductive is set to zero, and the substrate bias when cut off is set to the power supply voltage V _dd , and the N-type MOS transistor is made conductive. In the analog switch in which the substrate bias at the time is set to zero and the substrate bias at the time of interruption is set to the power supply voltage V _ss , the thresholds of both MOS transistors are 0.1 to 100 in absolute value.
0.4v or a depletion type, and a parameter γ representing the substrate bias effect is 0.8 <γ <1.5
Set to.

[0007]

EXAMPLES Examples of the present invention will be described below. FIG. 2 is a circuit diagram of an analog switch to which the present invention is applied. The same parts as those in FIG. 1 are designated by the same reference numerals. 7-9
Is a P-type MOS transistor, and 10 to 12 are N-type MOS transistors, all of which are for controlling the substrate bias of the MOS transistors 3 and 4 constituting the analog switch body.

In this analog switch, when the voltage of the control terminal 5 is "H", the MOS constituting the switch body is formed.
Transistors 3 and 4 become conductive, and M for substrate bias control
The OS transistors 8, 9, 11, 12 are also conductive, and the MOS
The transistors 7 and 10 are turned off.

Therefore, the voltage of the input / output terminal 1 (the source voltage of the MOS transistor 3) is applied as a bias to the substrate of the MOS transistor 3 by the conduction of the MOS transistor 8, and the voltage of the input / output terminal 2 by the conduction of the MOS transistor 12. (Source voltage of MOS transistor 4)
Is applied as a bias to the substrate of the MOS transistor 4. That is, the substrate bias of both MOS transistors 3 and 4 at this time becomes zero.

On the contrary, when the voltage of the control terminal 5 is "L", the MOS transistors 3 and 4 constituting the switch body are formed.
Is cut off, and the MOS transistors 8, 9, 11, 12 for controlling the substrate bias are also cut off, and the MOS transistor 7,
10 conducts.

Therefore, the power source voltage V _dd is applied as a bias to the substrate of the MOS transistor 3 by the conduction of the MOS transistor 7, and the power source voltage V _ss (= ground potential) is applied to the substrate of the MOS transistor 4 by the conduction of the MOS transistor 10. Applied as a bias. Therefore, at this time, the MOS transistors 3 and 4 shift in the direction in which the threshold value V _TH thereof increases due to the substrate bias effect, and the cutoff effect is enhanced.

In the analog switch having such a circuit structure, in this embodiment, the substrate of each of the MOS transistors 3, 4, 7 to 12 of the circuit is made independent from the other. As shown in FIG. 3, for P-type MOS transistors 3 and 7 to 9, for example, an N-type epitaxial layer 21 is formed on the upper surface of a P-type substrate 20, and the N-type epitaxial layer 21 is formed in the epitaxial layer 21. The MOS transistors 3 and 7 to 9 are directly formed, and the portion is separated from others by the isolation region 22. For the N-type MOS transistors 4, 10 to 12, a P-type well 23 is formed in the epitaxial layer 21, and the MOS transistor 4,
10 to 12 can be formed, and this can also be realized by a structure in which the isolation region 22 separates it from the others. Such a structure is known in a semiconductor device in which both a bipolar transistor and a MOS transistor are formed on the same substrate.

In this way, by making each MOS transistor independent, its substrate (in the P-type MOS transistor, the region surrounded by the isolation region 22, the N-type M) is formed.
In the OS transistor, a bias can be applied to the well 23) independently of others.

Further, in this embodiment, the threshold value V _TH of the P-type MOS transistors 3 and 7 to 9 is set smaller than usual, such as -0.1 to -0.4v, and the N-type MOS transistors 4 and 10 are set. The threshold value V _{TH of} 12 is also set small like 0.1 to 0.4 v.

As a result, the gate-source voltage V _GS for making these MOS transistors conductive only needs to be the voltage of the low threshold value V _TH , so that even if the power supply voltage drops (for example, about 0.6 V), The MOS transistors can be made sufficiently conductive and the internal resistance at that time can be made extremely small.

Further, in this embodiment, the concentration of the substrate forming these MOS transistors (the impurity concentration of the epitaxial layer 21 in the P-type MOS transistor, the impurity concentration of the well 23 in the N-type MOS transistor) is set higher than usual, The parameter γ value indicating the substrate bias effect is 0.8 <γ <1.5 when normally γ <0.6.
Set it to a large value.

As a result, the MOS transistors 7, 1
When 0 is conducted and the power supply voltages V _dd and V _ss are applied to the substrate bias, the threshold value V _TH of each MOS transistor is shifted to a larger value than before (when γ <0.6). As a result, the threshold value V _TH becomes substantially large and it becomes difficult to conduct electricity. That is, the internal resistance at the time of interruption becomes large, and the leak current becomes small. The lower limit value of γ, “0.8”, is a value at which the substrate bias effect begins to become remarkable, and the upper limit, “1.5”, was determined from the allowable value of resistance in the process and during conduction.

Now, the relationship between V _TH and γ described above will be described. The P-type MOS transistor 3 has the relationship of the following expression 1, and the N-type MOS transistor 4 has the relationship of the following expression 2. _{V TP <V TP (SW)} ≦ V TP + γ P ([V dd / 2] + 2φ fP) 1/2 ··· (1) V TN -γ N ([V dd / 2] + 2φ fN) 1/2 ≤ V _{TN (SW)} <V _TN (2)

V _TP : V _TH of the P-type MOS transistors 7 to 9 V _{TP (SW)} : V _{TH of the} P-type MOS transistor 3 γ _P : γ φ _{fP of the} P-type MOS transistor 3 Fermi of the P-type MOS transistor 3 level V _TN: N-type MOS transistor _{10~12 V TH V TN (SW)} : V TH of the N-type MOS transistor 4 gamma _N: gamma of N-type MOS transistor 4 phi _fN: Fermi level of the N-type MOS transistor 4 V _dd : Power supply voltage

In equation (1), "γ _P ([V _dd / 2] +
2φ _fP) ^1/2 "indicates a shift amount of V _TH due to the substrate bias effect. Therefore, if V _{TP (SW)} is set in advance so as to fall within the range of Equation 1, the apparent V _TH of V _{TP (SW)} when the substrate bias effect is working will be more than V _TP. Works well without. γ _P and V _{TP (SW)} are set in this range. The above also applies to the equation (2).

When the analog switch is conducting, the substrate bias effect hardly acts, so V _{TP (SW)} > V _TP ,
Since V _{TN (SW)} <V _TN , the internal resistance can be reduced. Further, when the analog switch is cut off, the substrate bias effect works, resulting in V _{TP (SW) to} V _TP and V _{TN (SW) to} V _TN , and the leak current can be suppressed small.

Although the P type is used for the substrate 20 in FIG. 3, it is also possible to use the N type, and in this case, an N type MOS transistor is formed in the P type epitaxial layer to form the P type. Will be formed in the N-type well.

In the above description, each MOS transistor has been described as an enhancement type, but in the present invention, it is important that the threshold value V _TH at the time of conduction is low, so it may be a depletion type. Even in this depletion type, the threshold V _{TH is} caused by the substrate bias effect at the time of interruption.
It is possible to prevent the leakage current from increasing by shifting (increasing the enhancement type) in the direction of increasing.

[0024]

As described above, according to the analog switch of the present invention, the threshold voltage V _TH of each MOS transistor becomes small at the time of conduction, and the characteristics become a depletion type or a characteristic close to it, so that the internal resistance becomes small. Due to the effect, the threshold value V _TH is substantially increased and the internal resistance is sufficiently increased, so that even if the power supply voltage is low, the switch function thereof can be sufficiently exerted.

[Brief description of drawings]

FIG. 1 is a principle circuit diagram of an analog switch.

FIG. 2 is a circuit diagram of an analog switch to which the present invention is applied.

FIG. 3 is a structural diagram of substrate separation of a P-type MOS transistor and an N-type MOS transistor.

[Explanation of symbols] 1, 2: Input / output terminals, 3: P-type MOS transistor,
4: N-type MOS transistor, 5: Control terminal, 6: Inverter, 7-9: P-type MOS transistor, 10-1
2: N-type MOS transistor.

Claims (1)

[Claims] 1. A P-type MOS transistor and an N-type MOS transistor are connected in parallel, the substrate bias when the P-type MOS transistor is conductive is set to zero, and the substrate bias when cut off is set to a power supply voltage V _dd. In an analog switch in which the substrate bias when the N-type MOS transistor is conductive is set to zero and the substrate bias when cut off is set to the power supply voltage V _ss , the threshold values of both the MOS transistors are 0.1 in absolute value.
.About.0.4 v or a depletion type, and a parameter γ representing the substrate bias effect is 0.8 <γ <1.
An analog switch characterized by being set to 5.