JPH0616557B2 - Method for manufacturing insulated gate field effect semiconductor device - Google Patents
Method for manufacturing insulated gate field effect semiconductor deviceInfo
- Publication number
- JPH0616557B2 JPH0616557B2 JP61005260A JP526086A JPH0616557B2 JP H0616557 B2 JPH0616557 B2 JP H0616557B2 JP 61005260 A JP61005260 A JP 61005260A JP 526086 A JP526086 A JP 526086A JP H0616557 B2 JPH0616557 B2 JP H0616557B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- gate electrode
- drain
- conductivity type
- island
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 21
- 238000000034 method Methods 0.000 title claims description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 230000005669 field effect Effects 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims description 14
- 239000012535 impurity Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims description 3
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 description 18
- 230000005684 electric field Effects 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Description
【発明の詳細な説明】 イ．産業上の利用分野 本発明は絶縁ゲート型電界効果半導体装置の製造方法に
関し、例えばＭＯＳＦＥＴ（Metal Oxide Semiconducto
r Field Effect Transistor）の製造方法に関するもの
である。Detailed Description of the Invention a. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an insulated gate field effect semiconductor device, for example, a MOSFET (Metal Oxide Semiconducto).
r Field Effect Transistor) manufacturing method.
ロ．従来技術 従来、ＭＯＳＦＥＴにおいて、ゲートとドレイン部分で
破壊が生じることはよく知られている。例えば、ドレイ
ン側に電圧を加えてゆくと、ドレインとゲートの部分で
アバランシェ破壊が生じ、これが高耐圧用トランジスタ
等にとって大きな弱点である。B. 2. Description of the Related Art Conventionally, it is well known that breakdown occurs in the gate and drain portions of MOSFET. For example, when a voltage is applied to the drain side, avalanche breakdown occurs in the drain and gate portions, which is a major weak point for high breakdown voltage transistors and the like.
この対策として、第７図〜第９図に示す構造が知られて
いる。第７図はいわゆるＬＤＤ（Lightly Doped Drai
n）構造のＭＯＳＦＥＴであって、Ｎ+型ドレイン領域１
及びソース領域６に接してゲート電極２下に少し食い込
んだ低濃度Ｎ−型半導体領域３、７を形成することによ
って、ゲートによるドレイン近傍での電界集中を緩和し
ている。第８図はオフセット構造を示し、Ｎ−型半導体
領域３を形成すると共にゲート電極２をオフセットして
電界集中を少なくしている。第９図はＧＧＯ（Graded G
ate Oxide）構造を示し、フィールド酸化膜４下にＮ−
型半導体領域３を形成する一方、ゲート電極２を同酸化
膜４上に延設している。なお、図中の５はＰ型半導体基
板、６はＮ＋型ソース領域、８はゲート酸化膜、９はＳ
ｉＯ２膜、１０はソース電極、１１はドレイン電極であ
る。As measures against this, the structures shown in FIGS. 7 to 9 are known. Figure 7 shows the so-called LDD (Lightly Doped Drai).
n) structure MOSFET, N + type drain region 1
By forming the low concentration N − type semiconductor regions 3 and 7 which are in contact with the source region 6 and slightly under the gate electrode 2, the electric field concentration due to the gate in the vicinity of the drain is relaxed. FIG. 8 shows an offset structure in which the N − type semiconductor region 3 is formed and the gate electrode 2 is offset to reduce the electric field concentration. Figure 9 shows GGO (Graded G)
ate Oxide) structure, and N − under the field oxide film 4.
While forming the type semiconductor region 3, the gate electrode 2 is extended on the oxide film 4. In the figure, 5 is a P-type semiconductor substrate, 6 is an N + -type source region, 8 is a gate oxide film, and 9 is S.
The iO 2 film, 10 is a source electrode, and 11 is a drain electrode.
ところで、これらの各構造のＭＯＳＦＥＴはいずれも、
次の如き欠点がある。By the way, the MOSFETs of each of these structures are
It has the following drawbacks.
(1)．低濃度、例えば1014／cm3オーダーの領域３が存在
するために、トランジスタの利得（ｇｍ）が低下する。(1). Due to the presence of the region 3 having a low concentration, for example, on the order of 10 14 / cm 3 , the gain (gm) of the transistor is lowered.
(2)．長時間使用すると、低濃度領域３上に反転層が生
じ、このためにやはり利得低下が生じ易くなる。(2). When used for a long time, an inversion layer is formed on the low-concentration region 3, which also tends to cause a decrease in gain.
(3)．低濃度領域３はソース及びドレイン領域とは別の
イオン注入工程を経て形成する必要があるので、製造工
程が増えてしまう。(3). Since the low-concentration region 3 needs to be formed through an ion implantation process different from the source and drain regions, the number of manufacturing processes increases.
ハ．発明の目的 本発明の目的は、電界集中の緩和によって効果的に破壊
を防止でき、かつ高利得、高信頼性で製造容易な絶縁ゲ
ート型電界効果半導体装置の製造方法を提供することに
ある。C. It is an object of the present invention to provide a method for manufacturing an insulated gate field effect semiconductor device, which can effectively prevent breakdown by relaxing electric field concentration, and has high gain, high reliability, and easy manufacturing.
ニ．発明の構成 すなわち、本発明は、第１導電型の半導体基板の表面に
絶縁膜を形成する工程と、前記絶縁膜上に導電膜を形成
する工程と、前記導電膜に対しフォトリソグラフィー及
びエッチング処理を施して孔を備えるゲート電極を形成
する工程と、前記ゲート電極をマスクとして第２導電型
の不純物を照射し、前記ゲート電極が存在しない領域下
の前記半導体基板表面に前記第２導電型の不純物を打ち
込んで、前記ゲート電極の外側に位置する所定の前記半
導体基板表面に第２導電型のソース及びドレイン領域を
それぞれ形成するとともに前記ゲート電極の孔と対向す
る前記半導体基板表面に第２導電型の島状領域を形成す
る工程とを有する絶縁ゲート型電界効果半導体装置の製
造方法に係るものである。D. Configuration of the Invention That is, the present invention provides a step of forming an insulating film on the surface of a first conductivity type semiconductor substrate, a step of forming a conductive film on the insulating film, and a photolithography and etching treatment for the conductive film. To form a gate electrode having a hole, and irradiating the second conductivity type impurity with the gate electrode as a mask to expose the semiconductor substrate surface under the region where the gate electrode does not exist to the second conductivity type. Impurities are implanted to form source and drain regions of the second conductivity type on the surface of the predetermined semiconductor substrate located outside the gate electrode, and the second conductivity is formed on the surface of the semiconductor substrate facing the holes of the gate electrode. A method of manufacturing an insulated gate field effect semiconductor device having a step of forming a mold island region.
ホ．実施例 以下に、本発明の実施例を第１図〜第６図について詳細
に説明する。但し、第７図〜第９図と共通する部分に
は、共通符号を付してその説明を省略する。E. Embodiments Embodiments of the present invention will be described in detail below with reference to FIGS. However, parts common to those in FIGS. 7 to 9 are designated by common reference numerals, and description thereof will be omitted.
第１図及び第２図は、第１の実施例によるＭＯＳＦＥＴ
を示すものである。1 and 2 show a MOSFET according to the first embodiment.
Is shown.
このトランジスタによれば、ソース領域６とドレイン領
域１との間のチャネル領域１２に、両領域６及び１と同
一導電型であってそれら各領域から分離された島状（こ
こでは小円形の浮き島状で電気的にはフローティング状
態）の高濃度Ｎ＋型半導体領域１３が多数個形成されて
いる。これらの島状領域１３は夫々、ソース領域６及び
ドレイン領域１とほぼ同じ不純物濃度（例えば1016〜10
18／cm3）を有しており、後述するイオン注入によって
セルフアラインに拡散形成されたものである。これに対
応して、ポリシリコンゲート電極２２は多数の小孔１４
が上記島状領域１３と一対一に形成されている。また、
ドレイン領域１にコンタクトされた電極１１は、上記各
島状領域１３を全面的に覆う如くにチャネル領域１２上
にまで延設されている。According to this transistor, in the channel region 12 between the source region 6 and the drain region 1, island-shaped regions (here, small circular floating islands) of the same conductivity type as those of the regions 6 and 1 are separated from each other. A large number of high-concentration N + type semiconductor regions 13 that are electrically floating) are formed. Each of these island regions 13 has almost the same impurity concentration (for example, 10 16 to 10 16) as the source region 6 and the drain region 1.
18 / cm 3 ) and is self-aligned and diffused by the ion implantation described later. Correspondingly, the polysilicon gate electrode 22 has a large number of small holes 14
Are formed in one-to-one correspondence with the island regions 13. Also,
The electrode 11 in contact with the drain region 1 is extended to above the channel region 12 so as to cover the island regions 13 entirely.
上記のように、島状（フローティング状態の浮き島状）
領域１３を形成すれば、動作時に、ゲート及びドレイン
の部分で破壊（アバランシェ破壊）が発生する電圧より
低い電圧値でドレイン領域１と島状領域１３との間に第
２図に破線１５で示すように空乏層が生じ、パンチスル
ー現象が起る。このパンチスルーが生じるように予めド
レイン領域１と島状領域１３との距離を設定している。
この結果、上記空乏層１５によってゲート２２による電
界の集中が効果的に緩和され、ドレイ破壊電圧が平滑
（plane）な電圧値まで高められる。例えば、従来の構
造ではドレイン破壊が18〜20Ｖで生じていたが、本実施
例の構造によってドレイン破壊電圧を80〜100Ｖに高め
ることが可能である。As described above, islands (floating islands in a floating state)
If the region 13 is formed, it is indicated by a broken line 15 in FIG. 2 between the drain region 1 and the island region 13 at a voltage value lower than the voltage at which breakdown (avalanche breakdown) occurs in the gate and drain portions during operation. As described above, a depletion layer is generated and a punch through phenomenon occurs. The distance between the drain region 1 and the island region 13 is set in advance so that this punch-through occurs.
As a result, the depletion layer 15 effectively relaxes the concentration of the electric field by the gate 22, and the drain breakdown voltage is increased to a smooth voltage value. For example, the drain breakdown occurs at 18 to 20 V in the conventional structure, but the drain breakdown voltage can be increased to 80 to 100 V by the structure of this embodiment.
しかも、上記島状領域１３は高不純物濃度を有している
ので、トランジスタとしての動作時に従来の如き利得低
下や反転層の発生が生じ難く、信頼性の良いデバイスを
提供できる。このＭＯＳＦＥＴが導通（オン）状態のと
き、島状領域１３は低抵抗として働くので、同じチャネ
ル長を有するＭＯＳＦＥＴと比較して実効チャネル長は
短くなり、このため大きな利得が得られる。Moreover, since the island-shaped region 13 has a high impurity concentration, it is possible to provide a highly reliable device in which the decrease in gain and the generation of the inversion layer as in the conventional case are unlikely to occur when operating as a transistor. When the MOSFET is in the conductive (ON) state, the island-shaped region 13 functions as a low resistance, so that the effective channel length is shorter than that of the MOSFET having the same channel length, and thus a large gain is obtained.
また、ドレイン破壊は、基板５の不純物濃度とドレイン
領域１の拡散深さとによってコントロールでき、一般に
その拡散深さを大きくすること及び基板濃度を低くする
ことによって耐圧を高め、ドレイン破壊を生じ難くする
ことができる。Further, the drain breakdown can be controlled by the impurity concentration of the substrate 5 and the diffusion depth of the drain region 1. Generally, by increasing the diffusion depth and decreasing the substrate concentration, the breakdown voltage is increased and the drain breakdown is less likely to occur. be able to.
また、本実施例では、ドレイン電極１１をチャネル領域
１２上に延設せしめ、同領域上を覆っているので、この
延設部分１１ａによって更にゲート電極による電界集中
を緩和し、耐圧を向上させることができる。Further, in this embodiment, since the drain electrode 11 is extended on the channel region 12 and covers the same, the extended portion 11a can further alleviate the electric field concentration by the gate electrode and improve the breakdown voltage. You can
本実施例によるＭＯＳＦＥＴは、破壊の生じ難い構造で
あってドレイン側に加わる電圧によるゲート破壊（又は
ゲートによるドレイン近傍での電界集中）を少なくでき
るので、こうしたゲート破壊或いはホットエレクトロン
の発生を嫌う例えば高耐圧、高電圧用トランジスタ、シ
ョートチャネルトランジスタや、ダイナミックＲＡＭ
（random access memory）及びスタティックＲＡＭの周
辺回路用のトランジスタ等として好適である。The MOSFET according to the present embodiment has a structure in which breakdown is unlikely to occur, and gate breakdown due to a voltage applied to the drain side (or electric field concentration near the drain due to the gate) can be reduced. High breakdown voltage, high voltage transistor, short channel transistor, dynamic RAM
It is suitable as a (random access memory) and a transistor for peripheral circuits of static RAM.
次に、本実施例によるＭＯＳＦＥＴの製造方法の主たる
過程を第３図で説明する。Next, the main steps of the method for manufacturing the MOSFET according to this embodiment will be described with reference to FIG.
まず第３Ａ図のように、Ｐ型シリコン基板５の一主面
に、公知の熱酸化技術及び化学的気相成長（ＣＶＤ）技
術によってＳｉＯ２膜８、不純物ドープド低抵抗ポリシ
リコン膜２２を形成する。First, as shown in FIG. 3A, a SiO 2 film 8 and an impurity-doped low resistance polysilicon film 22 are formed on one main surface of a P-type silicon substrate 5 by a known thermal oxidation technique and chemical vapor deposition (CVD) technique. To do.
次いで第３Ｂ図のように、フォトリソグラフィー及びエ
ッチングによってポリシリコン膜２２をゲート電極形状
に加工すると同時に、上記した多数の小孔１４も形成す
る。Next, as shown in FIG. 3B, the polysilicon film 22 is processed into a gate electrode shape by photolithography and etching, and at the same time, a large number of the small holes 14 are formed.
次いで第３Ｃ図のように、イオン注入によってＮ型不純
物、例えば砒素イオン１６を照射し、ポリシリコン膜２
２の存在しない領域下の基板表面に打ち込み、Ｎ＋型の
ソース領域６、ドレイン領域１、島状領域１３を夫々セ
ルフアラインに形成する。Next, as shown in FIG. 3C, an N-type impurity, for example, arsenic ion 16 is irradiated by ion implantation to form a polysilicon film 2
By implanting into the surface of the substrate below the region where 2 does not exist, the N + type source region 6, the drain region 1 and the island region 13 are formed in self-alignment.
従って、このＭＯＳＦＥＴは、従来のプロセスを変更す
ることなく製造できるので、極めて都合がよい。なお、
第３Ｃ図の工程で、打ち込みイオンのドーズ量又は濃度
を変えれば、上述した空乏層１５（第２図参照）の伸び
方を変化させ、耐圧をコントロールできる。このために
は、ソース及びドレイン領域とは別に、島状領域１３を
形成するためのイオン注入を行ってもよい。Therefore, this MOSFET is extremely convenient because it can be manufactured without changing the conventional process. In addition,
By changing the dose amount or concentration of the implanted ions in the step of FIG. 3C, it is possible to change the extension of the depletion layer 15 (see FIG. 2) and control the breakdown voltage. For this purpose, ion implantation for forming the island-shaped regions 13 may be performed separately from the source and drain regions.
第４図及び第５図は、本発明の他の実施例を示すもので
ある。4 and 5 show another embodiment of the present invention.
これらの例では、島状領域１３の個数及び形状（パター
ン）を変え、第４図ではソース及びドレイン領域側にの
み夫々１列形成し、また第５図では島状領域１３を夫々
連続層として形成している。このように構成しても、上
述した実施例と同様の作用効果が得られる。In these examples, the number and shape (pattern) of the island regions 13 are changed, one row is formed only on the source and drain region sides in FIG. 4, and the island regions 13 are formed as continuous layers in FIG. Is forming. Even with this configuration, the same operational effects as those of the above-described embodiment can be obtained.
第６図は、更に他の実施例を示すものである。FIG. 6 shows still another embodiment.
この例によれば、島状領域１３は上述の例（第２図）と
同様の個数及びパターンに形成されているが、ゲート電
極２２は上述した小孔１４がなく、連続層として形成さ
れている。従って、ゲート電極２２を上述の例のように
加工する必要はないが、製造プロセスを部分的に変更す
ることを要する。例えば、島状領域１３をまず拡散形成
（このときソース及びドレイン領域も同時に拡散形成し
てよい。）した後、ポリシリコンゲート２２をゲート電
極形状に加工する。According to this example, the island regions 13 are formed in the same number and pattern as in the above example (FIG. 2), but the gate electrode 22 is formed as a continuous layer without the small holes 14 described above. There is. Therefore, it is not necessary to process the gate electrode 22 as in the above example, but it is necessary to partially change the manufacturing process. For example, the island-shaped region 13 is first diffused (at this time, the source and drain regions may be simultaneously diffused), and then the polysilicon gate 22 is processed into a gate electrode shape.
以上、本発明を例示したが、上述の実施例は本発明の技
術的思想に基づいて種々変更が可能である。Although the present invention has been illustrated above, the above-described embodiment can be variously modified based on the technical idea of the present invention.
例えば、上述の島状領域１３の形状、パターン、配列は
様々に変更してよい。また、電気的にフローティング状
態にする以外に、第５図に破線１７で示す如くに延長
し、両島状領域を一体にして共通に一定の電圧を印加し
てもよい。例えば、基板に対して逆バイアスの電圧を印
加すれば、上述した空乏層１５の伸びを更にコントロー
ルでき一層の高耐圧下を期待できる。第４図及び第５図
の如き例においては、島状領域１３はドレイン側にのみ
形成してもよい（ソース側には必ずしも形成しなくてよ
い）。なお、上述の各領域の導電型を変換することがで
きる。For example, the shape, pattern, and arrangement of the island regions 13 described above may be variously changed. In addition to the electrically floating state, it may be extended as shown by the broken line 17 in FIG. 5 so that both island regions are integrated and a constant voltage is commonly applied. For example, if a reverse bias voltage is applied to the substrate, the extension of the depletion layer 15 described above can be further controlled, and a higher breakdown voltage can be expected. In the example shown in FIGS. 4 and 5, the island region 13 may be formed only on the drain side (not necessarily on the source side). The conductivity type of each area described above can be changed.
ヘ．発明の作用効果 本発明の絶縁ゲート型電界効果半導体装置の製造方法に
おいては、上述の如く、ソース領域、、ドレイン領域及
び島状領域をそれぞれセルフアラインに形成できるの
で、島状領域を形成しない従来のこの種半導体装置製造
方法のプロセスを変更することなく本発明の絶縁ゲート
型電界効果半導体装置を製造することができる。F. Advantageous Effects of the Invention In the method for manufacturing an insulated gate field effect semiconductor device of the present invention, since the source region, the drain region and the island region can be formed in self-alignment as described above, the conventional island-shaped region is not formed. The insulated gate field effect semiconductor device of the present invention can be manufactured without changing the process of this type of semiconductor device manufacturing method.
第１図〜第６図は本発明の実施例を示すものであって、 第１図はＭＯＳＦＥＴの要部平面図、 第２図は第１図II−II線に対応する断面図、 第３Ａ図、第３Ｂ図及び、第３Ｃ図はＭＯＳＦＥＴの製
造方法の主たる過程を順に示す各断面図、 第４図、第５図は他の例によるＭＯＳＦＥＴの要部平面
図、 第６図は更に他の例によるＭＯＦＥＴの断面図 である。 第７図、第８図及び第９図は従来のＭＯＳＦＥＴの各断
面図である。 なお、図面に示す符号において、 １……ドレイン領域 ６……ソース領域 １０、１１……電極 １１ａ……電極延設部 １２……チャネル領域 １３……島状領域 １４……小孔 １５……空乏層 １６……不純物イオン ２２……ゲート電極 である。1 to 6 show an embodiment of the present invention. FIG. 1 is a plan view of a main part of a MOSFET, FIG. 2 is a sectional view corresponding to line II-II in FIG. 1, and FIG. FIGS. 3B and 3C are cross-sectional views showing the main steps of the method for manufacturing a MOSFET in order, FIGS. 4 and 5 are plan views of a main part of a MOSFET according to another example, and FIG. 3 is a sectional view of a MOFET according to the example of FIG. FIG. 7, FIG. 8 and FIG. 9 are cross-sectional views of a conventional MOSFET. In the reference numerals shown in the drawings, 1 ... Drain region 6 ... Source region 10, 11 ... Electrode 11a ... Electrode extended portion 12 ... Channel region 13 ... Island region 14 ... Small hole 15 ... Depletion layer 16 ... Impurity ion 22 ... Gate electrode.
Claims (1)
形成する工程と、 前記絶縁膜上に導電膜を形成する工程と、 前記導電膜に対してフォトリソグラフィー及びエッチン
グ処理を施して孔を備えるゲート電極を形成する工程
と、 前記ゲート電極をマスクとして第２導電型の不純物を照
射し、前記ゲート電極が存在しない領域下の前記半導体
基板表面に前記第２導電型の不純物を打ち込んで、前記
ゲート電極の外側に位置する所定の前記半導体基板表面
に第２導電型のソース及びドレイン領域をそれぞれ形成
するとともに前記ゲート電極の孔と対向する前記半導体
基板表面に第２導電型の島状領域を形成する工程と、 を有する絶縁ゲート型電界効果半導体装置の製造方法。1. A step of forming an insulating film on the surface of a semiconductor substrate of the first conductivity type, a step of forming a conductive film on the insulating film, and a photolithography and etching process for the conductive film. Forming a gate electrode having a hole, and irradiating with a second conductivity type impurity by using the gate electrode as a mask, and implanting the second conductivity type impurity on a surface of the semiconductor substrate below a region where the gate electrode does not exist. A second conductivity type source and drain region is formed on a predetermined semiconductor substrate surface outside the gate electrode, and a second conductivity type island is formed on the semiconductor substrate surface facing the hole of the gate electrode. Forming a gate region, and a method for manufacturing an insulated gate field effect semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61005260A JPH0616557B2 (en) | 1986-01-14 | 1986-01-14 | Method for manufacturing insulated gate field effect semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61005260A JPH0616557B2 (en) | 1986-01-14 | 1986-01-14 | Method for manufacturing insulated gate field effect semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62163373A JPS62163373A (en) | 1987-07-20 |
| JPH0616557B2 true JPH0616557B2 (en) | 1994-03-02 |
Family
ID=11606258
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61005260A Expired - Lifetime JPH0616557B2 (en) | 1986-01-14 | 1986-01-14 | Method for manufacturing insulated gate field effect semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0616557B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6672554B2 (en) * | 2001-09-19 | 2004-01-06 | Nifco Inc. | Article storage device and shutter used therein |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49115679A (en) * | 1973-03-07 | 1974-11-05 | ||
| JPS5050878A (en) * | 1973-09-05 | 1975-05-07 |
-
1986
- 1986-01-14 JP JP61005260A patent/JPH0616557B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62163373A (en) | 1987-07-20 |
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