JPH06163719A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To suppress the generation of silicon nodules by providing a laminated structure of pure Al and Al-Si. CONSTITUTION:A contact hole is formed. A thin, pure Al layer 13 and an All-Si layer 14 are sequentially formed on the entire surface. The pure Al layer 13 and the Al-Si layer 14 undergo hot etching at the same time, and a first-layer electrode wiring 5 is formed. Annealing is performed, and the ohmic junction is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a miniaturized contact hole which suppresses the generation of silicon nodules.

[0002]

2. Description of the Related Art In the field of IC, LSI, etc., 1 to 2% by weight of silicon (S
Aluminum silicon containing (i) (Al-Si)
Is often used. However, with the miniaturization of devices, the miniaturization of contact holes for electrical connection between wiring and diffusion regions has progressed, and at present 2.0 mm × 2.0 mm.
A size of mm or less is required. As the miniaturization progresses to this point, as shown in FIG. 6, silicon in the Al-Si electrode (1) epitaxially grows in the contact hole to form a silicon nodule (2), and the grown silicon nodule blocks the contact surface. Therefore, there is a drawback that the contact resistance increases. Particularly in semiconductor integrated circuits, the P-type diffusion region is often set to a lower impurity concentration, so that the contact resistance of the P-type diffusion region becomes more problematic than that of the N-type.

Therefore, for example, Japanese Unexamined Patent Publication No. 01-312868.
As described in Japanese Patent Publication No. JP-A-2003-242242, a silicon metal surface is covered with a barrier metal such as Mo-Si or W-Si between the aluminum electrode (1) and the substrate (3) to cover the silicon crystal surface. It is common practice to prevent the occurrence of

[0004]

However, the use of the barrier metal requires a facility (sputtering device, etc.) dedicated to the barrier metal, and the process becomes complicated due to the poor selectivity with respect to silicon, resulting in high cost. There was a flaw.
Therefore, a method of suppressing the generation of silicon nodules while mainly using aluminum has been desired.

[0005]

The present invention has been made in view of the above-mentioned conventional drawbacks. After forming a contact hole, first, a pure frame aluminum layer containing no silicon is formed, and then a silicon layer is formed thereon. By forming a layer of aluminum and silicon containing silicon, and photoetching both at the same time to form the first-layer electrode wiring of the laminated structure, and annealing the wafer to form all ohmic electrodes, a structure mainly composed of aluminum is formed. Provided is a method for manufacturing a semiconductor device in which generation of silicon nodules is suppressed.

[0006]

According to the present invention, the pure frame Al layer (13) is brought into contact with the silicon crystal plane in the contact hole (12), and Si
Al-S containing silicon as a raw material of nodules (2)
The i layer (14) is on the pure frame Al layer (13). Therefore, in order for the silicon atoms of the Al-Si layer (14) to deposit as Si nodules (2) during annealing, the pure frame Al layer (13) must be diffused, and the same annealing treatment is performed. However, in the case of the present application, the amount of precipitation is smaller due to the diffusion lime lag. Further, if the film thickness is the same, the total amount of silicon atoms existing on the contact hole (12) is reduced, so that the amount of precipitation can be reduced.

[0007]

An embodiment of the present invention will be described in detail below with reference to the drawings. First, referring to FIG. 1, the surface of a substrate (10) on which a large number of P-type or N-type diffusion regions are formed for forming a circuit element is covered with a silicon oxide film (11), and a normal photoresist using a photoresist is used. Contact hole (12) in silicon oxide film (11) by etching process
To form. The P-type or N-type diffusion region is exposed in the contact hole (12). The substrate (10) may be an epitaxial layer such as BIP-IC.

The etching of the silicon oxide film is performed by a hydrofluoric acid buffer solution (buffer hydrofluoric acid) or reactive ion etching (RIE). In the actual process, the substrate is washed with water and dried after etching, and exposed to air until the next process is performed. Therefore, several tens of liters of natural oxide film is formed on the silicon surface in the contact hole (12), and if it remains as it is, it will become an obstacle to ohmic contact. To do. The pre-etching is performed by etching with a hydrofluoric acid buffer solution for several tens of seconds, and then washing with water and drying are performed again.

Referring to FIG. 2, a pure frame Al layer (13) containing no silicon is deposited on the entire surface of the wafer immediately after pre-etching so that a natural oxide film does not grow. The film thickness is 0.1 to 0.3 μm. Referring to FIG. 3, 1 to 2 of silicon is formed on the entire surface of the pure frame Al layer (13).
An Al-Si layer (14) containing wt% is similarly deposited by the sputtering method. The film thickness is 1.0 to 1.2 μm.

Referring to FIG. 4, a photoresist is applied on the Al-Si layer (14), the pattern is exposed and developed using a photomask, and a pure frame Al layer (13) and an Al-Si layer (14) are formed. ) And are simultaneously etched to form the first-layer electrode wiring (15). This first layer electrode wiring (1
5) constitutes all ohmic electrodes in contact with the silicon surface. After the formation of the first-layer electrode wiring (15), if necessary, the formation of the interlayer insulating film and the formation of the second-layer electrode wiring are continued, but the second-layer and the subsequent layers have the Al-Si single layer structure.

At the final stage of the manufacturing process, 4
By performing annealing treatment at 00 ° C. for several hours, ohmic contact between the first layer electrode wiring (15) and the silicon surface is obtained. In the above annealing treatment, the silicon crystal plane is exposed in the contact hole (12) and the silicon atom is present in the Al-Si layer (14) of the first-layer electrode wiring (15). Silicon atoms are deposited in the holes (12) to form silicon nodules. However, in order for silicon atoms to be deposited, the silicon atoms in the Al-Si layer (14) play a part in pure frame Al.
After the layer (13) is diffused, the diffusion time becomes a time lag. Therefore, even if the annealing treatment is performed for the same time as the conventional example, the present invention can reduce the amount of precipitation. In addition, if the film thickness of the first-layer electrode wiring (15) and the silicon concentration of the Al-Si layer (14) are the same as those of the conventional example, the present invention is concerned with the electrode wiring because the pure frame Al layer (14) is present. It is equivalent to lowering the silicon concentration of. The deposition amount of silicon nodules is equal to the total amount of silicon atoms existing on the contact holes (12), and therefore the deposition amount of the present invention can be reduced by the amount corresponding to the reduction of the silicon concentration.

The silicon of the Al-Si layer (14) is
It is more advantageous than pure frame Al in terms of workability during etching, so-called cracking, while suppressing the generation of alloy spikes. Therefore, the silicon concentration of the Al-Si layer (14) cannot be lowered below a certain value. The present application describes a pure frame Al layer (1
Since the film thickness of 3) is extremely thin, 0.1 to 0.2 μm, the silicon concentration does not drop below the required level, and the thin film thickness does not deteriorate the workability of etching.

FIG. 5 is a diagram comparing the contact resistance and the variation thereof between the conventional method and the present application. The size of the contact hole (12) is 1.6 μ × 1.6 μ, and the conventional method is a normal process using only Al—Si without using via metal. Specifically, the N-type contact is the emitter of the NPN transistor or the source / drain region of the N-channel MOS transistor, and the P-type contact is the source / drain region of the P-channel MOS transistor. Due to the high impurity concentration and the barrier height, the N-type contact has no great difference in contact resistance and variation. However, the burying of contact holes due to silicon nodules that was sometimes seen in the conventional method was not observed at all. Compared with P-type contact, the contact resistance is 8
A decrease of 15Ω from 6.0Ω to 70.7Ω was observed, and the variation (δ / x) in contact resistance was significantly improved from 33.4% to 21.1%. Of course, the contact holes were not buried by the silicon nodules.

As described above, according to the present invention, by suppressing the generation of silicon nodules (2), good contacts for both P-type and N-type can be stably obtained without variation. Incidentally, JP-A-56-23774 discloses an electrode structure in which a pure Al layer and an Al-Si layer are laminated, but this is an improvement only in the Schottky junction portion.
Unlike the present application, not all ohmic electrodes have a laminated structure.

[0015]

As described above, according to the present invention, there is an advantage that the deposition of silicon nodules can be suppressed and the contact resistance and its variation can be greatly improved. Moreover, since the most common materials such as Al and Al-Si are used without using a special metal such as a barrier metal, there is an advantage that the manufacturing process is not so complicated.

[Brief description of drawings]

FIG. 1 is a first sectional view for explaining the present invention.

FIG. 2 is a second cross-sectional view for explaining the present invention.

FIG. 3 is a third sectional view for explaining the present invention.

FIG. 4 is a fourth sectional view for explaining the present invention.

FIG. 5 is a diagram for comparing the present application and a conventional example.

FIG. 6 is a cross-sectional view for explaining a conventional example.

Claims (1)

[Claims] 1. A step of forming a contact hole in an insulating film covering a surface of a semiconductor region, and a step of covering the surface of the semiconductor region exposed in the contact hole with a pure frame aluminum layer containing no silicon, A step of covering the pure aluminum layer with an aluminum / silicon layer containing silicon, and a step of photoetching the aluminum layer and the aluminum / silicon layer simultaneously to form a first-layer electrode wiring; A method of manufacturing a semiconductor device, comprising the step of annealing the above to form all ohmic electrodes of the chip.