JPH05283408A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a manufacturing method of a semiconductor device which has a process capable of forming an interlayer insulating film excellent in flatness without damaging a substrate even in the case of a fine element. CONSTITUTION:The title manufacturing method is constituted of the following; a process for forming a wiring layer 3 on a semiconductor substrate 1, a process for forming a silicon nitride layer 4 on the wiring layer 3, a process for etching the wiring layer 3 by using the silicon nitride layer 4 as a mask, a process wherein the semiconductor substrate 1 is dipped in a supersaturated solution of SiO2 and an SiO2 film is selectively grown on a region of the substrate except the silicon nitride layer 4, and a process for eliminating the silicon nitride layer 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an interlayer insulating film, laminated wiring and the like.

[0002]

2. Description of the Related Art In recent years, large-scale integrated circuits formed by integrating a large number of transistors, resistors, etc., on a single chip on important parts of a computer or communication equipment so as to achieve an electric circuit ( LSI) is widely used. Therefore, the performance of the entire device is largely linked to the performance of the LSI alone.

The performance of the LSI itself can be improved by increasing the degree of integration, that is, by miniaturizing the elements. However, the miniaturization of the device has the following problems.

That is, as shown in FIG. 14A, when the interlayer insulating film 284 is deposited on the semiconductor substrate 281 on which the Al wiring 283 is formed via the silicon oxide film 282, A
Since the space between the 1 wirings 283 is narrow, a void 285 is generated, and there is a problem that reliability is reduced.

Further, since the interlayer insulating film 284 is not flat, there is a problem that a focus error of exposure occurs in a photolithography process which is a post-process and it becomes difficult to perform accurate film processing.

The above-mentioned problem can be solved to some extent by using etch back, but in this case, a new problem that the process is complicated occurs.

Further, the following problems also make it difficult to miniaturize the device.

As shown in FIG. 14B, the lower layer wiring 29
The lower wiring 293 may be etched by over-etching when an opening is formed in the interlayer insulating film 294 by etching in order to make contact with 3.

That is, the lower layer wiring 29 is provided through the insulating film 292.
On the semiconductor substrate 291 on which the interlayer insulating film 29 is formed.
4 is deposited, a photoresist pattern is formed thereon, and the interlayer insulating film 294 is etched using this as a mask.

The interlayer insulating film 294 is preferably flat, but is influenced by the lower layer wiring 293. For this reason,
In order to form a flat film, the interlayer insulating film 294 needs to be formed as a thick film. As a result, the etching amount increases, and the lower layer wiring 293 is also etched.

If the photoresist pattern is displaced, the insulating film 292 in the lower layer of the lower wiring 293 is also etched as shown in FIG. 14C. To prevent this, the alignment margin, that is, the lower layer wiring 293.
However, it is difficult to miniaturize the device.

Further, it is necessary to form element isolation regions of various widths with the miniaturization of elements. When the conventional method, for example, the groove burying method is used, all the trenches are equally filled with the insulating film. There was a problem that it was difficult.

[0013]

As described above, in the conventional method of manufacturing a semiconductor device, when the element is miniaturized, a void is generated in the formation of the interlayer insulating film, or the upper wiring is formed. There are problems that the lower layer wiring is etched and it is difficult to form element isolation regions of various widths. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a semiconductor device capable of miniaturizing an element without inviting a complicated manufacturing process. is there.

[0014]

The essence of the present invention is to utilize the selective growth of an insulating film in a liquid phase.

That is, in order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention (claim 1) comprises a step of forming a metal film on a substrate and a step of forming a metal film on the metal film in a liquid phase. A step of forming a mask pattern on which a predetermined insulating film does not grow, a step of etching the metal film using this mask pattern as a mask, and a predetermined insulating layer on the substrate in a region other than the mask pattern in the liquid phase. The method is characterized by comprising a step of selectively growing a film and a step of removing the mask pattern.

Another method of manufacturing a semiconductor device according to the present invention (claim 2) includes a step of forming a first metal wiring on a substrate and a predetermined insulating film in a liquid phase on the metal wiring. Forming a mask pattern that does not grow, a step of selectively growing a predetermined insulating film on a substrate in a region other than the mask pattern in a liquid phase, and removing the mask pattern to form an opening. And then forming a second metal wiring by burying a wiring material in the opening.

According to another method of manufacturing a semiconductor device of the present invention (claim 3), a step of forming a mask pattern on a substrate in which a predetermined insulating film does not grow in a liquid phase, and the mask pattern. Is used as a mask to form a groove by etching the substrate, a step of selectively growing a predetermined insulating film in the groove in a liquid phase, and a step of removing the mask pattern. It is characterized by

Another method of manufacturing a semiconductor device according to the present invention (claim 4) comprises a step of forming a mask pattern on a substrate in which a predetermined insulating film does not grow in a liquid phase, and a step of forming a mask pattern in the liquid phase. A step of selectively growing a predetermined insulating film on the substrate in regions other than the mask pattern; and a step of forming a semiconductor film on the substrate in the region of the mask pattern after removing the mask pattern. It is characterized by having.

[0019]

According to the method of manufacturing a semiconductor device of the present invention, a mask pattern which does not grow a predetermined insulating film in a liquid phase is formed on a substrate, and then a predetermined insulating film is selectively grown in the liquid phase. , Remove the mask pattern.

Therefore, if a substrate on which a metal film having wiring as the uppermost layer is deposited is selected as the substrate subjected to the desired treatment, the metal film is etched using the mask pattern as a mask and then predetermined in the liquid phase. By selectively growing the insulating film, and then removing the mask pattern, an interlayer insulating film having excellent flatness can be obtained without etching back the insulating film to be the interlayer insulating film. Further, even if the space between the wiring layers is narrowed, it is possible to prevent the generation of voids in the interlayer insulating film because the selective growth is used.

Further, as a substrate subjected to desired processing,
After selecting a substrate having a wiring layer as the uppermost layer and forming a mask pattern on the wiring layer, selective growth of a predetermined insulating film is performed in a liquid phase, and thereafter, if the mask pattern is removed, The through hole can be formed without etching the insulating film serving as the interlayer insulating film. Therefore, the problem that the wiring layer is etched does not occur. Further, if the mask pattern is formed by using the photolithography technique, the dimensional accuracy of the opening is determined by the photoresist patterning accuracy. Therefore, since it is not necessary to consider the etching accuracy, a finer through-hole can be formed as compared with the conventional method using etching.

Further, in the present invention (claim 4), a mask pattern which does not allow a predetermined insulating film to grow in a liquid phase is formed on a substrate, and the substrate is etched by using this mask pattern as a mask to separate elements. Since the groove to be the region is formed and the predetermined insulating film is selectively grown in the liquid phase, the inside of the groove can be filled with the insulating film. Therefore, since it is not necessary to etch back the insulating film to be the insulating film for element isolation, there is no problem that the substrate is damaged during the formation of the element isolation region, and the process is simplified.

Further, according to the present invention (claim 5), a mask pattern is formed after a predetermined insulating film is selectively grown in a liquid phase.
Then, the semiconductor film is removed and a semiconductor film is formed over the substrate in that region, so that a substrate having the same structure as when the groove is filled with the insulating film is obtained. Furthermore, since it is not necessary to form a groove by etching the substrate, the substrate damage can be reduced.

[0024]

Embodiments will be described below with reference to the drawings.

FIG. 1 is a sectional view of a forming process showing a method of forming an interlayer insulating film according to the first embodiment of the present invention.

First, as shown in FIG. 1A, after a silicon oxide film 2 is formed on a semiconductor substrate 1, a wiring layer 3 is deposited thereon. Next, a silicon nitride layer 4 on the entire surface
After depositing a photoresist, a photoresist is applied thereon, and then exposure and development are performed to leave the photoresist only in the wiring region. Then, using this photoresist as a mask, the silicon nitride layer 4 is etched, and then the photoresist is removed.

Next, as shown in FIG. 1B, the wiring layer 3 is etched using the silicon nitride layer 4 as a mask.

Next, as shown in FIG. 1C, the semiconductor substrate 1
Is immersed in a supersaturated solution of SiO ₂ to form an SiO ₂ film 5 as an interlayer insulating film on the silicon oxide film 2. SiO
_As the supersaturated solution of ₂ , SiO ₂ which is supersaturated with a silicified hydrofluoric acid solution is used. The film forming temperature may be room temperature. Since SiO ₂ does not grow on the silicon nitride layer 4 in a supersaturated solution of SiO ₂ , the SiO ₂ film 5 selectively grows on the silicon oxide film 2.

Next, when the film thickness of the SiO ₂ film 5 becomes the same as that of the wiring layer 5, the semiconductor substrate 1 is taken out from the supersaturated solution of SiO ₂ . Finally, as shown in FIG. 1D, the silicon nitride layer 4 is removed, and the step of forming the interlayer insulating film is completed.

According to the method described above, since SiO ₂ grows on the silicon oxide film 2 to form the SiO ₂ film, no void is generated even if the space between the wiring layers 3 is narrowed due to miniaturization. Further, Si is formed on the silicon nitride layer 4.
Since O ₂ does not grow, the silicon nitride layer 4 can be easily removed, and the surface can be planarized without complicating the manufacturing process.

Thus, according to the present embodiment, even if the element is miniaturized, it is possible to obtain an interlayer insulating film having no void and a flat surface.

In this embodiment, the silicon nitride layer 4 is formed by using a photoresist pattern, but it may be formed by a photoresist by using a direct photolithography process. In this embodiment, after the silicon nitride layer 4 is formed, the photoresist pattern is peeled off and the process proceeds to the next step. However, the photoresist pattern may be peeled off to the next step. In this case, the peeling of the photoresist pattern is performed, for example,
This is performed simultaneously with the removal of the silicon nitride layer 4. A photoresist may be used instead of the silicon nitride layer 4.

FIG. 2 is a sectional view of a forming process showing a method for forming an interlayer insulating film according to the second embodiment of the present invention.

First, as shown in FIG. 2A, a silicon oxide film 22 is formed on a semiconductor substrate 21, and an Al film to be a wiring layer 23 is deposited on the silicon oxide film 22. Then, a photoresist pattern 2 for a wiring layer is formed on the Al film.
4 is formed, and the Al film is etched using this as a mask to form the wiring layer 23.

Next, as shown in FIG. 2B, after removing the photoresist pattern 24, the semiconductor substrate 21 is immersed in a strong acid solution, for example, concentrated nitric acid, for surface modification of the wiring layer 23. Then, a passivation layer (Al ₂ O ₃ ) is formed on the surface of the wiring layer 23.
25 is formed.

[0036] Finally, as shown in FIG. 2 (c), by immersing the semiconductor substrate 21 in the SiO ₂ of the supersaturated solution, the SiO ₂ film 26 to the wiring layer 23 is an interlayer insulating film on the silicon oxide film 22 Deposit to the same thickness. Here, since the passivation layer 25 has a property that SiO ₂ does not grow,
The O ₂ film 26 selectively grows on the silicon oxide film 22. The passivation layer 25 also plays a role of protecting the wiring layer 23 from acid.

According to the method described above, voids do not occur even if the space between the wiring layers 23 becomes narrow due to miniaturization for the same reason as in the previous embodiment. In addition, in this embodiment, the wiring layer 2
Since the passivation layer 25 is formed on the surface of the wiring layer 23 instead of forming the silicon nitride layer on the surface of the wiring layer 3, the step of removing the silicon nitride layer is eliminated, and the interlayer insulating film can be formed by a simpler process.

Thus, according to this embodiment, similarly to the previous embodiment, even if the element is miniaturized, an interlayer insulating film having no void and a flat surface can be obtained.

Although the passivation layer 25 is formed on the entire surface of the wiring layer 23 in this embodiment, the passivation layer 25 may be formed only on the side portion of the wiring layer 23.

That is, under the condition that the resistance of the photoresist pattern 24 can be maintained, the passivation layer 25 is formed only on the side portion of the wiring layer 23.
After formation, thereby forming a SiO ₂ film 26 by immersing the semiconductor substrate 21 in the SiO ₂ of the supersaturated solution. And S
When the semiconductor substrate 21 is taken out of the supersaturated solution of iO _{2 and} the photoresist pattern 24 is peeled off, an interlayer insulating film having a structure as shown in FIG. 1D is obtained. As a reforming method in this case, annealing in nitrogen plasma can be used. Further, when the wiring layer 23 is etched, the wiring layer 2
It is also possible to use an etching component that is deposited on the side of 3.

In this embodiment, the semiconductor substrate 21 is immersed in a strong acid solution to form the passivation layer 25 on the surface of the wiring layer 23 for surface modification of the wiring layer 23.
The tungsten film may be deposited only on the surface of the wiring layer 23 by using the D method. Although Al is used as the material of the wiring layer 23, copper may be used instead. As a modification method in this case, there is a method of depositing gold on the surface of the copper wiring by a plating method. Further, when copper containing titanium is used as the wiring layer material, the surface of the copper wiring layer can be converted into titanium nitride by anneal in a nitrogen atmosphere for modification. The point is that the surface of the wiring layer should be modified so that the wiring layer does not elute with the supersaturated solution of SiO ₂ .

FIG. 3 is a sectional view of a forming process showing a method of forming an interlayer insulating film according to the third embodiment of the present invention.

This embodiment relates to a method of forming a wiring layer when it is not dissolved in a supersaturated solution of SiO ₂ .

First, as shown in FIG. 3A, a metal film made of tungsten, polysilicon, or the like to be the wiring layer 33 is deposited on the semiconductor substrate 31 via the silicon oxide film 32, and then a photoresist pattern is formed. 34 is formed, and the metal film is etched using this as a mask to form the wiring layer 33.

Next, as shown in FIG. 3B, the semiconductor substrate 3
1 was immersed in a supersaturated solution of SiO _2, selectively growing a SiO ₂ film 35 an interlayer insulating film on the silicon oxide film 32. Here, as with the silicon nitride layer, during a supersaturated solution of SiO _2, photoresist pattern - on down 34, SiO ₂ does not grow.

Finally, as shown in FIG. 3C, the photoresist pattern 34 is removed to complete the step of forming the interlayer insulating film.

The method described above can also achieve the same effect as that of the previous embodiment, and moreover, the material of the wiring layer 33 is SiO 2.
_{Since a} metal that does not dissolve in the supersaturated solution of ₂ is used, there is no need to form a passivation layer.

FIG. 4 is a sectional view of a forming process showing a method of forming an interlayer insulating film according to the fourth embodiment of the present invention.

First, as shown in FIG. 4A, a silicon oxide film 42 is formed on a semiconductor substrate 41, and then a thin film to be a thin wiring layer 43a is deposited on the silicon oxide film 42. Examples of the material of the thin film include polysilicon, copper, tungsten and the like. Next, a photoresist pattern 44 is formed on this thin film, and the thin film is etched using this as a mask to form a thin wiring layer 43a.

Next, as shown in FIG. 4B, the semiconductor substrate 4
1 was immersed in a supersaturated solution of SiO _2, it is selectively grown by a desired thickness of the SiO ₂ film 45 an interlayer insulating film on the silicon oxide film 42.

Next, as shown in FIG. 4C, after removing the photoresist pattern 44, as shown in FIG.
Using the thin wiring layer 43a as a seed, a thick wiring layer 43b is selectively formed on the thin wiring layer 43a to close the opening formed by peeling the photoresist pattern 44. The method for forming the thick wiring layer 43b includes the following methods.

That is, when the thin wiring layer 43a is made of polysilicon, the thick wiring layer 43b is selectively formed on the thin wiring layer 43a by the epitaxial growth method.

When the thin wiring layer 43a is made of copper, a thick wiring layer 43b made of copper or gold is selectively formed on the thin wiring layer 43a by a plating method.

When the thin wiring layer 43a is made of tungsten, the thin wiring layer 43 is formed by the selective CVD method.
A thick wiring layer 43b made of tungsten, copper or aluminum is selectively formed on a.

Also by the method described above, it is possible to obtain an interlayer insulating film having no voids or steps even if the element becomes fine, and it is possible to prevent the deterioration of the reliability of the device.

In the above first to fourth embodiments, the case of forming the interlayer insulating film has been described. However, the present invention is directed to element isolation, contact holes, via holes, and gates of MOS transistors. It can also be applied to the formation of the emitter of a bipolar transistor.

5 and 6 are sectional views of a forming process showing a method of forming a laminated wiring according to the fifth embodiment of the present invention.

First, as shown in FIG. 5A, the lower wiring 53 is formed on the semiconductor substrate 51 with the interlayer insulating film 52 interposed therebetween.

Next, as shown in FIG. 5B, the lower wiring 53
To protect the
A thin insulating film 54 made of SiO ₂ having a thickness of 00 nm or less is deposited on the entire surface.

Next, as shown in FIG. 5C, a photoresist is applied to the entire surface, and then a through-hole is used as a photomask.
Exposure is carried out using a reverse pattern of the pattern, and then development is carried out to form a photoresist pattern 55. After that, the photoresist pattern 55 is modified if necessary. As a modification method, a photoresist pattern 5 is used.
There are a method of making the surface of No. 5 hydrophobic and a method of removing impurities on the surface of the photoresist pattern 55.

Next, as shown in FIG. 6A, the semiconductor substrate 5
1 is immersed in a supersaturated solution of SiO ₂ to form a thin insulating film 5
An SiO ₂ film 56, which is an interlayer insulating film, is selectively grown on the film 4 to a desired thickness.

Next, as shown in FIG. 6B, after removing the photoresist pattern 55, the exposed thin insulating film 54 is removed by anisotropic etching. At this point, the through-hole forming process is completed.

Finally, as shown in FIG. 6C, a metal material is embedded in the through hole to form the upper wiring 57.
As the metal material, Al, Au, Cu, W, Zn, N
Materials such as i, Co, Pd, Ti and Si, and combinations of these materials can be used. As the embedding method, there are a selective CVD method, an electroless plating method, a combination of a sputtering method and an etch back, and the like. The upper layer wiring 56 may have a single layer structure or a laminated structure.

According to the method described above, since SiO ₂ is selectively grown on the thin insulating film 54 to form the SiO ₂ film, even if the space between the lower layer wirings 53 becomes narrow due to miniaturization,
That is, even if the aspect ratio is high, Si without voids
An O ₂ film 56 is obtained. Further, since the through hole can be formed by peeling off the photoresist pattern 55, the lower layer wiring 53 is etched by the over etching of the insulating film which becomes the interlayer insulating film as in the conventional method. There is no problem with being. Moreover, since the number of etching processes is reduced, the manufacturing process can be simplified.

In this embodiment, the dimensional accuracy of the through hole is determined by the photoresist patterning accuracy. Therefore, since it is not necessary to consider the etching accuracy, a finer through-hole is required as compared with the conventional method using etching.
A hole can be formed. In addition, as shown in FIG.
Even if the position of the photoresist pattern 55 is displaced, the through hole can be formed by removing the photoresist pattern 55. Therefore, as shown in FIG.
7 can be formed. Therefore, the alignment margin becomes unnecessary, and the miniaturization and integration of the multilayer wiring can be improved.

FIGS. 8 and 9 are sectional views of a forming process showing a method of forming a laminated wiring according to the sixth embodiment of the present invention.

First, as shown in FIG. 8A, a gate insulating film 63, a gate electrode 64, and a source are formed in an element forming region of a semiconductor substrate 61 surrounded by an insulating film 62 for element isolation. -The drain diffusion layer 65 is formed. After that, in order to protect the base, for example, a thin insulating film 66 made of a SiO ₂ film having a thickness of 100 nm or less is formed by using a sputtering method or a CVD method.
To form.

Next, as shown in FIG. 8B, a photoresist is applied on the entire surface, and a through-hole is used as a photomask.
Exposure is carried out using a reverse pattern of the pattern, and then development is carried out to form a photoresist pattern 67. Then, the semiconductor substrate 61 is dipped in a supersaturated solution of SiO ₂ to form an SiO ₂ film 6 which is an interlayer insulating film on the thin insulating film 66.
8 is selectively grown to the desired thickness.

Next, as shown in FIG. 8C, after the photoresist pattern 67 is peeled off, the exposed thin insulating film 66 is removed.
Is removed using anisotropic etching to form a through hole. Then, a metal material is embedded in the through hole to form the first layer wiring 69.

After removing the photoresist pattern 67 and before embedding the metal material, a heat treatment at 300 to 900 ° C. in a vacuum is performed to remove the water content of the SiO ₂ film 68, if necessary. May be.

Next, as shown in FIG. 9A, a thin insulating film 70 is formed to protect the lower layer, and then the thin insulating film 7 is formed.
After a photoresist is applied on the photoresist layer 0, a photoresist pattern 71 is formed by using a photolithography technique to remove the photoresist except for the region to be the second layer wiring.

Next, as shown in FIG. 9B, the semiconductor substrate 6
1 is immersed in a supersaturated solution of SiO ₂ to form a thin insulating film 7
A SiO ₂ film 72 is selectively deposited on the SiO. Then, after removing the photoresist pattern 71, the exposed thin insulating film 70 is removed to form a through hole. Then, a metal material is embedded in the through hole and the second layer wiring 73 is formed.
To form.

By repeating the above steps, for example, by repeating the process two more times, an element having a four-layer wiring structure as shown in FIG. 9C is obtained. In the figure, 76 and 79 are the third layer wiring and the fourth layer wiring, 74 and 77 are thin insulating films, and 75 and 78 are SiO ₂ films.

According to the method described above, a desired number of laminated wirings connected to the source / drain diffusion layer 65 through the fine holes can be easily formed.

FIG. 10 is a sectional view of a forming process showing a method of forming an element isolation region according to the seventh embodiment of the present invention.

First, as shown in FIG. 10A, a photoresist pattern 82 covering the element region is formed on the Si substrate 81, and the Si substrate 81 is etched using this as a mask to form a groove to be an element isolation region. To form.

Next, as shown in FIG. 10B, the Si substrate 8
1 is immersed in a supersaturated solution of SiO ₂ , and a SiO ₂ film 83, which is an insulating film for element isolation, is selectively deposited in the groove to fill the groove. You can selectively depositing SiO ₂ film 83 in the groove, during the supersaturated solution of SiO _2, because SiO ₂ does not grow on the photoresist.

Finally, as shown in FIG. 10C, the photoresist pattern 82 is peeled off to complete the element isolation region forming step.

According to the method described above, the SiO ₂ film 83 can be embedded in the trench without the etching back step of the insulating film, so that the Si region corresponding to the element region is isolated at the time of element isolation.
There is no problem that the substrate 81 is damaged,
Moreover, the formation process can be simplified.

On the other hand, in the conventional method, as shown in FIG. 11A, after the insulating film 84 for element isolation is deposited on the entire surface of the Si substrate 81 in which the groove is formed, it is etched into the groove by the etch back method. Since the insulating film 84 is buried, the Si substrate 81 is damaged at the time of etch back, which causes a problem in reliability. For example, when a high-concentration diffusion region such as a source / drain diffusion layer is formed, if the Si substrate 81 is damaged,
Occurrence of a leak current, a decrease in withstand voltage, etc., reduce the reliability of the device.

In the above-mentioned conventional method, if the widths of the grooves are different,
Since the film thickness of the insulating film 84 of the wide groove is thinner, a step is generated, which causes a defect such as a disconnection or a short circuit of the wiring.
Reliability is reduced.

On the other hand, according to the method of this embodiment, the groove can be filled with the SiO ₂ film having a uniform film thickness, so that the deterioration of reliability due to the above-mentioned cause can be prevented.

Thus, according to this embodiment, it is possible to form element isolation regions of various widths without causing substrate damage or steps, thereby improving reliability.

FIG. 12 is a sectional view of a forming process showing a method of forming an element isolation region according to the eighth embodiment of the present invention.

[0085] First, as shown in FIG. 12 (a), the surface of the Si substrate 91 to form a SiO ₂ film 92 by thermal oxidation, followed by, Si ₃ on the SiO ₂ film 92 by CVD N _Four
The film 93 is deposited. Then the Si ₃ N ₄ film 93 a photoresist pattern to cover the element region on - after the formation of the emissions 94, the photoresist pattern - Si ₃ N a down 94 as a mask
_{The 4} film 93, the SiO ₂ film 92, and the Si substrate 91 are etched to form a groove to be an element isolation region.

Next, as shown in FIG. 12B, after removing the photoresist pattern 94, a Si ₃ N ₄ film 93 is deposited on the entire surface by using the CVD method again, and this is etched back to form a groove. Si ₃ N ₄ film 93 is formed on the side wall of the.

[0087] Finally, as shown in FIG. 12 (c), by immersing the Si substrate 91 in a supersaturated solution of SiO _2, selectively depositing SiO ₂ film 95 is an insulating film for element isolation in the groove And fill the groove.

By the method described above, it goes without saying that the same effect as in the previous embodiment can be obtained, and in this embodiment, since the Si ₃ N ₄ film 93 is formed on the side wall of the groove, the side wall of the groove is prevents SiO ₂ film 95 to be grown, it is possible to obtain the SiO ₂ film 95 having more excellent flatness.

FIG. 13 is a sectional view of a forming process showing a method of forming an element isolation region according to the ninth embodiment of the present invention.

First, as shown in FIG. 13A, a photoresist pattern 1 covering the element region is formed on the Si substrate 101.
02 is formed.

Next, as shown in FIG. 13B, the Si substrate 1
01 is immersed in a supersaturated solution of SiO _2, photoresist pattern - on the Si substrate 101 surrounded by the down 102, selectively depositing a SiO ₂ film 103 is an insulating film for element isolation.

Next, as shown in FIG. 13C, the photoresist pattern 102 is peeled off to expose the surface of the Si substrate 101 in the element forming region.

Finally, as shown in FIG. 13D, a selective epitaxial growth method is used to selectively grow Si on the surface of the Si substrate 101 to form the Si film 1 to be an element formation region.
To form 04.

According to the method described above, since it is not necessary to form the groove by etching, the damage of the Si substrate 101 can be further reduced.

The present invention is not limited to the above embodiment. For example, instead of the SiO ₂ film, Ta
An insulating film such as O may be selectively grown in the liquid phase. In addition, various modifications can be made without departing from the scope of the present invention.

[0096]

As described above in detail, according to the present invention, by utilizing the selective growth of the insulating film in the liquid phase, the insulating film to be the interlayer insulating film or the element isolation insulating film is not etched. In addition, since an insulating film such as an interlayer insulating film or an element isolation insulating film can be formed, it is possible to avoid a decrease in reliability due to the etching process.

[Brief description of drawings]

FIG. 1 is a sectional view of a forming process showing a method for forming an interlayer insulating film according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a forming process showing a method for forming an interlayer insulating film according to the second embodiment of the present invention.

FIG. 3 is a sectional view of a forming process showing a method for forming an interlayer insulating film according to the third embodiment of the present invention.

FIG. 4 is a sectional view of a forming process showing a method of forming an interlayer insulating film according to a fourth embodiment of the present invention.

FIG. 5 is a sectional view of a forming process showing a method of forming a laminated wiring according to a fifth embodiment of the present invention.

FIG. 6 is a sectional view of a forming process showing a method of forming a laminated wiring according to a fifth embodiment of the present invention.

FIG. 7 is a sectional view of a forming process showing a method of forming a laminated wiring when a photoresist pattern is displaced.

FIG. 8 is a sectional view of a forming process showing a method of forming a laminated wiring according to a sixth embodiment of the present invention.

FIG. 9 is a sectional view of a forming process showing a method of forming a laminated wiring according to a sixth embodiment of the present invention.

FIG. 10 is a sectional view of a forming process showing a method for forming an element isolation region according to the seventh embodiment of the present invention.

FIG. 11 is a sectional view of a forming process showing a conventional method of forming an element isolation region.

FIG. 12 is a sectional view of a forming process showing a method of forming an element isolation region according to an eighth embodiment of the present invention.

FIG. 13 is a sectional view of a forming process showing the method of forming the element isolation region according to the ninth embodiment of the present invention.

FIG. 14 is a diagram for explaining a conventional problem.

[Explanation of symbols]

1, 21, 31, 41, 51, 61 ... Semiconductor substrate 2,
22, 32, 42 ... Silicon oxide film, 3, 23, 33,
43a, 43b, ... Wiring layer, 4 ... Silicon nitride layer, 5, 26, 35, 45, 56, 68, 72, 75,
78, 83, 92, 95, 103 ... SiO ₂ film, 24,
34, 44, 55, 67, 71, 82, 94, 102 ...
Photoresist pattern, 25 ... Passive layer, 52 ... Interlayer insulating film, 53 ... Lower layer wiring, 54, 62, 66, 70, 7
4, 77, 84 ... Insulating film, 57 ... Upper layer wiring, 63 ... Gate
Gate insulating film, 64 ... Gate electrode, 65 ... Source / drain diffusion layer, 69 ... First layer wiring, 73 ... Second layer wiring, 76 ...
Third layer wiring, 79 ... Second layer wiring, 81, 91, 101 ...
Si substrate, 93 ... Si ₃ N ₄ film, 104 ... Si film.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Masanobu Saito 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Stock company Toshiba Research Institute

Claims (4)

[Claims] 1. A step of forming a metal film on a substrate, a step of forming a mask pattern on the metal film in which a predetermined insulating film does not grow in a liquid phase, and the mask pattern is used as a mask. The method comprises the steps of etching a metal film, selectively growing a predetermined insulating film on a substrate in a region other than the mask pattern in a liquid phase, and removing the mask pattern. And a method for manufacturing a semiconductor device. 2. A step of forming a first metal wiring on a substrate, a step of forming a mask pattern on the metal wiring in which a predetermined insulating film does not grow in a liquid phase, and a step of forming a mask pattern in the liquid phase. A step of selectively growing a predetermined insulating film on the substrate in a region other than the mask pattern; and after removing the mask pattern to form an opening, a wiring material is embedded in the opening to form a second layer. And a step of forming the metal wiring. 3. A step of forming a mask pattern on a substrate in which a predetermined insulating film does not grow in a liquid phase, and the substrate is etched by using this mask pattern as a mask to form a groove serving as an element isolation region. And a step of selectively growing a predetermined insulating film in the groove in a liquid phase, and a step of removing the mask pattern, a method of manufacturing a semiconductor device. 4. A step of forming a mask pattern on a substrate in which a predetermined insulating film does not grow in a liquid phase, and a predetermined insulating film is selected on the substrate in a region other than the mask pattern in the liquid phase. And a step of forming a semiconductor film on the substrate in the region of the mask pattern after removing the mask pattern, the method of manufacturing a semiconductor device.