JPH06163536A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor integrated circuit device in which difference of signal propagation time is reduced between a plurality of input terminals receiving clock signals or the like. CONSTITUTION:In the semiconductor integrated circuit device, a planar wiring 12 is formed while covering input terminals 13. Consequently, redundant wiring between signal input and respective input terminals 13 can be shortened. This constitution reduces difference of signal propagation time between respective input terminals 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having an extremely large number of driving points such as clock signals.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device, there are many wirings having extremely large fan-outs such as clock wirings. Conventionally, as shown in FIG. 6, these wirings include a buffer 11 and an input terminal such as a clock input. 13 and wiring 6
I was connected by 1. Here, a propagation delay occurs in a signal that reaches the input terminal 13 from the buffer 11 via the wiring 61, due to the resistance component of the wiring 61 and the parasitic capacitance, and the signal of the signal is input between the plurality of input terminals 13. There is a time difference in arrival.

In order to eliminate this time difference, a balanced tree type layout wiring method has been conventionally used. An example of the above-described conventional layout wiring method will be described below with reference to the drawings.

FIG. 7 shows a layout of clock wiring of a conventional semiconductor integrated circuit in a balanced tree type. In FIG. 7, 11 is a buffer, 13 is an input terminal such as a clock input, 71, 73, 74, 76, 77, 79, 80
Is a wiring, and 72, 75, 78 are branch points for branching the wiring, and the buffer 11 and the input terminal are connected through branch points 72, 75, 78,
The wirings 71, 73, 74, 76, 77, 79, 80 are connected.

In the above structure, the wiring 71 is connected to the branch point 7
It is divided into wirings 73 and 74 by 2. One of the divided wires 73 is again divided into wires 76 and 77 at the branch point 75. Also in the wiring 74, the wiring 7 is again provided at the branch point 78.
It is divided into 9,80. Thereafter, the wiring is divided in the same manner and connected to the input terminal 13. The wiring lengths of the wirings divided from one branch point are made as equal as possible.

By the wiring method described above, the difference in the wiring length from the buffer to each input terminal 13 is reduced, so that the difference in the resistance component and the parasitic capacitance related to the wiring to each input terminal 13 is also reduced, and the propagation time difference is reduced. Also decreases.

[0007]

However, in the above-described conventional layout wiring method, there are many restrictions on the wiring of a highly integrated semiconductor integrated circuit device, and it is difficult to design to eliminate the time difference of signal propagation, and to reduce the time difference. Wiring design is also difficult. In addition, since the number of redundant wiring arrangements increases,
The wiring resistance increases and the propagation delay to the input terminal increases.

To solve the above problems, the present invention easily reduces the propagation time difference to a plurality of input terminals without using complicated wiring, and suppresses the influence of an induced current generated from the wiring on a transistor or the like. A semiconductor integrated circuit device is provided.

[0009]

In order to achieve the above object, the present invention provides a semiconductor integrated circuit device having wiring connected to a plurality of input terminals, the wiring covering a region including a plurality of input terminals. It is provided with a structure of being formed in a planar shape.

Further, a structure is provided in which a planar conductor layer connected to a power source is formed between the above wiring and another wiring layer.

[0011]

With the above-described structure, the present invention can easily shorten the wiring distance to a plurality of input terminals in a semiconductor integrated circuit device having wirings connected to a plurality of input terminals without using a complicated layout wiring method. , Reducing the propagation time difference of the signal input to each of the plurality of input terminals.
Further, it is possible to prevent the influence of the induced current or the like generated from the wiring on the transistor or the like.

[0012]

【Example】

(Embodiment 1) FIG. 1 shows a wiring layout of a semiconductor integrated circuit device showing an embodiment of the present invention, and FIG. 2 is a sectional view taken along line XX 'of FIG.

In FIG. 1, 11 is a buffer, 12 is a wiring, and 13 is an input terminal. The buffer 11 is the wiring 12
It is connected to the input terminal 13 via. The wiring 12 is
It is formed in a planar shape so as to cover the area including the input terminal 13. In FIG. 2, reference numeral 21 denotes a transistor gate, 22
Is an insulator, 23 is a first aluminum layer, 24 is a second aluminum layer,
A transistor 25 includes the input terminal 13, the gate 21 of the transistor, and the like, and is connected to another transistor through the first aluminum layer 23 and the second aluminum layer 24. Figure 1
The input terminal 13 in the inside is the gate 2 of the transistor in FIG.
Connected to 1.

1 and 2, constituent elements having the same functions as those of the conventional semiconductor integrated circuit device are designated by the same reference numerals.

The operation of the semiconductor integrated circuit device configured as described above will be described below with reference to FIGS. 1 and 2.

The signal output from the buffer 11 in FIG. 1 is sent to the input terminal 13 via the planar wiring 12.
The signal input to the input terminal 13 is sent to the gate 21 of the transistor of FIG. 2 and the transistor 25 operates.

When a signal propagates through the planar wiring 12, because of the shape of the wiring, from the connection point between the buffer 11 and the wiring 12 to the input terminal 13, there is a concentric circle with a signal propagation delay due to wiring resistance. Signal propagates to. Therefore,
The signal is propagated from the buffer 11 to the input terminal 13 in the shortest time.

As described above, according to the semiconductor integrated circuit device of the embodiment of the present invention, since the wiring 12 is formed by the surface, the signal propagates from the buffer 11 to the plurality of input terminals 13 in the shortest time. However, it is possible to eliminate redundant routing of wiring as in the case of the semiconductor integrated circuit device of the conventional example shown in FIG. Therefore, compared to the conventional case, each input terminal 13
It is possible to reduce the difference in the propagation time of signals to and from. Further, since the wiring resistance is reduced, the propagation delay is shorter than that in the conventional example.

FIG. 3 shows a layout of a semiconductor integrated circuit device showing an application example of the present invention.

Reference numeral 31 in FIG. 3 denotes a linear wiring, which connects the buffer 11 and the planar wiring 12. Incidentally, 1 in FIG.
The components of the semiconductor integrated circuit device denoted by the numbers 1 to 13 indicate components having the same functions as those in FIG.

In FIG. 3, the linear wiring 31 and the planar wiring 1
By connecting 2 near the center of the semiconductor integrated circuit device, it is possible to reduce the difference in distance from the connection point between the linear wiring 31 and the planar wiring 12 to the plurality of input terminals 13. It is possible to further reduce the time difference required for the signal propagation from the buffer 11 to the plurality of input terminals 13 as compared with the embodiment of FIG.

(Embodiment 2) A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 shows the layout of the semiconductor integrated circuit device showing the second embodiment of the present invention.
FIG. 6 is a sectional view taken along line XX ′ of FIG. 4.

In FIG. 4, 11 is a buffer, 12 is a planar wire, 13 is an input terminal, 12 is a planar wire in FIG. 5, 13 is an input terminal, 21 is a gate of a transistor, 22 is an insulator, Reference numeral 23 is a first aluminum layer, 24 is a second aluminum layer, and 25 is a transistor, which includes the input terminal 13 and the gate 21 of the transistor. The above is shown in FIG. 1 and FIG. 2, respectively.
The configuration is the same as that of.

In FIGS. 4 and 5, the difference from FIGS. 1 and 2 is that the conductor layer 41 grounded to the power supply is connected to the planar wiring 1.
It is inserted between the second aluminum layer 24 and the second aluminum layer 24.

The operation of the semiconductor integrated circuit configured as described above will be described below with reference to FIGS. 4 and 5.

As in the case of the first embodiment, a signal is sent from the buffer 11 to the input terminal 13 via the planar wiring 12.
At this time, the planar wiring 12 generates an induced current or the like depending on the condition of the input signal waveform due to the planar shape, but the conductor layer 41 connected to the power source serves as a shield. The influence of an induced current or the like on the transistor 22 and the wirings 23 and 24 in the layer is prevented.

The present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.

[0029]

As is apparent from the above embodiments, according to the present invention, the following effects can be obtained.

(1) Since the shape of the aluminum wiring is formed by the surface, the signal propagates from the buffer to each input terminal in the shortest distance, and the redundant routing of the wiring can be eliminated. Therefore, it is possible to reduce the difference in the propagation time of the signal to each of the plurality of input terminals as compared with the conventional case.

(2) By providing a grounded conductor layer between the planar wiring and the following layers such as transistors and wiring, the influence of the induced current generated when the signal flows through the wiring is prevented. It is possible to prevent it from reaching layers such as a transistor and an aluminum wiring.

[Brief description of drawings]

FIG. 1 is a wiring layout diagram of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor integrated circuit device according to the same embodiment.

FIG. 3 is a wiring layout diagram of a semiconductor integrated circuit device according to an application example of the first embodiment of the present invention.

FIG. 4 is a wiring layout diagram of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 5 is a sectional view of a transistor of the semiconductor integrated circuit device in the same example.

FIG. 6 is a wiring layout diagram of a conventional semiconductor integrated circuit device.

FIG. 7 is a layout diagram of a wiring of a conventional semiconductor integrated circuit device by a balance tree method.

[Explanation of symbols]

 12-sided wiring 13 Input terminal

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number for FI Technical indication H01L 27/04 D 8427-4M H03K 17/04 9184-5J

Claims (2)

[Claims] 1. A semiconductor integrated circuit device having wiring connected to a plurality of input terminals, wherein the wiring covers a region including the plurality of input terminals and is formed in a planar shape. Semiconductor integrated circuit device. 2. A semiconductor integrated circuit device comprising a planar conductor layer connected to a power supply between a wiring layer forming the wiring according to claim 1 and another wiring layer.