JPH06161796A - Information processor - Google Patents

Abstract

PURPOSE:To provide the information processor equipped with a fault detecting means which enables an early countermeasure for a fault and improves maintainability. CONSTITUTION:Data read out of a memory 2 for data storage are inspected by an ECC circuit 4 which detects and corrects an error bit. When the error is detected, the bit position at the point of the error detection is held in a memory 7 for error information storage, the current frequency of data read instruction from a data processing circuit 1 is counted by a read counter 5 and held in a memory 8 for count information storage, and intervals of error generation and its frequency are known from a difference in the counted value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device,
In particular, the present invention relates to an information processing apparatus having means for detecting a failure of a data bit read from a data storage memory.

[0002]

2. Description of the Related Art Conventionally, a data storage memory, a circuit for instructing the data storage memory to read data bit by bit, and processing the read data, an error detection for the read data bit, and ECC that can be corrected
An information processing device having an (Error Checking and Correction) circuit is known.

In this type of information processing apparatus, when an error is detected, the ECC circuit extracts only the information indicating the position of the error bit, and stores it as failure information in failure information storage means to search for the failure location and It was used for evaluation.

[0004]

In such a conventional information processing apparatus, it is possible to know the error bit position and the failure occurrence frequency, but it is not possible to know the occurrence interval and frequency of each failure. Therefore, it becomes difficult to identify the location of the failure and take early measures against the failure, and improvement is desired.

The present invention has been made under such a background, and an object of the present invention is to provide an information processing apparatus having a failure detecting means capable of detecting a failure occurrence interval and a frequency.

[0006]

In order to achieve the above object, according to the present invention, a data storage memory, a data read instructing means for instructing the data storage memory to read data in bit units, and a reading operation based on the instruction. In an information processing device having an error bit position detection means for monitoring the status of the output data bit and outputting the position information of the error bit when an error is detected, the number of read instructions output from the data read instruction means is cumulatively counted. And the data read number counting means for sequentially outputting the current count information, and the position information of the error bit when the error bit position detecting means detects an error and the count information at this time are stored in association with each other. And means for storing failure information.

In the above structure, the error bit position detecting means has the ECC circuit described above, and the data read number counting means has an initialization circuit for returning the count information to an initial value each time an error is detected. is doing.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. 1 is a data processing circuit (data read instruction means), 2 is a data storage memory, 3 is a check bit storage memory, and 4 is an ECC. Reference numeral 5 denotes a read counter (data read number counting means), 6 denotes an error control circuit, 7 denotes an error information storage memory, and 8 denotes a count information storage memory. Further, a is a read instruction signal, b is an error bit display signal, and c
Indicates an error write instruction signal, and d indicates a read count signal.

When reading the data in the data storage memory 2 from the data processing circuit 1, first, the data processing circuit 1 is read.
Is a data storage memory 2 and a check bit storage memory 3
The read instruction signal a is output to. In response to this instruction, the data is read from the data storage memory 2 and the check bit storage memory 3 bit by bit, sequentially checked by the ECC circuit 4, and if a bit error is detected, it is corrected and sent to the data processing circuit 1.

The read counter 5 cumulatively counts the number of times the data is read from the data storage memory 2 by the read instruction signal a, and outputs the read count signal (count information) a representing the count value to the count information storage memory 8. send.

Further, an error bit display signal (error bit position information) b representing the presence / absence of 1-bit error detection and the bit position in which error is detected in the inspected data is taken out from the ECC circuit 4, and the error control circuit 6 To the error information storage memory 7.

The error control circuit 6 monitors the read instruction signal a and the error bit display signal b, and when an error is displayed on the error bit display signal b while the read instruction signal a is being driven, the error write instruction signal a is displayed. c is driven, and information on the error bit display signal b and the read count signal d is written in the error information storage memory 7 and the count information storage memory 8 by the error write instruction signal c (fault information storage means). .

Next, the manner in which fault information is written in the error information storage memory 7 and the count information storage memory 8 in the above configuration will be described with reference to FIG.

In the first data read, the read counter 5 is incremented to "1". At this time, in the illustrated example, since the inspection by the ECC circuit 4 is normal, writing to the error information storage memory 7 and the count information storage memory 8 is not performed.

In the second data read, the read counter circuit 5 counts up to "2", but the ECC circuit 4
Error was detected by the check by (n1 bit),
An n1 bit error is written in the error information storage memory 7, and a count value "2" is written in the count information storage memory 8, as shown in the figure.

In the third and fourth data reading, the count value of the read counter 5 is incremented to "3" and "4", and the inspection by the ECC circuit 4 is normal. Therefore, the error information storage memory 7 and Writing to the counting information storage memory 8 is not performed.

At the fifth and sixth data reading, the count value of the read counter 5 is incremented to "5" and "6", but an error is detected by the inspection by the ECC circuit 4 (n2 bit, n3). (Bit), n2 bit error, n3 bit error,
Count values "5" and "6" are written in the count information storage memory 8, respectively.

In this way, since the bit position information at the time of error detection and the count value representing the number of read instructions at that time are held in correspondence with each other, at which bit position, at what read instruction interval and frequency. You can know if an error has occurred.

FIG. 3 is a block diagram of the essential parts according to a modification of the above embodiment, showing an example in which an initialization circuit 30 is added to the read counter 5.

This will be described with reference to FIGS. 1 and 3. The initialization circuit 30 writes data to the error information storage memory 7 and the count information storage memory 8 after the driving of the error write instruction signal c is completed. After the completion of loading, the initialization instruction signal e is driven to initialize the cumulative count value of the read counter 5. Other operations are the same as those in the above case.

Next, how the fault information is written in the error information storage memory 7 and the count information storage memory 8 when the initialization circuit 30 is added will be described with reference to FIG.

In the first data read, the count value of the read counter 5 is incremented to "1". At this time, in the illustrated example, since the inspection by the ECC circuit 4 is normal, writing to the error information storage memory 7 and the count information storage memory 8 is not performed.

In the second data read, the count value of the read counter 5 is counted up to "2".
Since an error was detected in the inspection by the C circuit 4 (n1 bit), an n1 bit error was written to the error information storage memory 7, and a count value “2” was written to the count information storage memory 8, and then initialization was performed. The circuit 30 drives the initialization instruction signal e to initialize the read counter circuit 5 (count value "
0 ").

At the third and fourth data reading, the count value of the read counting circuit 5 is incremented by "1" and "2", but since the inspection by the ECC circuit 4 is normal, it is for storing error information. Writing to the memory 7 and the counting information storage memory 8 is not performed.

In the fifth data read, the read counter circuit 5 is counted up to "3" and an error is detected by the inspection by the ECC circuit 4 (n2 bit). Therefore, an n2 bit error is stored in the error information storage memory 7. , The count value “3” is written in the count information storage memory 8, and thereafter,
The initialization circuit 30 drives the initialization instruction signal e to initialize the read counting circuit 5 (count value "0").

In the sixth data read, the count value of the read counter 5 is incremented to "1" and an error is detected by the inspection by the ECC circuit 4 (n3 bit). The bit error and the count value "1" are written in the count information storage memory 8, respectively, and thereafter the initialization instruction signal e is driven by the initialization circuit 30 to initialize the read counter circuit 5 (count value "
0 ").

As described above, since the accumulated count value between the previous error detection time and the bit position information at the time of error detection is held correspondingly, the read instruction interval and the read instruction interval can be confirmed by checking this count value. You can know the frequency immediately. This improves maintainability. Further, since the read counter 5 is initialized every time an error is detected, the above operation can be realized with a small capacity.

[0029]

As described above in detail, according to the present invention, the data bit position at the time of occurrence of a failure, the failure occurrence interval and the frequency thereof can be known, and the failure location can be identified and its early stage. There is an effect that measures can be taken. INDUSTRIAL APPLICABILITY The present invention can be a particularly effective fault detecting means in the case of automatically recovering after a fault occurs, such as an information processing device having an ECC circuit, and the evaluation thereof becomes easy.

Further, since the initialization circuit is added to the data instructing number counting means so that the count value is initialized each time an error is detected, it becomes easy to recognize the failure occurrence interval, the maintainability is improved, and the total maintenance is improved. This has the effect of saving the capacity of the numerical value holding means.

[Brief description of drawings]

FIG. 1 is a block diagram of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a state until failure information is written after data reading and inspection in the configuration of FIG.

FIG. 3 is an explanatory diagram of an initialization circuit used in another embodiment of the present invention.

FIG. 4 is an explanatory diagram showing a state until failure information is written when an initialization circuit is added.

[Explanation of symbols]

 1 ... Data processing circuit 2 ... Data storage memory 3 ... Check bit storage memory 4 ... ECC circuit 5 ... Read counter 6 ... Error control circuit 7 ... Error information storage Memory 8 ... Count information storage memory 30 ... Initialization circuit a ... Read instruction signal b ... Error bit display signal c ... Error write instruction signal d ... Read count signal e ... Initialization instruction signal

Claims (3)

[Claims] 1. A data storage memory, a data read instructing means for instructing the data storage memory to read out data in bit units, a state of a data bit read by the instruction is monitored, and when an error is detected, the error is detected. In an information processing device having an error bit position detecting means for outputting bit position information, a data read number counting means for accumulatively counting the number of read instructions output from the data read instructing means and sequentially outputting current count information. And an error information storage unit that stores the position information of the error bit and the count information at this time in association with each other when the error bit position detection unit detects an error. apparatus. 2. The information processing apparatus according to claim 1, wherein the error bit position detecting means has an ECC (Error Checking and Correction) circuit for correcting the data bit after the position information of the error bit is output. . 3. The data read number counting means further comprises:
The information processing apparatus according to claim 1, further comprising an initialization circuit that returns the count information to an initial value each time an error is detected.