JP2000215111A - Unit and method for memory control - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability while carrying on the operation of a system seamlessly by detecting a fault in its early stage and removing the fault. SOLUTION: When a CPU 10 starts memory access and a cache memory 40 is free, a memory control circuit 50 specifies a cache line of the cache memory 40 to be inspected and takes the data of the specified cache line out of the cache memory 40 to perform inspection.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device and a memory control method for a built-in cache memory.
The present invention relates to a memory control device and a memory control method for autonomously checking data in a cache.

[0002]

2. Description of the Related Art Conventionally, when detecting a fault in a memory, a host device accesses the memory device, reads out actual data, and checks the data. If there is an error in the read data, a memory failure is detected.

In this case, if data with a low access frequency stays in the memory for a long period of time, a failure due to a holding characteristic or the like becomes latent and eventually causes multiple failures. When such multiple failures are induced, the reliability of the entire system is reduced, the service capability is reduced, and the operation of the system cannot be continued.

To solve such a problem, for example, Japanese Patent Application Laid-Open No. 3-59740 discloses a timer circuit for generating a periodic interrupt signal, an error display F / for displaying an error when a memory failure occurs. And an F circuit.

Thus, when an interrupt signal arrives,
The address of the memory is updated, and data in which all bits are set at the address is stored. Thereafter, the data is read out and collated, and the data in which all bits are reset are stored at the same address.

When a memory failure is detected as a result of data collation, an error display is performed by an error display F / F circuit. As a result, failure detection of all bits of all memories is performed, so that a complete memory check can be performed.

In Japanese Patent Application Laid-Open No. 4-86932,
An address bus buffer A disabled by the fetch cycle display signal, a data bus buffer, an address bus buffer B enabled by the fetch cycle display signal, a counter counted up by the fetch cycle display signal, and a fetch cycle display signal AND of chip enable signal of RAM and parity bit holding memory output from decoder
And an AND gate which takes the following.

As a result, a fault is detected by the memory fault detecting circuit during the OP code fetch cycle, so that a potential fault in the RAM can be detected early without lowering the processing capability of the CPU.

[0009]

However, in the former prior art described above, a periodic interrupt signal is used, two unique patterns are used as test data, or the original data before and after the test is used. Since evacuation and recovery processing is required, there is a problem that even in normal system operation, a fixed decrease in service operation is accompanied.

[0010] Further, when a failure occurs, the service is interrupted because the failure is not eliminated.

On the other hand, the latter prior art described above has a problem that it cannot be applied to the memory of the instruction code portion because the inspection method is performed using different addresses during the instruction code fetch.

Further, since the instruction fetch cycle and the data access cycle depend on a specific processor which is clearly separated, there is also a problem that the instruction fetch cycle and the data access cycle are limited to a specific processor. Further, at the time of a failure, since the failure is not eliminated, there is a problem that the service is interrupted as described above.

The present invention has been made in view of such a situation, and a memory control apparatus capable of seamlessly continuing the operation of a system by early detection and elimination of a failure and improving reliability. And a memory control method.

[0014]

According to a first aspect of the present invention, there is provided a memory control device, comprising: a CPU for performing memory access; a bus unit connected to the CPU via a memory bus for internal access; Main memory connected to the bus unit via a memory bus, a cache memory connected to the CPU via a memory bus for internal access, a memory access started by the CPU, and the cache memory is in an empty state. And a memory control circuit for checking data in the cache memory. Also, when a memory access is started by the CPU, if there is no valid address portion, the cache memory
A signal can be generated, and the idle state can be maintained until there is a response from the main memory accessed by the CPU. Further, when the memory control circuit receives the MIS signal, the memory control circuit includes a cache line designating unit that designates a cache line to be inspected in the cache memory, and a data examining unit that extracts data of the designated cache line from the cache memory and performs an inspection. Can be provided. Further, when the data checking means corrects the correctable data in the cache memory, the cache line designation means can write the corrected data back to the cache line. In addition, when the data check unit cannot correct the data in the cache memory, the cache line designating unit eliminates uncorrectable data and notifies the CPU of a failure when a serious failure is detected. You can do so. The memory control method according to claim 6, wherein a first step of performing a memory access of a cache memory or a main storage memory; and a memory access is started;
And a second step of checking data in the cache memory when the cache memory is empty. In the second step, when a memory access is started, if there is no valid address portion, a miss signal is generated, and a free state is kept until a response is received from the main memory to be accessed. Can be included. In the second step, when a MIS signal is received, a third step of specifying a cache line to be inspected in the cache memory, and a fourth step of extracting data of the specified cache line from the cache memory and performing an inspection. And a step of: The fourth step may include a step of correcting correctable data in the cache memory, and the third step may include a step of writing the corrected data back to the cache line. Can be. Further, in the case where data correction of the cache memory is impossible, the third step may include a step of excluding uncorrectable data and notifying a failure. In the memory control device and the memory control method according to the present invention, when memory access is started by the CPU and the cache memory is in an empty state,
The memory control circuit specifies a cache line to be inspected in the cache memory, and retrieves data of the specified cache line from the cache memory to perform the inspection.

[0015]

Embodiments of the present invention will be described below.

FIG. 1 is a block diagram showing an embodiment of the memory control device of the present invention, FIG. 2 is a time chart for explaining the operation of the memory control device of FIG. 1, and FIG. 5 is a flowchart for explaining the operation of the memory control device.

The memory control device shown in FIG.
0, bus unit (BU) 20, main memory (Me)
m) 30, cache memory 40 and memory control circuit 5
0 is provided.

The CPU 10 is connected to a bus unit (BU) 20 and a cache memory 40 via a memory bus.

The memory bus for internal access comprises an address bus 11, a control bus 12, and a data bus 13. Memory buses for external access include an address bus 21, a control bus 22, and a data bus 2.
3 is comprised.

The CPU 10 performs memory access via an address bus 11, a control bus 12, and a data bus 13.

The cache memory 40 stores CTL, dat
a and CHK. The CTL is composed of a plurality of rvd 41 and a plurality of tag 42 as status information. data is a cache of multiple lines
data43. CHK is composed of a plurality of codes 44 corresponding to cachedata 43 of each cache line.

The memory control circuit 50 includes a Det detection circuit 5
1, CHKCTL circuit 52, A_PTRCTR circuit 53
And a CHKer circuit 54. The Det detection circuit 51 outputs the result of the Det detection as a signal 61 to CH
Output to the KCTL circuit 52. Here, the Det detection circuit 51, the CHKCTL circuit 52, and the A_PTRCTR circuit 53 serve as a cache line designation unit. CH
The Ker circuit 54 is a data inspection unit.

When the cache memory 40 receives the access from the memory bus, the cache memory 40 checks the rvd 41 and the tag 42 as the state information held therein.
At this time, the cache memory 40 stores the address bus 11
If you have a valid cache line specified in
A response signal is returned to the CPU 10 via the control bus 12.

The cache memory 40 performs a read or write process on a designated address based on an instruction from the CPU 10. The control instruction at this time is performed via the control bus 12. Input and output of data are performed via the data bus 13. If there is no valid cache line in the cache memory 40,
The MIS signal 60 is output from the cache memory 40.

The cache memory 40 stores a signal 63
Cached cache line specified by
ta43 and the corresponding code44 are output as signals 64 and 65, respectively. Also, remove
When the signal 67 is received, the rvd 41 as the state information specified by the signal 63 is rewritten to the invalid state to eliminate data. Alternatively, rvd41 as the designated state information is marked as remove.

When the bus unit (BU) 20 receives the MIS signal 60 from the cache memory 40, the bus unit (BU) 20 is enabled to access the external memory.

When the memory control circuit 50 receives the MIS signal 60 or the busy signal 69 via the Det detection circuit 51, the memory control circuit 50 activates the CHKCTL circuit 52 to enter an operation state. When the CHKCTL circuit 52 is activated, a signal 62 is output.

The A_PTRCTR circuit 53 outputs the pointer to the cache memory 40 as a signal 63. CH
The Ker circuit 54 receives the cached signal 64
The normality test of the data 43 and the code 44 received as the signal 65 is performed.

The result checked by the CHKer circuit 54 is as follows:
The result signal 66 is reported to the CHKCTL circuit 52.

When the CHKCTL circuit 52 receives this,
Cachedata4 corrected by the CHKer circuit 54
3 and the code 44 are written back by the signal 64 and the signal 65. Alternatively, a remove signal 67 is output. Or a
The alarm signal 68 is output. Further, the CHKCTL circuit 52 updates the pointer of the A_PTRCTR circuit 53 for the next processing, and ends a series of operations started.

Next, the operation of the memory control device having such a configuration will be described with reference to FIGS.

First, the CPU 10 controls the address bus 11,
A control signal is output via the control bus 12 and the data bus 13 to perform memory access. The CPU 10 outputs the control signal ADS at time t0 in FIG. 2 to indicate that the address on the address bus 11 is valid (step A).
1: FIG. 3).

The cache memory 40 stores the control signals ADS and adrs (address) -A at time t in FIG.
When received in step 1, rvd41 and tag42 as state information in the cache memory 40 are checked (step A).
2, A3: FIG. 3).

If the cache memory 40 has a valid cache line, the response signal VLD is
Is returned via the control bus 12 during the time t1. If the control bus 12 instructs a read operation, the data in the cache memory 40 corresponding to the specified address is
The data is output to the CPU 10 via the data bus 13 at time t2 in FIG. 2 (step A4: FIG. 3).

The CPU 10 converts the read data into the data shown in FIG.
At time t3. If the control bus 12 has instructed the write operation, the write data from the data bus 13 is taken into the cache line corresponding to the address specified at the time t2 in FIG. 2 (step A4: FIG. 3).

If there is no valid cache line, the state becomes a miss-hit state. At this time, the cache memory 40 outputs the MIS signal 60 at time ta in FIG. 2 and enters its own inspection mode.

The bus unit (BU) 20 is enabled and the main memory (Mem) 30 can be accessed. During time ta in FIG. 2, the control signal AD
When S is output to the control bus 22 and main memory access is started, a response from the main storage memory (Mem) 30 is awaited (step A5: FIG. 3).

Upon receiving the MIS signal 60, the memory control circuit 50 starts a self-test operation (step B1:
(Fig. 3). The CHKCTL circuit 52 outputs a pointer for selecting one of the cache lines held in the cache memory 40 from the A_PTRCTR circuit 53 to the signal 63 at time ta in FIG. 2 and sends the pointer to the cache memory 40 (step B2: FIG. 3). ).

The cache data 43 and code 44 of the cache line selected by the pointer are sent to the CHKer circuit 54 as a signal 64 and a signal 65, respectively. The CHKer circuit 54 checks the normality of the data extracted during the time ta in FIG. 2 (step B3: FIG. 3).

When a failure due to poor holding characteristics or the like is detected, the failure signal is reported to the CHKCTL circuit 52 by a result signal 66. If the result indicates that the contents of the result have been corrected (step B4: FIG. 3),
Cachedata4 corrected by the CHKer circuit 54
3 and the code 44 are written back to the pointed cache line in the cache memory 40 during the time tb in FIG. 2 (step B5: FIG. 3).

If the contents of the result indicate that correction is not possible and the rvd 41 as the status information of the cache line of the cache memory 40 indicates clean (step B8: FIG. 3), the CHKCTL circuit 52 is checked. The elimination of the failed data is performed during the time tb in FIG.
An ove signal 67 is output to instruct the cache memory 40.

The cache memory 40 that has received the remove signal 67 stores the rvd 41 as the state information of the cache line selected by the pointer at the time tc in FIG.
Is rewritten to invalid to eliminate data (step B6: FIG. 3).

The contents of the result indicate that correction is impossible, and the rvd 41 as the status information of the cache line of the cache memory 40 is the main storage memory (Me
m) If it indicates a dirty state that requires sweeping out to 30 (Step B8: FIG. 3), the CHKCTL circuit 52 outputs the remove signal 67 during time tb in FIG. 2 as uncorrectable failure data. Cache memory 4
Indicate to 0.

The cache memory 40 stores the time tc in FIG.
Then, rvd41 as the status information of the cache line selected by the pointer is marked as remove (step B9: FIG. 3).

Further, when the CHKCTL circuit 52 detects a serious failure, it sends out an alarm signal 68 at time tc in FIG. 2 to interrupt the CPU 10 (step B1).
0: FIG. 3).

The CHKCTL circuit 52 uses the A_PTRCTR circuit 5 at time td in FIG. 2 for the next self-test access.
The pointer value in 3 is updated, and the self-test operation is completed (step B7: FIG. 3).

In a state where the CPU 10 is dedicated to internal processing, the CPU 10 outputs a busy69 signal indicating that no memory access is being performed (step C).
1: FIG. 3). The memory control circuit 50 has a bus 69
Is detected, a self-inspection operation is started (step B).
1: FIG. 3).

As described above, in the present embodiment, the autonomous self-check is executed for all the internal cache lines during the free time of the cache memory 40 to prevent a potential failure. Can be detected at an early stage.

Further, since a major multiple failure can be prevented by detecting and eliminating the intermittent failure of the cache memory 40 at an early stage, high reliability can be maintained and stable operation service of the system can be continued. Therefore, seamless operation can be continued without interrupting operation of the entire system. Further, since a serious failure detected by the autonomous self-test is interrupted to the CPU 10 as an upper device at an early stage, the reliability can be improved.

[0050]

As described above, according to the memory control device and the memory control method of the present invention, when the memory access is started by the CPU and the cache memory is in an empty state, the memory control circuit checks the cache memory. The cache line to be specified is specified, and the data of the specified cache line is retrieved from the cache memory and inspected, so that system operation can be seamlessly continued by early detection of failure and elimination of failure, and reliability can be improved. Can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a memory control device of the present invention.

FIG. 2 is a time chart for explaining an operation of the memory control device of FIG. 1;

FIG. 3 is a flowchart illustrating an operation of the memory control device of FIG. 1;

[Explanation of symbols]

 10 CPU 11 Address bus 12 Control bus 13 Data bus 20 Bus unit (BU) 21 Address bus 22 Control bus 23 Data bus 30 Main storage memory (Mem) 40 Cache memory 41 rvd 42 tag 43 cachedata 44 code 50 Memory control circuit 51 Det Detection circuit 52 CHKCTL circuit 53 A_PTRCTR circuit 54 CHKer circuit 60 mis signal 61 to 65 signal 67 remove signal 68 alarm signal 69 busy signal

Claims (10)

[Claims] A CPU for performing a memory access, and a CPU via a memory bus for internal access.
A main unit memory connected to the bus unit via a memory bus for external access; and a bus unit connected to the C via a memory bus for internal access.
A memory, comprising: a cache memory connected to a PU; and a memory control circuit for examining data in the cache memory when memory access is started by the CPU and the cache memory is empty. Control device. 2. The cache memory according to claim 1, wherein when the memory access is started by the CPU, if there is no valid address portion, the cache memory generates a miss signal and the main memory is accessed by the CPU. 2. The memory control device according to claim 1, wherein the memory control device remains empty until a response is received from the memory controller. 3. The memory control circuit, upon receiving the MIS signal, a cache line designating means for designating a cache line to be inspected in the cache memory, and fetching data of the designated cache line from the cache memory. 2. The memory control device according to claim 1, further comprising: a data inspection unit that performs an inspection by performing a test. 4. The cache line designating means, when the data check means corrects correctable data in the cache memory, writes the corrected data back to the cache line. Item 4. The memory control device according to item 3. 5. The cache line designating means, when it is impossible to correct the data in the cache memory by the data checking means, excludes the uncorrectable data and, when detecting a serious failure, CPU
4. The memory control device according to claim 3, wherein a fault is notified to the memory controller. 6. A first step of performing a memory access to a cache memory or a main storage memory, and a step of checking data in the cache memory when the memory access is started and the cache memory is in an empty state. 2. A memory control method, comprising: 7. In the second step, when a valid address portion does not exist when the memory access is started, a miss signal is generated, and a miss signal is generated from the main memory accessed by the memory. 7. The memory control method according to claim 6, further comprising the step of: leaving a vacant state until a response is received. 8. The method according to claim 8, further comprising: receiving the MIS signal, specifying a cache line to be inspected in the cache memory, and transmitting the data of the specified cache line to the cache memory. 7. The memory control method according to claim 6, further comprising: performing a test by taking out the memory from the memory. 9. The fourth step includes a step of correcting correctable data in the cache memory, and the third step writes the corrected data back to the cache line. 9. The memory control method according to claim 8, comprising a step. 10. The method according to claim 3, wherein the third step includes a step of, when the data of the cache memory cannot be corrected, excluding the uncorrectable data and notifying a failure. The memory control method according to claim 8.