JPH06152392A - System clock generator - Google Patents

Abstract

PURPOSE:To reduce the size and cost of a system clock generator capable of temporarily changing the frequency of a clock and increasing or decreasing the number of clocks to be generated within a certain period. CONSTITUTION:An input clock is frequency-divided by a variable frequency divider 2 and the frequency-divided clock is inputted to a PLL circuit 3. The frequency dividing ratio of the frequency divider 2 is controlled by a frequency dividing ratio control circuit 1, and when a control signal is inputted from the external, the frequency dividing ratio of the divider 2 is changed only for a certain fixed period. An output clock is extracted from the PLL 3, and when a control signal is not inputted from the external, the phase of the output clock is synchronized with that of the input clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system clock generator for a digital transmitter / receiver for a mobile unit.

[0002]

2. Description of the Related Art Radio wave propagation in a mobile body has many propagation paths due to diffraction, reflection, etc., and changes every moment.
The receiver receives the strongest radio wave among the radio waves that have passed through a plurality of routes, but the data propagation time between transmission and reception varies depending on the route through which the radio wave propagates. The receiver detects this difference in data propagation time and feeds it back to the system clock generator to temporarily change the frequency of the system clock to absorb the difference in data propagation time. The converter converted this into an analog quantity based on the feedback data and directly controlled the VCO inside the PLL.

FIG. 3 is a system diagram of a conventional system clock generator. When the lead / lag control signal is input, the lead / lag control voltage generating circuit 4 outputs a voltage having an appropriate value for a certain period. The output of the lead-lag control voltage generation circuit 4 is directly input to the VCO 6 via the voltage adder 5, and the frequency of the system clock can be changed for a certain period. A PLL circuit 3 includes a phase adder (PD) 7 and a low pass filter (LPF) 8 in addition to the voltage adder 5 and VCO 6.

[0004]

In this conventional system clock generator, since an analog amount is handled, it is necessary to make an adjustment at the time of offset adjustment of the analog arithmetic unit, and in order to miniaturize and mass-produce the receiver. It was an obstacle.

[0005]

A system clock generator according to the present technology divides an input clock to generate a PLL (Phas).
e Locked Loop) As a reference of the circuit, by inserting a frequency divider with the same frequency division ratio as the input inside the PLL, in the system that oscillates the VCO at the same frequency as the input clock and takes it out as the output clock The frequency divider is provided with a frequency division ratio control circuit for temporarily changing the frequency division ratio of the variable frequency divider by an external control signal.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings. FIG. 1 is a system diagram of an embodiment of the present invention. Set the input clock frequency to fin and the output clock frequency to fout
And Further, the normal frequency division ratio of the variable frequency divider 2 is set to n _N ,
The frequency division ratio is n _A for the advance control and n _R for the delay control.
Then, the frequency division ratio of the frequency divider 9 inside the PLL circuit 3 is n _N
And fout = fin at the normal time. Further, the relationship of the frequency division ratio is as follows.

_{N A} <n _N <n _R (1) The frequency division ratio control circuit 1 changes the frequency division ratio of the variable frequency divider 2 for a certain period t when receiving the advance control signal or the delay control signal. For example, when the advance control signal is input, the PLL
The reference clock of is fin / n _A , and the normal fin
The frequency is higher than / n _N. Therefore, the frequency of the output clock also increases, and the frequency of the output clock is n _N / n
_Although it becomes _A times, when the control period t passes, the frequency returns to the normal frequency. How to change the frequency of the output clock is determined by the operating speed of the PLL. By properly selecting the operating speed, frequency division ratio and control period of the PLL, the system clock generated by a necessary amount within a fixed period. You can increase or decrease the number of.

FIG. 2 shows a second embodiment of the present invention. The system clock generator itself has a function of temporarily changing the frequency of the clock.

[0009]

As described above, according to the present invention, since the analog amount is not used for temporarily changing the frequency of the system clock, adjustment is not necessary and integration is possible. It has the effect that it can be converted.

[Brief description of drawings]

FIG. 1 is a system diagram of an embodiment of the present invention.

FIG. 2 is a system diagram of a second embodiment of the present invention.

FIG. 3 is a system diagram of a conventional example.

[Explanation of symbols]

1 Frequency division ratio control circuit 2 Variable frequency divider 3 PLL (Phase Locked Loop)
Circuit 4 Lead-lag control voltage generation circuit 5 Voltage adder 6 Voltage-controlled oscillator 7 Phase comparator 8 Low-pass filter 9 Frequency divider

Claims (1)

[Claims] 1. A PLL (Phas) which, when a reference clock is input, generates an output clock having a frequency equal to or an integral multiple of the reference clock in synchronization with the phase of the reference clock.
e Locked Loop) circuit, a variable frequency divider for a reference clock input, and a frequency division ratio control circuit capable of changing the frequency division ratio of an external control signal input for a certain period. System clock generator characterized by.