JPS5887921A - Multiple output frequency synthesizer - Google Patents

Abstract

PURPOSE:To obtain a plurality of continuous frequency signals, by using a frequency synthesizer repetitively outputting a plurality of frequency signals in time division, a gate circuit sectioning and outputting the signals at each channel number, and using a sample phase locked loop locked and held to this output. CONSTITUTION:A frequency synthesizer 1a outputs various frequencies corresponding to each channel number in burst state. A gate circuit 14 sections various frequencies with a control signal (c) at each channel number and forms reference signals fA, fB,...fZ of sample phase locked loops 13A-13Z. Since holding function is given to the sample phase locked loops 13A, 13B,...13Z so as to be outputted as continuous signals, only one frequency synthesizer of the local oscillator of an SCPC device is enough, allowing to attain small size.

Description

[Detailed Description of the Invention] This invention is based on S CP C (Single Channel).
A conventional device of this type is shown in FIG. The figure number 2 indicates the T1 (transmitting side, 9-E the receiving) side, and A, B, . . . , L are the input base punt signals 5, (I A ), (I B ), . ...,
(IL) is a frequency synthesizer that can vary the output frequency in steps of the reference frequency, (2A), (2B),...
, (2L) are input bass punt signals A, B,...
Mixer (3) converts the frequency of L into IF band signals a, b, ..., t, and combines the multiple input signals a, b, ..., t into a single transmitter output signal OU. A combiner (4) outputting T converts a single receiver input signal IN into multiple IF band signals m.

n, ・−=, a distributor that distributes to z, (iM),
(IN], ..., (IZ) are frequency synthesizers that can vary the output frequency in steps of the reference frequency, (2M)
, (2N), -, I2Z) converts the iF band signals m, n, ..., 2 into baseband output signals M,
N.

..., a frequency converter for converting into Z, (6) an oscillator for generating an input signal to the frequency synchronizer (1), 15
1 is a buffer circuit for distributing the output of the oscillator (6) to each synthesizer (1).

Figure 3 is for supplementary explanation of Figure 1.
The configuration of the frequency synthesizer (]) shown in the figure is shown.

3 in the same figure, (7) is a voltage-controlled oscillator (VCO) whose oscillation frequency is controlled by the input voltage, and t81 is vC
(9) is a phase comparator (PSl) that detects the difference between the phase of the divided output of VCO+71 and the phase of the external reference frequency signal r.
)), (101 is a low-pass filter (L P F ) that determines the initial characteristics of the phase-locked circuit, flll+ is a switch that outputs the channel number in BCD code, +1
21 is a variable frequency divider (8
), S is the above v CO+
71 output signal, which is the output signal of this frequency synthesizer (
1) is the output signal.

The missing number operation will be explained. The signals outputted from the oscillator (6) are first outputted multiple times from the buffer circuit (5) and become a reference frequency signal group for the frequency synthesizer (1). In the frequency synthesizer (1), the phase difference between the reference frequency signal r and the frequency-divided signal of the output S of V C0171 is calculated from PSI] 91 +, and the PSD (output 4 voltage of 91 L P F (1
By smoothing by 1 Jl and adding VCO (7th control voltage), the divided frequency of V CO+71 is finally made to match the reference frequency.Then, the output frequency of V CO+71 when phase synchronized is is fvco=Nmf, where fo is the standard circumference.

N is the number of branch stations. Therefore, by outputting the frequency division number corresponding to the specified channel number from the logic circuit (121), the signal of the desired frequency is frequency-converted through the mixer (2) and output as an output signal.The same is true on the receiving side. By setting the switch tune of the frequency synthesizer (1) to the channel number assigned to each frequency synthesizer (1), the signal necessary for the own station can be extracted from the received signal group. Number of frequency synthesizers (1) equal to the channel capacity
By providing a local oscillator for each signal line,
On the transmitting side, the required number of carrier waves arranged at regular intervals is obtained, and on the receiving side, the required number of carrier waves arranged at regular intervals is obtained.
By changing the output frequency of the local oscillator on the receiving side from the transmitted wave, a baseband signal of the same frequency can be obtained.

2 in a 5CPC device with a relatively large channel) V capacity,
Conventional devices are configured to have the same number of synthesizers as the channel capacity to be accessed, each serving as a local oscillator for transmitting and receiving, which poses a problem in that the device itself becomes large and needs to be miniaturized.

This invention was made in view of the problems of the conventional ones as described above, and achieved miniaturization by standardizing the frequency synthesizer and replacing the same number of synthesizers as the conventional channel capacity with sample phase-locked loops. The purpose is to provide a frequency synthesizer.

An embodiment of the present invention will be described below with reference to the drawings.

3 in Figure 2, (2A), (2B), ..., (2L
), (2M), (2N), ... (2Z), +3
1.

+41 and +61 indicate the same as in Figure 1, and (la
) is a reference frequency synthesizer (13A) that outputs frequency signals corresponding to a large number of child channel numbers in burst form.
), (13B), ..., (13L), (13M), (
13N),...j (1321 is a sample phase-locked loop composed of a phase comparator having a sample ho/71 function, (14) is a sample phase-locked loop consisting of a phase comparator having a sample ho/71 function, and (14) is a sample phase-locked loop that generates frequencies corresponding to a large number of channel numbers generated from the frequency synthesizer (1a). This is a gate circuit that uses an external sub-signal C to distinguish and output the same channel number, that is, the same frequency range.

Figures 4 and 5 are for supplementary explanation of Figure 2.
4 shows the configuration of the sample phase-locked loop (marked with i) in FIG. 2, and FIG. 5 shows the configuration of the frequency synthesizer (1a) in FIG. 3.

8 in Figure 4, (7) is VCO5+91) is PSI with f7 pull-hold +4 function), tlol is LPF,
r is a reference frequency signal and S is an output signal. 3 in Fig. 5, (7) is vco, ts) is a voltage divider, and t9
1ha P S D, GOILtL P F, f+21
Lta chic times IW! , (lla) is a switch that changes the channel number every moment in a certain time unit, r is a reference frequency signal, S is an output signal, and C is a side slope signal.Next, the operation will be explained.

First, in order to make one frequency synthesizer common, the output of V CO+71 in Figure 5 requires the number of cycles equal to the channel capacity, and to achieve this, the output of the switch (lla) in Figure 5 is changed in a certain time unit, and the logic circuit (the frequency division number of the 121 output is changed in units of 11 at that time). The frequency of the V COi71 output in the synchronized state is determined by the product of the reference signal frequency and the frequency division number,
By changing this number of branch stations at a sufficiently slow speed (on the other hand, the response speed of the loop), the output of Fig.
Various frequencies corresponding to each channel number are output in a burst state. However, this work of changing the number of branch stations shall be repeated several times. That is, instead of changing the frequency division number by the number of times corresponding to the channel capacity, one step is set to be the number of times in which the frequency division number is equal to the wax volume, and this is repeated. Gate circuit 041 in Figure 2
From this point, the various S frequencies are distinguished for each random number by the control signal C of the frequency synthesizer (1a), and the sample phase-locked loop (one country's reference signal fA,
Create fB,=-JL, fM, fN, , fZ. Here, each channel number (separated Letterhurst signal is divided into PSυ (9
a) is added as a reference signal r to one input of V
The phase is directly compared with the output frequency of COi 71, and the phase difference signal is sent to V CO (71
The loops are synchronized by regulating the voltage. In this case, as a condition for initial synchronization, it is necessary that the response speed of the loop be sufficiently fast compared to the period Jg1i of the input burst signal. However, since the human input is a burst signal, it immediately becomes an open loop, so during this time it is necessary to provide a hold function to keep the voltage constant and allow the V COi71 to oscillate stably. This can be solved by Aoko. The output of the VCO (71) obtained through this process is output as a stable continuous signal.

As described above, this invention is based on the 5CP (8 in the device), which has multiple channels, and the frequency synthesizer is shared by one synthesizer. By replacing it with a synchronous loop, an inexpensive and compact multi-output frequency synthesizer can be obtained.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a multi-output frequency synthesizer using a conventional frequency synthesizer, Fig. 2 is a block diagram of a multi-output frequency synthesizer according to an embodiment of the present invention, and Fig. 3 is a block diagram of a multi-output frequency synthesizer using a conventional frequency synthesizer. Fig. 4 is a block diagram of the sample phase synchronization l-70 in Fig. 2, and Fig. 5 is a block diagram of the
FIG. 2 is a configuration diagram of the frequency synthesizer shown in FIG. (1a) Reference frequency synthesizer, (13)...sample phase locked loop, 04) Gate circuit. In the figures, the same reference numerals indicate the same or corresponding parts. Agent Makoto Kuzuno
-Figure 1 Figure 2 Figure 3 Figure 596-

Claims (1)

[Claims] (1) A reference frequency synthesizer that repeatedly outputs multiple frequency signals in a time-sharing manner, a gate circuit that divides and outputs the multiple frequency signals from this reference frequency synthesizer into the same frequency range, and a A multi-output frequency synthesizer comprising: a sample phase-locked loop that uses a signal as a reference signal and outputs a signal synchronized with the reference signal.