JP3076256B2 - Multiple frequency output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-frequency output circuit, and more particularly to a multi-frequency output circuit for outputting a number of frequency components corresponding to a cyclic change in a plurality of local oscillation frequencies.

[0002]

2. Description of the Related Art A conventional apparatus for outputting a plurality of frequencies has a configuration in which the same number of frequency synthesizers as the number of output frequencies are provided. This has had a great effect on miniaturization and cost reduction of the apparatus. Particularly, with the development of mobile communication systems such as mobile phones and PHSs in recent years, the number of mobile radio base stations has increased dramatically, and this base station needs to transmit at many frequencies and receive components of many frequency bands. There is a need for technical development.

Therefore, as disclosed in Japanese Patent Application Laid-Open No. 58-87921, there is a circuit in which the same number of synthesizers as the channel capacity are replaced with a sample phase locked loop to reduce the size.

As a conventional configuration example, as shown in FIG.
PLL circuit 1 for alternately outputting a plurality of frequencies according to frequency designation data, switch circuit 2 for alternately dividing a plurality of frequencies according to switch switching data, and frequency synthesis for synthesizing each frequency via switch circuit 2 for continuous transmission A part 3 is provided.

As shown in FIG. 7, the frequency synthesizer 3 includes a sample PLL circuit 13 for each frequency, and each sample PLL circuit 13 further includes a voltage controlled oscillator whose oscillation frequency is controlled by an input voltage. 14
And a phase comparator having a phase comparator having a sample-and-hold function, having an input of the output of the voltage-controlled oscillator 14 and a predetermined frequency via the switch circuit 2 and outputting a continuous voltage.
D15 and the voltage output from PSD15 as inputs,
It comprises a filter 16 for smoothing the voltage input to the voltage controlled oscillator 14.

Next, the operation will be described. As an example, when two frequencies are output, the frequency designation data A for setting the frequency A and the frequency designation data B for setting the frequency B are alternately serialized as serial data to the PLL circuit 1 and the response speed of the loop is sufficiently low. By alternately outputting at the speed, the PLL circuit 1 can alternately output the frequency A and the frequency B.

Next, the frequency A output from the PLL circuit 1 and
The frequency B is input to the switch circuit 2 and the switch circuit 2
Is connected to the switch terminal 1 in advance, and the frequency A is output to the first system.

Next, the switch circuit 2 is connected to the switch terminal 2 of the switch circuit 2 based on the first switch switching data, and the frequency B is output to the second system.

As described above, the frequency A can be divided into one system and the frequency B can be divided into two systems by alternately and repeatedly switching 1 and 2 of the switch circuit 2 based on the switch switching data. However, it is intermittent transmission here.

Therefore, it is necessary to input the divided frequency A and frequency B to the sample PLL circuit 13 provided for each frequency of the frequency synthesizing section 3 and synthesize them so as to perform continuous transmission.

The detailed operation of the sample PLL circuit 13 is as follows. A predetermined frequency A passing through the switch circuit 2 is input as a reference signal to a PSD 15 having a sample and hold function, and the PSD 15 directly outputs an output frequency of the voltage controlled oscillator 14 to the PSD 15. A voltage corresponding to the phase difference is output to the voltage controlled oscillator 14 via the filter 16 and the voltage controlled oscillator 14 is voltage controlled to synchronize the loop.

In this case, the condition of the initial synchronization is as follows.
It needs to be fast enough.

Further, since the frequency A is intermittent transmission, it immediately becomes an open loop, so it is necessary to stabilize the voltage controlled oscillator 14 by stabilizing the voltage by providing a hold function during this period. This is realized by shortening the period of the intermittent transmission of the input signal.

In order to obtain a highly stable output frequency, PS
A filter 16 is added between D15 and the voltage controlled oscillator 14. With the above circuit, the frequency A can be continuously transmitted.

Similarly, the frequency B is also changed to the sample PLL circuit 1
3 enables continuous transmission.

[0016]

However, the first problem of the conventional multiple frequency output synthesizer is that PLL circuits must be added by the number of output frequencies. Therefore, large-scale circuit reduction has not been realized, and only small-scale miniaturization can be realized. In addition, since relatively expensive components such as a voltage controlled oscillator and a PSD are added as many as the number of output frequencies, a great merit cannot be obtained in terms of cost.

The second problem is that there are many restrictions on the intermittent transmission cycle. PL that receives frequency designation data
The L circuit alternately outputs a plurality of frequencies. However, it is necessary to alternately output the plurality of frequencies at a sufficiently low speed with respect to the response speed of the PLL cycle. In order to realize continuous transmission in the sample PLL circuit, it is necessary to shorten the period of the intermittent transmission of the frequency. As described above, the two are in a reciprocal relationship, so that the frequency synthesizer has many restrictions.

An object of the present invention is to provide a frequency synthesizer circuit capable of a plurality of outputs with a reduced size, a reduced number of components, and a reduced cost.

[0019]

According to the present invention, there is provided a multi-frequency output circuit capable of outputting a plurality of signals, comprising: a PLL circuit for outputting a frequency corresponding to the frequency designation data; A first switch circuit that periodically performs a switching operation in accordance with the following, and a frequency synthesizer that synthesizes the frequency separated by the first switch circuit. 1
To the N-th distribution unit, and the first frequency distributed by the distribution unit is output without delay, and the second to N-th frequencies distributed by the distribution unit are output with a predetermined delay amount in advance. A delay unit, a first frequency, and a first to Nth frequencies via the delay unit are input, and a switch unit for selecting a switch is provided. To N corresponding to the Nth switch terminal
And outputs N from frequency 1.

In a plurality of frequency output circuits for outputting a plurality of frequency components, a PLL circuit for outputting a frequency component corresponding to the frequency designation data in a time-series manner, and a first to an N-th (N is a positive integer) That periodically performs a switching operation in response to switch switching data for the switch terminal of
And a plurality of frequency synthesizers for synthesizing continuous frequency components with a plurality of delay units according to the intermittent frequency components separated by the first switch circuit. It is characterized in that frequency components can be continuously transmitted.

Further, in the above multiple frequency output circuit, the frequency synthesizing section converts the input frequency component into a first frequency component.
And the first frequency component distributed by the distributor is output without delay, and the second to N-th frequency components distributed by the distributor are each delayed by a predetermined delay. A delay unit that outputs a signal with an amount, and a switch unit that receives the first frequency component and the second to Nth frequency components via the delay unit and selects a switch. And In the multiple frequency output circuit, the switch unit synthesizes first to Nth frequency components of the same frequency corresponding to the first to Nth switch terminals, and continuously converts the frequency components 1 to N of the same frequency. Is output.

A plurality of frequency output circuits for respectively outputting a plurality of frequency components; a PLL circuit for outputting a frequency component corresponding to the frequency designation data in a time series;
A first switch circuit for distributing in accordance with switch switching data for each frequency component of the PLL circuit;
And a frequency synthesizer for synthesizing a continuous frequency component for each output number of the switch circuit, wherein the frequency synthesizer distributes the frequency component input from the first switch circuit to the first to Nth distribution components. And the first frequency component distributed by the distribution unit is output without delay, and the second to Nth frequency components distributed by the distribution unit are each given a predetermined delay amount in advance. It is characterized by comprising a delay unit for outputting, and a switch unit for performing switch synthesis by using the first frequency component and the second to Nth frequency components passing through the delay unit as inputs.

[Operation] The present invention enables a frequency synthesizer having a plurality of outputs by providing a frequency synthesizing unit with a distribution unit, a delay unit, and a switch unit.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION

First Embodiment [1] Description of Configuration Next, an embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, a multiple frequency output circuit according to the present invention includes a PLL circuit 1 for outputting a frequency component corresponding to frequency designation data, and a first to an Nth switch terminal corresponding to switch switching data. A first switch circuit 2 that periodically performs a switching operation and a frequency synthesizer 3 that synthesizes the frequency components separated by the first switch circuit 2.

The PLL circuit 1 includes a reference oscillator that oscillates a reference frequency using a crystal or a ceramic element, a voltage controlled oscillator (VCO), and a programmable frequency divider that divides the output signal of the VCO according to frequency designation data. A comparator for comparing the phase of the output of the programmable frequency divider with the output of the reference oscillator, and a low-pass filter for filtering only a predetermined frequency component from the output of the comparator. , A stable multi-frequency signal can be obtained. Here, the output signal of the VCO is used as the output of the PLL circuit 1, and the output signal of the programmable frequency divider changes in accordance with the frequency division ratio specified by the frequency specification data. , A stable frequency component can be output. In the PLL circuit 1, the frequency component cannot be switched and output immediately in response to the change of the frequency designation data, especially due to the response of the low-pass filter. Therefore, the switching time needs some allowance for the frequency change time.

The switch circuit 2 may be a mechanical switch, but is preferably an analog switch using a MOS transistor, and may be an ECL switch capable of high-speed switching. In addition, the switch circuit 2 can easily obtain a one-input multi-terminal output in a small size.

Further, the configuration of the frequency synthesizing unit 3 is as follows: a distributing unit 4 for distributing the input frequency components from the first to the N-th, and the first frequency components distributed by the distributing unit 4 are output without delay. The second to N-th frequencies distributed by the distribution unit 4 are output with a predetermined delay amount beforehand.
, A first frequency component, and a second to N-th frequency components passing through the delay unit 5, and a switch unit 6 for selecting a switch.

The frequency synthesizer 3 is composed of N switches corresponding to the first to N-th switch terminals of the first switch circuit 2. That is, the frequency components corresponding to the number of types of the frequency designation data can be continuously output from the respective frequency synthesizers 3.

The distribution unit 4 of the frequency synthesis unit 3
Of the switch circuit 2 is received by the buffer amplifier and output to each delay unit as a low impedance output. Alternatively, a CMOS buffer amplifier may be used for each output. Further, the delay unit of the delay unit 5 of the frequency synthesis unit 3 is provided with the number obtained by subtracting 1 from the number of switching of the first switch circuit 2, and the delay unit using a surface acoustic wave (SAW) element is realistic. To a small extent, any of a delay device using an LC circuit, an A / D, D / A converter, and a digital delay device using a FIFO memory may be used. The switch circuit of the switch section 6 may be the same as that described for the switch circuit 2, and operates at the same steps in terms of timing except that the initial setting state is different. Further, the switching timing of the frequency designation data is synchronized with the first switch circuit 2 and the switch section 6, and if the frequency designation data changes cyclically, the same switching signal is supplied to the present frequency synthesizer. May be done.

[2] Description of Operation Next, the operation of the multiple frequency output circuit of FIG.
This will be described with reference to FIG. FIG. 2 is a circuit example of a two-output frequency output circuit, and FIG. 3 is a time chart in the case of a two-output frequency output circuit.

For example, when switch switching data for controlling the switching of the first switch circuit 2 is input as shown in FIG. 3A and two frequency components are output, the frequency specifying data for specifying the frequency A component is output. A and frequency designation data B for designating the frequency B component are alternately input as serial data to the PLL circuit 1 as shown in FIG. 3B, so that the PLL circuit 1 can plot the frequency A and the frequency B component. As shown in (c) of FIG. 3, output can be performed alternately. Where P
It is necessary to switch the frequency designation data at a sufficiently low speed with respect to the response speed of the loop of the LL circuit 1.

Next, the frequency A component and the frequency B component output from the PLL circuit 1 are input to the switch circuit 2, and the switch circuit 2 is connected to the switch terminal 1 in advance. Is output to

Next, the first switch circuit 2 is connected to the switch terminal 2 side of the first switch circuit 2 by the first switch switching data, and the first frequency B component is 2
Output to the system.

As described above, the first switch circuit 2 uses the switch switching data synchronized with the frequency designation data.
By repeatedly and alternately switching the switch terminals 1 and 2, the frequency A component is changed to the first system as shown in FIG.
The frequency B component can be divided into two systems as shown in FIG. However, this is an example of intermittent transmission.

Therefore, it is necessary to input the separated frequency A component and frequency B component to the frequency synthesizing unit 3 and synthesize them so as to perform continuous transmission.

As an operation of the frequency synthesizer 3, the frequency A component passing through the first switch circuit 2 is divided into two by the distribution circuit 7 of the distributor 4, and the first frequency A component is shown in FIG. The second switch circuit 11 of the switch unit 6
Is directly input to the switch terminal 1.

The second frequency A component is time-delayed by the delay circuit 9 of the delay unit 5 (hereinafter referred to as A ') of the first frequency designation data A, and is switched as shown in FIG. The signal is input to the switch terminal 2 of the second switch circuit 11 of the unit 6.

A first frequency A component having the same frequency;
The second section of the switch section 6 which receives the second frequency A 'component as an input
Is connected to the switch terminal 1 in advance, and outputs a first frequency A component.

Next, the second switch circuit 11 of the switch section 6 is operated according to the first switch switching data (a).
Switches to the switch terminal 2 to output the second frequency A 'component.

The above operation of switching the switch terminals 1 and 2 is defined as one cycle, and by repeating this cycle, the frequency A component and the frequency A 'component are continuously repeated as shown in FIG. The same frequency component can be output as a transmission signal by setting the delay time of the delay device to be a delay device in which the phase components also match each other.

Similarly, the frequency B via the switch circuit 2
The component is divided into two by the distribution circuit 8 of the distribution unit 4, and the first
The frequency B component of the switch unit 6 as shown in FIG.
Are directly input to the switch terminal 1 of the third switch circuit 12.

The second frequency B component is time-delayed by the first frequency designation data A (hereinafter, referred to as B ') by the delay circuit 10 of the delay unit 5, and as shown in FIG. The signal is output to the switch terminal 2 of the third switch circuit 12 of the switch section 6.

However, the third switch component circuit 12 of the switch section 6, which receives the first frequency B component and the second frequency B 'component of the same frequency, is connected to the switch terminal 2 in advance. No output.

Next, according to the first switch switching data, the third switch circuit 12 of the switch section 6 switches to the switch terminal 1, and outputs the first frequency B component.

Next, the third switch circuit 12 of the switch section 6 is switched to the switch terminal 2 by the second switch switching data, and outputs the second frequency B '.

The above operation of switching the switch terminals 2 and 1 is defined as one cycle, and by repeating this cycle, the frequency B component can be output as continuous transmission as shown in FIG. 3 (k).

The above operation can be applied to the case where the number of frequency components is N. That is, when outputting N frequencies in the same manner, the frequency N component is output from the frequency A component by the PLL circuit 1, switched and separated by the first switch circuit 2, and input to the frequency synthesis unit 3.

Further, for example, the frequency A component input to the frequency synthesizer 3 is distributed to N by the distributor 4, and the first frequency A component is input to the switch terminal 1 of the second switch 6 without delay. Is done. The second frequency A ″ component is time-delayed by the first frequency designation data in the delay unit 5 and is input to the switch terminal 2 of the switch unit 6. The third frequency A ′ ″ component is delayed by the delay unit 5 twice as long as the first frequency designation data, and is input to the switch terminal 3 of the switch unit 6. As described above, the N-th frequency ^AN component is delayed by the delay unit 5 for N-1 times the first frequency designation data, and is input to the switch terminal N of the switch unit 6. The same operation is performed from the frequency B component to the frequency N component.

However, the initial setting of the switch terminals of the switch section 6 is such that the frequency A component is the switch terminal 1, the frequency B component is the switch terminal 2, the frequency C component is the switch terminal 3, and the frequency N component is the switch terminal N. ... N → 1 if, for example, the initial setting of the switch terminal is 1 according to the switch switching data.
By repeatedly switching to →, continuous transmission becomes possible, and continuous transmission from the frequency A component to N becomes possible.

[Second Embodiment] In a conventional frequency synthesizer for continuously transmitting a plurality of local frequencies, a PLL circuit must be provided for each frequency, which greatly affects the miniaturization and cost reduction of the device. Was.
Therefore, a plurality of local frequencies are created by one PLL circuit, separated by a switch circuit, and combined so as to be continuously transmitted, so that a plurality of local frequencies can be output by continuous transmission.

FIG. 4 is a block diagram showing the configuration of the multi-frequency output circuit according to this embodiment. The blocks having the same functions as those in FIG. A PLL circuit 1 for alternately outputting a plurality of frequencies according to frequency designation data, a switch circuit 2 for separating each of the plurality of frequency components, and a frequency synthesis circuit 3 for synthesizing each frequency component via the switch circuit 2 for continuous transmission Consists of

FIG. 5 is a timing chart for explaining the operation of this embodiment. When two frequencies are output as an example of the operation, as shown in FIG. 5B, frequency designation data A for setting a predetermined frequency A component and frequency designation data B for setting a predetermined frequency B component Are input to the PLL circuit 1 alternately as serial data,
The LL circuit 1 can output a predetermined frequency A component and a predetermined frequency B component alternately.

Next, the predetermined frequency A component and the predetermined frequency B component output from the PLL circuit 1 are input to the switch circuit 2, and the switch circuit 2 uses the first switch switching data (a) to output a Side connected to the first
The first predetermined frequency A component is output to the first system. Next, the switch circuit 2 is connected to the b side of the switch circuit 2 by the second switch switching data (a), and the first predetermined frequency B component is output to the second system. As described above, by alternately switching the terminal a and the terminal b of the switch circuit 2 based on the switch switching data (a), the predetermined frequency A component can be divided into one system and the predetermined frequency B component can be divided into two systems. . However, it is intermittent transmission here.

Then, the predetermined frequency A component and the predetermined frequency B component that have been separated are input to the frequency synthesizing circuit 3 and are synthesized so as to be continuously transmitted and output as local frequencies.

The detailed operation of the frequency synthesis circuit 3 is as follows.
The predetermined frequency A component passing through the switch circuit 2 is divided into two, and the first predetermined frequency A component is
The second predetermined frequency A component is directly input to the terminal, time-delayed by the first frequency designation data A by the delay circuit 24, and input to the a side of the switch circuit 26. At this time, the delayed second predetermined frequency component is set as a frequency A 'component. As the operation of the switch circuit 26, the switch circuit 26 is connected to the b side by the first switch switching data, and outputs the first predetermined frequency A. Next, the switch circuit 26 is connected to the a side of the switch circuit 26 based on the second switch switching data, and outputs a second predetermined frequency A 'component. As described above, by alternately switching the terminal a and the terminal b of the switch circuit 26 with the switch switching data (a), the predetermined frequency A
The components can be transmitted continuously.

Similarly, the predetermined frequency B component that has passed through the switch circuit 2 is divided into two, and the first predetermined frequency B component is directly input to the b side of the switch circuit 27, and the second predetermined frequency B component is input. Is delayed by the delay circuit 25 by the time of the first frequency designation data A, and is input to the a side of the switch circuit 27. Here, if the switch circuit 27 is connected to the a side by the first switch switching data, a predetermined frequency A can be obtained by alternately switching the terminals a and b of the switch circuit 27 by the switch switching data.
Similarly to the component, the predetermined frequency B component can be continuously transmitted.

According to the present embodiment, since a plurality of local frequencies can be continuously transmitted and output by one PLL circuit, the size of the apparatus can be reduced, the number of components can be reduced, and the cost can be reduced.

[0059]

According to the present invention, since a plurality of local signals can be continuously transmitted by one PLL circuit, it is possible to provide a multi-frequency output circuit that is reduced in size and cost.
This is particularly effective in the case of a dual-band wireless base station device such as a two-output PDC system.

In addition, the limitation of the period of intermittent transmission for the PLL circuit to output a plurality of frequencies alternately is that the PLL circuit outputs the frequencies alternately at a sufficiently low speed with respect to the response speed of the loop. Can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing an embodiment of the present invention.

FIG. 3 is a time chart illustrating the operation of the embodiment of the present invention.

FIG. 4 is a block diagram showing an embodiment of the present invention.

FIG. 5 is a time chart illustrating the operation of the embodiment of the present invention.

FIG. 6 is a block diagram showing an embodiment of a conventional example.

FIG. 7 is a block diagram showing details of a conventional sample PLL circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 PLL circuit 2 switch circuit 3 frequency synthesis section 4 distribution section 5 delay section 6 switch section 7 distribution circuit 8 distribution circuit 9 delay circuit 10 delay circuit 11 switch circuit 12 switch circuit 13 sample PLL circuit 14 voltage controlled oscillator 15 PDS 16 filter

Claims (4)

(57) [Claims] 1. A multi-frequency output circuit for outputting a plurality of frequency components, comprising: a PLL circuit for outputting a frequency component corresponding to frequency designation data in a time-series manner; Nth
(N is a positive integer) a first switching circuit that periodically performs a switching operation in accordance with switch switching data to separate the frequency components, and a first switching circuit that is separated by the first switching circuit. and a plurality of frequency synthesizing unit for synthesizing the continuous frequency components comprises a plurality of delay units in accordance with the intermittent frequency components, respectively continuous output said frequency components from each of said plurality of frequency synthesis unit A multi-frequency output circuit characterized by being made possible. 2. The multi-frequency output circuit according to claim 1, wherein the frequency synthesizer distributes the input frequency component from first to N-th, and a first frequency divider distributed by the distributor. A delay unit that outputs the frequency components without delay, and outputs the second to Nth frequency components distributed by the distribution unit with a predetermined delay amount, respectively; the first frequency component and the delay And a switch unit for selecting a switch by using the second to Nth frequency components passed through the unit and selecting a switch. 3. The multi-frequency output circuit according to claim 2, wherein the switch unit combines first to Nth frequency components of the same frequency corresponding to the first to Nth switch terminals, and outputs the same frequency. A multi-frequency output circuit for continuously outputting N components from frequency 1 of the multi-frequency output circuit. 4. A plurality of frequency output circuits each outputting a plurality of frequency components, a PLL circuit outputting a plurality of frequency components corresponding to frequency designation data in a time series, and a switch for each frequency component of the PLL circuit. A first switch circuit for distributing according to the switching data; and a frequency synthesizer for synthesizing the frequency component into a continuous frequency component for each output number of the first switch circuit. the frequency synthesizer unit includes a distribution unit for the N distributing the frequency components inputted from the first switching circuit from the first, the first frequency component has been distributed by the distribution unit output without delay The second to Nth frequency components distributed by the distributor are output with a predetermined amount of delay in advance, and the second frequency component passes through the first frequency component and the delay unit. A switch unit for performing switch synthesis by using the second to Nth frequency components as inputs and performing the continuous frequency component .