JPH06151866A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the resistance to a load short-circuit in which a large collector current flows in a condition that a collector voltage of an IGBT is applied between collector and emitter. CONSTITUTION:Two MOSFETs 11 and 12 are inserted in series between a gate electrode 7 and an emitter electrode 9 of an IGBT, and a gate electrode of one MOSFET is connected to the gate electrode 7 of the IGBT and a gate electrode 6 of the other MOSFET is connected to a collector electrode 10 of the IGBT. By turning on both the MOSFETs 11 and 12 when both a gate potential and a collector potential of the IGBT are a high load short-circuit, the break of the IGBT can be prevented since the gate potential of the IGBT drops to an emitter potential.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate which switches a current flowing between electrodes provided on both main surfaces of a semiconductor substrate so as to be switched by a gate electrode provided on one main surface via an insulating film. Type bipolar transistor (hereinafter IGB
(Hereinafter referred to as T) as a main element, and a load short circuit withstand function improving function is added to the semiconductor device.

[0002]

2. Description of the Related Art An IGBT has been widely used as a power switching element capable of voltage-driving a current flowing between both electrodes provided on both main surfaces of a semiconductor substrate. Is required to improve. FIG. 2 shows the basic structure of an N-channel insulated gate bipolar transistor. High impurity concentration P ⁺⁺
N a low impurity concentration on the substrate 1 ^- the silicon wafer formed by depositing an epitaxial layer 2 N ^- selectively P on the surface layer of the layer 2 ^- diffusion layer 3 is formed, the P ^- surface of the diffusion layer 3 An N ⁺ source region 4 is selectively formed in the layer. A portion of the surface of the P ⁻ diffusion layer 3 sandwiched between the exposed portion of the N ⁻ layer 2 and the N ⁺ source region 4 is a channel portion 5, and the polycrystalline silicon is formed on the channel portion 5 via the gate oxide film 6. The gate electrode 7 is provided. Further, the P ⁻ diffusion layer 3 and the N ⁺ source region 4 are commonly in contact with the emitter electrode at the window of the oxide insulating film 8, while the back surface of the P ⁺⁺ substrate 1 is in contact with the collector electrode 10.

In this device, the emitter electrode 9 is grounded, and a positive voltage is applied to the collector electrode 10 while the gate electrode 7
When a voltage higher than the threshold voltage is applied to the channel part 5,
Is inverted from P-type to N-type, and electrons from the emitter electrode are N-type
⁺ Source region 4, inverted portion of channel portion 5, N ⁻ epitaxial layer 2, P ^{+ +} substrate 1 through collector electrode 10
It becomes conductive by flowing to. Then, this electron current becomes a base current of a PNP bipolar transistor consisting of the P ^{+ +} substrate 1, the N ^- epitaxial layer 2 and the P ^- diffusion layer 3 to operate this transistor, causing conductivity modulation in the N ^- epitaxial layer 2. , A relatively low on-voltage can be obtained. On the other hand, when a voltage equal to or lower than the threshold voltage is applied to the gate electrode 7, the inversion of the channel portion 5 does not occur, so that the conduction state is not established.

This semiconductor element manufacturing method is performed in the following procedure. After forming the gate oxide film 6 and the gate electrode 7 made of polycrystalline silicon on the surface of the silicon wafer made of the P ⁺⁺ substrate 1 and the N ⁻ epitaxial layer 2,
These two layers are selectively etched and patterned. The P ⁻ diffusion layer 3 is formed by ion-implanting P-type impurities through the window generated at this time and thermally diffusing them. Further, N-type impurities are ion-implanted and thermally diffused. Then
An oxide insulating film 8 serving as an interlayer insulating film is deposited and etched to form a contact hole. The N ⁺ source region 4 is formed by etching the diffusion layer of the N-type impurity until the P ⁻ diffusion layer 3 is exposed using the same mask as that used at this time. Further, the oxide insulating film 8 is over-etched and then the used mask is removed. After that, a metal electrode layer is deposited by vapor deposition and etched to form the emitter electrode 9. Finally, a metal electrode layer is deposited on the back surface of the P ⁺ substrate 1 to complete the device as a collector electrode 10.

[0005]

In the normal operation of such an IGBT, the power supply voltage is IG when it is in the off state.
Although it is applied to both ends of the BT, the power supply voltage is applied to the load when it is in the ON state, and almost no voltage is applied to the IGBT. However, a case may occur in which the load is short-circuited with the power supply due to some failure. This is called load short-circuiting. When the load is short-circuited, the power supply voltage is directly applied to the IGBT when the IGBT is turned on. FIG. 3 is an operation waveform of a load short circuit test assuming the most severe state of such an element. The gate voltage waveform is at time t ₀
Then, for example, when the voltage exceeds the threshold value of 15 V, the collector current starts to flow. At this time, in normal operation, the voltage waveform drops to near the ground potential as shown by the dotted line, but in this test, the high voltage state is maintained as shown by the solid line.
Therefore, as shown in FIG. 4, the collector current flows as large as about 10 times the rated current. The heat generated by the product of this large current and high voltage raises the element temperature, and when the temperature reaches a temperature determined by the element, it latches up and is destroyed.

It is an object of the present invention that the IGBT of the main element is shown in FIG.
It is to provide a semiconductor device capable of withstanding the harsh conditions shown in (1).

[0007]

In order to achieve the above object, the semiconductor device of the present invention has a first and a second enhancement type field effect connected in series between a gate electrode and an emitter electrode of an IGBT. A transistor (FET) is inserted, the gate electrode of the first FET is connected to the gate electrode of the IGBT, the gate electrode of the second FET is connected to the collector electrode of the IGBT, and the first FET is connected to the IGBT.
When the gate potential of exceeds the specified value, the second FET
Are turned on when the collector potential of the IGBT exceeds a predetermined value. Further, it is effective that the enhancement type FET has a gate electrode provided via a gate insulating film on a semiconductor layer provided on the semiconductor substrate surface of the IGBT via an insulating film.
It is also effective that the gate electrode of the second FET is connected to the electrode provided between the active portion and the edge portion of the surface of the IGBT semiconductor substrate on the side of the emitter electrode, which has substantially the same potential as the collector electrode.

[0008]

As shown in FIG. 3, the collector potential is lowered when the gate potential is high in the normal operation, but both the gate potential and the collector potential are high when the load is short-circuited. IG
Since the gate electrodes of the enhancement type FETs connected in series inserted between the emitter electrode and the gate electrode of the BT are connected to the gate electrode and the collector electrode, respectively, the gate potential and the collector potential are both MOS transistors.
When it is higher than the threshold of FET gate voltage, both FE
If T is turned on, the gate electrode and the emitter electrode are short-circuited when the load is short-circuited, and the potentials become equal.
The GBT is turned off and the collector current is limited.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawing in which the same reference numerals are given to the same parts as in FIG. In the semiconductor device of one embodiment of the present invention shown in FIG. 1, the gate electrode 7
N-channel MOSFETs 11 and 12 connected in series are inserted between the emitter electrode 9 and the emitter electrode 9 by wirings 13, 14, and 15. The gate electrode of the MOSFET 11 is the gate electrode 7 of the IGBT, and the gate electrode of the MOSFET 12 is the collector electrode of the IGBT. 10 and wirings 16 and 17 respectively. Therefore, in this semiconductor device, the reference numerals entered in the drawing correspond to the same reference numerals in FIG. 1, and the reference numeral 20 has the equivalent circuit shown in FIG. 5 which is the IGBT of the main element.
The gate electrode of T11 is the gate electrode 7 of the IGBT and the MOS
The gate electrode of the FET 12 has the same potential as the collector electrode 1 of the IGBT.

This semiconductor device was manufactured as follows. That is, the surface of a silicon wafer having a low impurity concentration N ⁻ epitaxial layer 2 grown on a high impurity concentration P ⁺⁺ substrate 1 is oxidized to a thickness of about 1000 Å to form a gate oxide film 6. Then, a polycrystalline silicon layer to be the gate electrode 7 is deposited to a thickness of about 1 μm, heavily doped with phosphorus as an N-type impurity, and the polycrystalline silicon and the gate oxide film 6 are etched using the same mask. Boron as a P-type impurity is ion-implanted from the resulting window at a dose of about 1 × 10 ¹⁴ / cm ² to perform thermal diffusion to form a P ⁻ diffusion layer 3. Further, arsenic as an N-type impurity is ion-implanted with a dose of about 1 × 10 ¹⁵ / cm ² to perform thermal diffusion. P on it
An interlayer insulating film 8 such as an SG film is deposited to a thickness of about 1 μm and is etched using a resist mask. At this time, the arsenic diffusion layer is etched using the same mask to form the N ⁺ source region 4. Further, after the insulating film 8 is over-etched and the resist used at this time is removed, the N ⁺ source region 4 and the P ⁻ diffusion layer 3 are exposed. Then
A metal such as aluminum, which will become the emitter electrode 9, is deposited by vapor deposition, and unnecessary portions are removed by etching. The structure of the IGBT is completed by using the collector electrode 10 having a metal electrode layer deposited on the back surface of the P ⁺ substrate 1. After that, with the wiring 15, the N-channel MOSFET 12
Of the N-channel MOSFET 11 is connected to the emitter electrode 9 by the wiring 13, and the drain electrode of the N-channel MOSFET 11 is connected by the wiring 13 to the gate electrode.
Are connected so as to detect the potentials of the gate electrode 7 and the collector electrode 10.

In the embodiment shown in FIG. 6, the P-type silicon wafer on which the IGBT is formed has an electrode 18 provided near the edge where the guard rings 31 are formed in a plurality of steps, and a MOSFE.
The gate electrode of T12 is connected by a wiring 17. The stopper electrode 19 provided at the edge of the wafer is at substantially the same potential as the collector electrode 10 through the edge of the low resistance wafer, and the stopper electrode 19 is formed due to the potential difference between the collector electrode 10 and the emitter electrode 9. It is distributed between 19 and the emitter electrode 9. Therefore, the potential of the intermediate electrode 18 becomes lower than that of the collector electrode 10, so that the threshold voltage for applying this potential to the gate of the MOSFET 12 to turn it on can be lowered, and the MOSFET 12 can be easily manufactured. Further, the connection becomes easier than the connection with the collector electrode 10 on the back surface of the silicon wafer.

In the embodiment shown in FIG. 7, an N channel MOS is used.
FETs 11 and 12 are formed by a P-type portion 21 of a polycrystalline silicon layer deposited on a silicon wafer via an insulating film 8 and a gate electrode 23 provided on a gate oxide film 22 thereon. As a result, the MOSFETs 11 and 12 for short-circuiting the gate electrode 7 of the IGBT and the collector electrode 10 are connected to the IGBT.
It can be mounted on a silicon wafer of T, does not require an external MOSFET, can be completely monolithic, and can be formed as a compact semiconductor device.

[0013]

According to the present invention, the FE capable of short-circuiting the gate electrode and the emitter electrode when both the gate potential and the collector potential become high as when the load is short-circuited.
By inserting T between the gate and the emitter, the gate potential can be dropped when the load is short-circuited, so that the IGBT of the main element can be protected from destruction.

[Brief description of drawings]

FIG. 1 is a sectional view of an essential part of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view of the IGBT.

[Fig. 3] IGBT load short circuit test operation waveform diagram

FIG. 4 is an IGBT collector current / gate voltage relationship diagram.

FIG. 5 is an equivalent circuit diagram of a semiconductor device according to the present invention.

FIG. 6 is a cross-sectional view of essential parts of a semiconductor device according to another embodiment of the present invention.

FIG. 7 is a cross-sectional view of essential parts of a semiconductor device according to still another embodiment of the present invention.

[Explanation of symbols]

1 P ⁺⁺ Silicon substrate 2 N ^- Epitaxial layer 3 P ^- Diffusion layer 4 N ⁺ Source region 5 Channel part 6 Gate oxide film 7 Gate electrode 8 Interlayer insulating film 9 Emitter electrode 10 Collector electrode 11 MOSFET 12 MOSFET 21 Polycrystalline silicon layer P-type part 22 Gate oxide film 23 Gate electrode

Claims (3)

[Claims] 1. A first and a second enhancement type field effect transistor, which are connected in series, are inserted between a gate electrode and an emitter electrode of the insulated gate bipolar transistor, and the gate electrode of the first field effect transistor is insulated. For the gate electrode of the gate type bipolar transistor,
The gate electrode of the second field effect transistor is connected to the collector electrode of the insulated gate bipolar transistor, and the first field effect transistor is configured to operate when the gate potential of the insulated gate bipolar transistor exceeds a predetermined value. The field-effect transistor is turned on when the collector potential of the insulated gate bipolar transistor exceeds a predetermined value. 2. An enhancement-type field effect transistor, wherein a gate electrode is provided via a gate insulating film on a semiconductor layer provided on the surface of a semiconductor substrate of an insulated gate bipolar transistor via an insulating film. 1. The semiconductor device according to 1. 3. A gate electrode of the second field effect transistor is connected to an electrode provided between an active portion and an edge portion of the surface of the insulated gate bipolar transistor semiconductor substrate, which has substantially the same potential as the collector electrode on the emitter electrode side surface. The semiconductor device according to claim 1 or 2, which is provided.