JPH06151862A - Insulated gate bipolar transistor - Google Patents

Abstract

PURPOSE:To reduce a resistance component of a channel diffusion layer directly below source layers without increasing the switching loss of an IGBT and control a latchup and improve a reliability. CONSTITUTION:By connecting an emitter electrode 11 to source layers 5 through conductor films 10 inserted under interlayer insulating films 9 between gate electrodes 8, a length of the source layers 5 can be shortened without changing a thickness of the interlayer insulating films 9 and a resistance component of a channel diffusion layer 4 directly below the source layers 5 can be reduced. For example, a titanium silicide is used as a material of the conductor films 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a MOS on a semiconductor substrate.
The present invention relates to an insulated gate bipolar transistor (hereinafter referred to as an IGBT) capable of controlling a current flowing in a substrate depending on its structure.

[0002]

2. Description of the Related Art An IGBT is composed of a plurality of modules.
It is often used to configure
Characteristics and high reliability are required. Figure 2 shows a part of the upper layer
It is a perspective view of the IGBT chip which showed the cross section. In the figure
Where p becomes the collector layer⁺N on the silicon substrate 1
⁺N by epitaxial growth via the buffer layer 2^-
Layer 3 is laminated, this n^-P-type selectively on the surface layer of layer 3
Channel diffusion layer 4 is formed. Furthermore, this tea
Selectively n on the surface layer of the flannel diffusion layer 4.⁺Source layer 5 is formed
And this n⁺Layers 5 and n^-Sandwiched between exposed parts of layer 3
Using the portion 6 of the channel diffusion layer 4 as a channel region,
P over the gate insulating film 7⁺From the polycrystalline silicon layer
And the gate electrode 8 connected to the gate terminal G is provided.
Has been. The gate electrode 8 is insulated from the interlayer insulating film 9.
The emitter electrode 11 is a p-layer 4 and an n-type⁺Commonly connected to layer 5
It is touched and connected to the emitter terminal E. On the other hand, p⁺Ko
The collector layer 1 is connected to the collector terminal C.
Pole 12 is touching. Figure 3 is an equivalent circuit diagram of this IGBT.
At p⁺Layers 1 and n⁺Layers 2 and n^-Layer 3 and p layer 4
PNP bipolar transistor 31, n⁺Layers 2 and n
^-Layer 3 and p layer 4 and n⁺NPN bipolar consisting of layer 5
Transistor 32 and n^-Layer 3, p layer 4, n ⁺Layer 5
And MOSFET 33 consisting of gate electrode 8 are combined
It was the one. Switch to speed up the IGBT
The following method is known to control the ringing time.

(1) As the chip size becomes larger, the depletion layer becomes larger and the switching time becomes slower, so the chip size is made smaller. (2) Diffusion of heavy metals or electron beam irradiation to shorten the lifetime. (3) The specifications are changed by increasing the resistivity of the n ⁻ layer 3 of the semiconductor substrate to reduce the thickness, or decreasing the resistivity of the n ⁺ layer 4 to reduce the thickness. The improvement of the reliability of the IGBT is achieved by suppressing the occurrence of latch-up. In the IGBT, a parasitic NPN transistor is generated from the n ⁺ layer 5, the p layer 4 and the n ⁻ layer 3, so that the NPN transistor is composed of the p ⁺ layer 1, the n ⁺ layer 2 and the n ⁻ layer 3 and the p layer 4. If a parasitic thyristor is formed together with a PNP transistor and this thyristor operates, the current flowing through the thyristor cannot be blocked even if the MOSFET 33 is turned off.
The IGBT runs hot and runs into destruction. This is generally called latch-up. In this latch-up, a large hole current flows in the p-channel diffusion layer 4 just below the n ⁺ layer 5, so that the voltage drop due to the resistance component in that portion causes the p-layer 4 and n ^+.
It occurs by raising the diffusion potential of the PN junction between layers 5.

Therefore, in order to improve the latch-up withstanding capability, the following method is known, in which the chip size is increased to make it difficult to break and the resistance component of the portion of the channel diffusion layer 4 immediately below the n ⁺ layer 5 is reduced. Has been. (1) The channel diffusion layer 4 is made high in impurity concentration and deepened. (2) A p ⁺ diffusion layer is formed in advance so as to overlap the portion of the channel diffusion layer 4 below the n ⁺ layer 5.

(3) After the channel diffusion layer 4 is formed as described in (2), the p ⁺ diffusion layer is formed therein again.

[0006]

[Problems to be Solved by the Invention] IG as shown in FIG.
When turning off the BT, the carrier is n^-Layers 3 to n
⁺Although it is ejected to layer 5, this carrier causes a tail charge.
A flow occurs. Fig. 4 shows the state, line 41 is voltage, line 42
Is the current and at turn-off the current 42 pulls the long tail 43
The loss 44 shown by hatching is large at turn-off.
I hear In order to suppress this tail current, heavy metal expansion
When collector or electron beam irradiation is performed, collector-emitter voltage V
_{CE (sat)}Variation, chip unit price and work man-hour increase
It Also, changing the chip size is economical and assembly work
Sex deteriorates, n⁺The channel diffusion layer 4 directly below the source layer 5
If it is made shallow to reduce the loss of the MOS part, it will latch up.
It becomes easier and the reliability decreases.

An object of the present invention is to solve the above problems and to provide an IGBT with high reliability by suppressing latch-up without increasing switching loss.

[0008]

In order to achieve the above object, a surface layer on the other side of a second layer of the first conductivity type is selectively formed on one side of which a first layer of the second conductivity type is in contact. A third layer of the second conductivity type and a fourth layer of the second conductivity type selectively formed on the surface layer of the third layer, the second layer exposed portion of the third layer and the fourth layer A gate electrode is provided on the exposed part sandwiched by an insulating film, the collector electrode is electrically connected to the first layer, and the gate electrode and the interlayer insulating film are insulated from the third layer and the fourth layer. IG in which the emitter electrodes are commonly electrically connected
In the BT, it is assumed that the emitter electrode is electrically connected to the fourth layer through the conductor film extending between the fourth layer and the interlayer insulating film and over the exposed portion of the third layer. The emitter electrodes are electrically connected to the third layer and the fourth layer at a plurality of locations on one semiconductor substrate, and the emitter electrodes are provided only at a location near the conductor bonding area for connecting the emitter electrodes to the outside. It is effective that the electrode is electrically connected to the fourth layer through the conductor film. Further, it is effective that the semiconductor is silicon and the conductor film is made of titanium silicide.

[0009]

In the conventional structure, in order to electrically connect the fourth layer to the emitter electrode, it was necessary to extend and expose the fourth layer to the portion where the interlayer insulating film was not present. On the other hand, by connecting the fourth layer and the emitter electrode via the conductor film, it is possible to connect to the emitter electrode even if the fourth layer is entirely under the interlayer insulating film, and the interlayer insulating film can be made thin. The fourth layer can be shortened without doing. As a result, the voltage drop in the third layer immediately below the fourth layer can be reduced by the shortening of the fourth layer, and the latch-up withstand capability can be improved. Such a structure is particularly effective by arranging it in the vicinity of the connecting portion between the emitter electrode and the conducting wire where latch-up easily occurs.

[0010]

FIG. 1 shows the vicinity of an emitter electrode contact portion of an IGBT according to an embodiment of the present invention, and the same parts as those in FIG. 2 are designated by the same reference numerals. This structure has p on the surface layer of the n ⁻ layer 3.
After forming the channel-shaped channel diffusion layer 4, the n ⁺ source layer 5 is formed by donor diffusion using the gate electrode 8 formed through the gate insulating film 7 and the resist film as a mask. Alternatively, the short n ⁺ source layer may be left by etching after forming the n ⁺ layer using only the gate electrode 8 as a mask. Next, the conductor film 10 is formed on the exposed surface of the gate electrode 8 and the silicon substrate, and the portions on the gate electrode 8 and the central portion of the exposed surface of the p layer 4 are removed by etching. After that, an interlayer insulating film 9 covering the gate electrode 8 is grown, and the exposed surface of the p layer 4 and
After forming a contact hole on a part of the TiSi ₂ film 10, an emitter electrode 11 is formed of Al and annealed at 150 to 200 ° C. The use of titanium silicide (TiSi ₂ ) as the conductor of the conductor film 10 has the advantages of withstanding this annealing and being easy to make ohmic contact with silicon, but a metal conductor may be applied.

FIGS. 6 and 7 are plan views showing the entire semiconductor substrate of the IGBT, and a large number of cell structures as shown in FIG. 1 or 2 are formed on the substrate 21, but the gate electrode 8 and the emitter electrode 9 are formed. The connection with the terminal is performed by bonding the Al conductive wire using the gate bonding pad 22 and the emitter bonding pad 23. In the embodiment of FIG. 6, the cell structure using the conductor film 10 as shown in FIG. 1 is applied to the entire surface of the substrate as shown by the shaded region 20.
In the embodiment shown in FIG. 7, the cell structure shown in FIG. 2 is applied only to the vicinity of the emitter bonding pad 23 where latch-up is likely to occur.

[0012]

According to the present invention, the emitter electrode and the source layer are connected to each other via the conductor film which penetrates under the interlayer insulating film of the gate electrode and the emitter electrode over the entire surface of the semiconductor substrate or a portion where latchup is likely to occur. By doing so, the source layer can be shortened without thinning the interlayer insulating film, the resistance component of the channel diffusion layer immediately below the source layer can be reduced, and the occurrence of latch-up can be suppressed.
As a result, an IGBT with improved reliability was obtained without increasing switching loss.

[Brief description of drawings]

FIG. 1 is a sectional view of the vicinity of an emitter electrode contact portion of an IGBT according to an embodiment of the present invention.

FIG. 2 is a perspective sectional view of a conventional IGBT.

FIG. 3 is an equivalent circuit diagram of the IGBT.

[Fig. 4] IGBT voltage, current, loss waveform diagram

FIG. 5 is a plan view of an IGBT semiconductor substrate according to an embodiment of the present invention.

FIG. 6 is a plan view of an IGBT semiconductor substrate according to another embodiment of the present invention.

[Explanation of symbols]

1 p ⁺ collector layer 2 n ⁺ buffer layer 3 n ⁻ layer 4 p-type channel diffusion layer 5 n ⁺ source layer 7 gate insulating film 8 gate electrode 9 interlayer insulating film 10 conductor film 11 emitter electrode 12 collector electrode

Claims (3)

[Claims] 1. A third layer of the second conductivity type selectively formed on a surface layer on the other side of the second layer of the first conductivity type, which is in contact with the first layer of the second conductivity type, and a third layer thereof. It has a fourth layer of the second conductivity type selectively formed on the surface layer of the three layers, and an insulating film is formed on the exposed portion sandwiched between the second layer exposed portion of the third layer and the fourth layer. A collector electrode is electrically connected to the first layer, and a gate electrode and an emitter electrode insulated by an interlayer insulating film are commonly electrically connected to the third layer and the fourth layer. In the insulated gate type, the emitter electrode is electrically connected to the fourth layer through a conductor film extending from between the fourth layer and the interlayer insulating film to above the exposed portion of the third layer. Bipolar transistor. 2. An emitter electrode is electrically connected to a third layer and a fourth layer at a plurality of points on one semiconductor substrate,
The emitter electrode is electrically connected to the fourth layer through a conductor film only in a portion in the vicinity of a wire bonding region for connecting the emitter electrode to the outside.
The insulated gate bipolar transistor described. 3. The insulated gate bipolar transistor according to claim 1, wherein the semiconductor is silicon and the conductor film is made of titanium silicide.