JPH08130249A - Semiconductor device - Google Patents

Abstract

PURPOSE: To obtain a semiconductor device having high breakdown strength in which a subcurrent caused by a reverse current upon interruption of an inductive load, e.g. a motor, and flowing through a parasitic NPN transistor to a semiconductor substrate can be reduced. CONSTITUTION: A metal layer 108 connected electrically with the source region 103 in an N type lateral double diffusion MOS transistor 180 is brought into direct contact with an N type diffusion layer 105 including a drain region 106 thus forming a Schottky barrier diode SBD. When the Schottky barrier diode SBD is conducted, subcurrent flowing into a P type semiconductor substrate 100 can be reduced and thereby heating of the semiconductor device can be suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device provided with a MOS transistor which can be preferably implemented to drive an inductive load such as a motor.

The term "N" or "P" in the claims, which indicates the conductivity type of a semiconductor, should be construed as a concept including high and low doped impurities. N ^+, N ^- also include,
“P” also includes P ⁺ and P ⁻ .

[0003]

2. Description of the Related Art FIG. 15 shows a conventional N-channel lateral type 2
FIG. 9 is a cross-sectional view showing the structure of a heavy diffusion MOS transistor 195. Horizontal double diffusion MOS transistor is abbreviated as LDM
OS (Lateral double Diffusion Metal Oxide Semicond
uctor) is also called. A P type diffusion layer 212 is formed in an N ⁻ well 211 formed on a P type semiconductor substrate 210, and an N ⁺ source region 213 is formed in the P type diffusion layer 212.
To form. An N type diffusion layer 214 is also formed in the N ⁻ well 211, and an N ⁺ drain region 215 is formed in the N type diffusion layer 214. N ⁺ source region 213
On the surface of the P-type diffusion layer 212 sandwiched between the gate electrode 216 and the N ⁻ well 211 via the gate oxide film 216g.
Is formed.

When a positive voltage is applied to the gate electrode 216, the channel region 217 near the surface of the P-type diffusion layer 212.
Is inverted to an N type to form an inversion layer, and a drain current IDN flows from the drain region 215 to the source region 213 through the inversion layer. When a negative voltage is applied to the gate electrode 216, the channel region 217 disappears and the N-channel lateral double diffusion MOS transistor 195 is cut off.

The P ⁺ diffusion region 218 serves as a back gate contact for the metal layer 21 connected to the source region 213.
9 is a P-type diffusion layer for making ohmic contact with the P-type diffusion layer 212. This P ⁺ diffusion region 218,
A parasitic PN junction type diode is formed by the N ⁺ drain region 215. N-channel lateral double diffusion MO
When the S transistor 195 is turned off, the reverse current IRN flows from the source to the drain, and the parasitic PN
The junction diode conducts and operates.

FIG. 16 is an electric circuit diagram of a so-called H-bridge motor drive circuit using the N-channel lateral double diffusion MOS transistor 195 shown in FIG. In this drive circuit, in order to drive the motor M which is an inductive load, the N-channel lateral double diffusion MOS transistor 195 shown in FIG.
4, a total of four are used and are electrically connected to form an H type including the motor M.
Connected to. These MOS transistors NM1 to N
Current paths flowing through M4 are denoted by reference numerals IA, IA1, IB,
There will be a total of 4 types of ICs. In the current paths IA and IA1,
A forward current flows in each of the MOS transistors NM1 to NM4, but in the current paths IB and IC, M
The currents flowing through the OS transistors NM2 and NM3 have opposite directions. This reverse current flows to the MOS transistor NM
2, NM3 parasitic PN junction type diodes ND2, ND3
Through the parasitic PN junction type diodes ND2 and ND3
Operates as a flywheel diode by bypassing the currents IB and IC. MOS transistors NM1 and N
The parasitic PN junction type diode of M4 is indicated by reference numerals ND1 and ND.
4.

When a gate signal from the control circuit is given, M
The OS transistors NM1 and NM4 are conductive, and the MOS
From the state where the transistors NM2, NM3 are cut off and the current path IA is formed, the MOS transistors NM1,
NM4 is cut off, and MOS transistors NM2 and NM
When the switch 3 is switched to a state in which the current path IA1 is formed, the parasitic PN junction diode ND 3 that functions as a flywheel diode by the motor M that is an inductive load.
2, a current path IB or IC is formed through ND3 and a current flows.

FIG. 17 is a sectional view showing a specific structure of the MOS transistors NM1 and NM2 included in the motor drive circuit shown in FIG. Parasitic P in FIG.
The N-junction type diodes ND1 to ND4 operate as flywheel diodes. When the parasitic PN junction type diode ND1 or ND3 in FIG. 16 conducts and operates, as shown in FIG. 17, the parasitic PNP transistor 2
61 conducts and operates. The MOS transistor N
The portion of M2 corresponding to the MOS transistor NM1 is shown with the same numeral with a suffix a, and a P ⁻ diffusion layer 262 is formed between these MOS transistors NM1 and NM2.

When the parasitic PNP transistor 261 becomes conductive, the sub-current IS to the P-type semiconductor substrate 210 is reached.
There is a problem that UB flows. Such sub-current I
Although it is conceivable to form an N ⁺ buried layer between the P-type semiconductor substrate 210 and the N ⁻ well 211 in order to reduce SUB, there is a problem in that the number of semiconductor manufacturing steps increases and the cost increases.

The parasitic PNP transistor 261 described above is also used.
If the sub-current ISUB that flows due to a large amount of heat is generated, heat generation of the semiconductor device becomes a problem. In order to reduce the amount of heat generation, a package having a low thermal resistance θja, that is, a high allowable heat loss PD is required, which requires a copper frame and a package with a heat dissipation fin, which causes a problem of increasing the cost of the package.

Another problem of the prior art shown in FIGS. 15-17 relates to switching efficiency. That is, MOS
The switching time when the transistor changes from the OFF state to the ON state is the reverse recovery time t of the flywheel diode formed by the parasitic PN junction type diode.
determined by rr. This reverse recovery time trr is a time required for the electrons of the minority carriers accumulated in the parasitic PN junction diode to be emitted, and is of the order of μsec, whereas the reverse recovery time of the MOS transistor is It is on the order of nsec, which is much shorter than the reverse recovery time of the parasitic PN junction diode. Since the reverse recovery time trr of the parasitic PN junction diode is long, the switching loss becomes significantly large as the switching frequency becomes high. Therefore, a PN junction type diode having a long reverse recovery time trr has a problem of large switching loss and poor switching efficiency.

In order to solve this problem, the parasitic P
When the switching operation of the MOS transistor is performed in a time shorter than the reverse recovery time trr of the N-junction diode, the parasitic PN junction diode operating as a bipolar element may cause thermal runaway and cause PN junction breakdown.

Therefore, in order to solve this problem, conventionally, an external diode is separately provided to the MOS transistor. In such a conventional method, an external diode is required, which obviously causes an increase in the number of parts and raises a new problem that the cost is increased.

In order to reduce the reverse recovery time trr of the parasitic PN junction type diode as described above, a heavy metal which is a lifetime killer is doped, or a carrier trap is formed in the crystal by irradiation with an electron beam or neutron. It has been traditional to introduce a lifetime killer by. In the method using the lifetime killer, the on-resistance of the MOS transistor becomes large, so that there is a process problem that the lifetime killer condition needs to be sufficiently optimized. In addition, there is a problem that it is difficult to optimize the lifetime killer condition because the leakage current of the MOS transistor increases and the threshold voltage fluctuates, which greatly affects the electrical characteristics.

After all, in the past, in order to solve the problem caused by the parasitic PN junction type diode as described above,
There is a problem that an external flywheel diode having a reverse recovery time shorter than that of the junction type diode must be used.

FIG. 18 is a sectional view showing the structure of a conventional P-channel lateral double-diffused MOS transistor 410. N ^- well 2 formed on P-type semiconductor substrate 220
An N-type diffusion layer 222 is formed in 21 and a P-type diffusion layer 222 is formed thereon.
^{+ A} source region 223 is formed. A P-type diffusion layer 224 is formed in the N ^- well 221, and a P-type diffusion layer 224 is further formed therein.
^{+ A} drain region 225 is formed. The N type diffusion layer 2 sandwiched between the P ⁺ source region 223 and the P type diffusion layer 224.
A gate electrode 226 is provided in the vicinity of the surfaces of the N ^- well 221 and the N ^- well 221 via a gate oxide film 226g.

In the P-channel lateral double-diffused MOS transistor 410, when a negative voltage is applied to the gate electrode 226, the channel region 227 near the surface of the N-type diffusion layer 222.
Are inverted to P-type to form an inversion layer, and the drain current IDP flows from the source region 223 to the drain region 225 through the inversion layer. When a positive voltage is applied to the gate electrode 226, the channel region 227 disappears and the P-channel lateral double diffusion MOS transistor 410 is cut off. The N ⁺ diffusion region 228 is an N ⁺ for the back gate contact.
It is a diffusion layer.

In the P-channel lateral double diffusion MOS transistor 410, the P ⁺ drain region 225 and the N ⁺ diffusion region 228 form a parasitic PN junction type diode. P-channel lateral double-diffused MOS transistor 410
When is turned off, a reverse current IRP flows from the drain to the source, and the parasitic PN junction type diode conducts and operates.

FIG. 19 is an electric circuit diagram of an H-bridge motor drive circuit for driving the motor M. The P-channel lateral double-diffused MOS transistor 410 shown in FIG.
The N-channel lateral double-diffused MOS transistor 195 used as shown by the MOS transistors PM1 and PM3 and shown in FIG. 15 is the MOS transistor NM.
2, used as indicated by NM4. The MOS transistors PM1 and NM2 are connected to a totem pole,
Similarly, the MOS transistors PM3 and NM4 are also connected to the totem pole to form a drive circuit for the motor M. In the motor drive circuit shown in FIG. 19 as well as the drive circuit shown in FIG.
IA1 allows a forward current to flow, and the current paths IB and Ic allow a reverse current to flow. At the time of switching from the current path IA to IA1, the above-mentioned parasitic PN junction type diode works as the flywheel diodes ND2 and PD3 to form the reverse current path IB or IC, and the reverse current flows. Flywheel diodes are also designated by the reference signs PD1, ND4.

FIG. 20 shows a specific configuration of the P-channel lateral double-diffused MOS transistor PM1 and the N-channel lateral double-diffused MOS transistor NM2 that form one of the totem pole connection structures in FIG. The parasitic PN junction type diode is used as the flywheel diodes PD1, PD3, ND2, ND4. For example, when the parasitic PN junction type diodes PD1, PD3 are operated in a conductive state, as shown in FIG.
The NP transistor 271 operates, and as a result, FIG.
As in the prior art described with reference to FIG. 17, there is a problem that the sub-current ISUB flows to the P-type semiconductor substrate 220. The larger the sub-current ISUB, the more problematic the heat generation of the semiconductor device of the present invention becomes. This is similar to the above-mentioned prior art. Further, the sub current ISUB flows and P
As the potential of the semiconductor substrate 220 rises,
There is also a problem that latch-up easily occurs.

Yet another prior art is shown in FIG. FIG. 21 is a cross-sectional view showing the structure of a conventional P-channel MOS transistor 350 that is well known. An N ⁻ well 231 is formed on the P type semiconductor substrate 230, and a P ⁺ source region 232 is formed inside the N ⁻ well 231.
And a P ⁺ drain region 233 are formed. In this P-channel MOS transistor 350, the gate electrode 234
N ^- well 23 directly under the gate oxide film 234g of
The vicinity of the surface of 1 becomes the channel region 235 by applying a negative voltage to the gate electrode 234. The N ⁺ diffusion region 236 is an N-type diffusion layer for back gate contact, and includes the P ⁺ drain region 233 and the N ⁺ diffusion region 23.
6 forms a parasitic PN junction type diode.

The P-channel MOS transistor 350 shown in FIG. 21 is replaced with the MOS of the motor drive circuit shown in FIG.
It can be used as the transistors PM1 and PM3,
The remaining MOS transistors NM2 and NM4 are
It can be configured by a channel lateral double diffusion MOS transistor 195. A specific configuration of one totem pole connection of such a motor drive circuit is shown in FIG. In FIG. 22, the MOS transistor PM1a
21 shows the P-channel MOS transistor 350 of FIG. In the conventional motor drive circuit similar to FIG. 19 having the configuration shown in FIGS. 21 and 22, the parasitic P of the P channel MOS transistor 350 is
When the N-junction diodes PD1 and PD3 conduct and operate, the parasitic PNP transistor 281 conducts and operates, and the sub-current ISUB flows into the P-type semiconductor substrate 230, as shown in FIG. The larger the sub-current ISUB, the more problematic the heat generation of the semiconductor device of the present invention. Further, the sub-current ISUB flows, the potential of the P-type semiconductor substrate 230 rises, and latch-up easily occurs. Such a problem is similar to the above-mentioned prior art.

Still another prior art is Japanese Patent Laid-Open No. 3-782.
No. 54 publication. In the above publication, the P-channel MO having the normal structure shown in FIGS.
In order to improve the latch-up resistance of the S transistor, N
There is disclosed a configuration in which a Schottky barrier diode is formed between a drain and an N-type semiconductor substrate in a P-channel MOS transistor formed on a type semiconductor substrate. The problem with this prior art is that it is difficult to increase the breakdown voltage. On the N-type semiconductor substrate in this prior art, a P ⁺ diffusion layer is first formed, and then a drain and a source region are further formed, whereby a P channel MO is formed.
An S transistor is formed. Withstand pressure control
Since it is determined only by the impurity concentration of the P ⁺ region in contact with the N type semiconductor substrate, there is a big problem that there is a limit in controlling the junction breakdown voltage between the N type semiconductor substrate and the P ⁺ diffusion layer. Therefore, this prior art is not suitable for increasing the breakdown voltage.

[0024]

SUMMARY OF THE INVENTION The object of the present invention is to solve the problems of each of the above-mentioned prior arts and to easily achieve a high breakdown voltage.
By providing an improved semiconductor device that prevents adverse effects caused by a parasitic MOS transistor operating and flowing a sub current ISUB, improves latch-up withstanding capability, and eliminates the need for an external flywheel diode having a short reverse recovery time. is there.

[0025]

According to the present invention, a first semiconductor layer, which is a well formed on a semiconductor substrate, has either a drain region or a source region of a conductivity type different from that of the first semiconductor layer of a MOS transistor. One of the second semiconductor layers is formed, and the metal layer electrically connected to the second semiconductor layer is connected to the first semiconductor layer, so that the MOS
A semiconductor device having a Schottky barrier diode formed in parallel with a transistor. Further, according to the present invention, the channel region of the P-type second semiconductor layer is formed in the N-type first semiconductor layer formed on the P-type semiconductor substrate,
The source region of the N-type first semiconductor layer formed in the channel region and the N formed in the N-type first semiconductor layer
Forming a N-channel lateral double-diffused MOS transistor having a drain region of the first semiconductor layer and a gate electrode provided on the channel region through a gate oxide film, and electrically connected to the source region The semiconductor device is characterized in that a Schottky barrier diode is formed in parallel with the MOS transistor by connecting the layer to the N-type first semiconductor layer in the drain region. Further, according to the present invention, in the N-type first semiconductor layer formed on the P-type semiconductor substrate, a channel region having the same conductivity type and an impurity concentration lower than that of the N-type first semiconductor layer is formed. And a drain region of the P-type second semiconductor layer formed in the N-type first semiconductor layer, and a channel region through the gate oxide film. P-channel lateral double-diffused MOS with gate electrode
A Schottky barrier diode parallel to the MOS transistor is formed by forming a transistor and connecting a metal layer electrically connected to the drain region to the N-type first semiconductor layer in the source region. And a semiconductor device. The present invention also provides a source region of the P-type second semiconductor layer, a drain region of the P-type second semiconductor layer, and a gate oxide provided in the N-type first semiconductor layer formed on the P-type semiconductor substrate. A P-channel MOS transistor having a gate electrode provided on a channel region extending over a source region and a drain region via a film is formed, and a metal layer electrically connected to the drain region is connected to the N-type first semiconductor layer. By doing so, a Schottky barrier diode is formed in parallel with the MOS transistor, which is a semiconductor device.

[0026]

According to the present invention, the first semiconductor layer which is a well is formed on, for example, a P-type silicon semiconductor substrate, and either the drain region or the source region of the MOS transistor is formed in the first semiconductor layer. And, for example, N
A second semiconductor layer, which is a type diffusion layer, is formed, and the metal layer electrically connected to the second semiconductor layer forms a barrier metal layer with the first semiconductor layer to form a Schottky connection part.
The Schottky barrier diode thus formed is
It is formed in parallel with the MOS transistor, and when the MOS transistor is turned off, an inductive load such as a motor causes a primary forward bias to flow a reverse current. The reverse recovery time of this Schottky barrier diode is sufficiently shorter than that of the above-mentioned parasitic PN junction type diode, and moreover, the forward voltage VF of the Schottky barrier diode.
Is clamped to 0.2 to 0.3V, which is sufficiently smaller than the forward voltage of 0.7V of the parasitic PN junction diode. Therefore, when the inductive load is cut off, the current that primarily flows in the opposite direction to the MOS transistor flows to the Schottky barrier diode, and the sub-current that flows to the semiconductor substrate of P type or the like is reduced to a sufficiently small level. That is,
Base-emitter voltage VBE of parasitic PNP transistor
Is, for example, 0.7 V, so that the Schottky barrier diode is rendered conductive before the parasitic PNP transistor is rendered conductive by the reverse current, and the sub-current to the semiconductor substrate can be reduced. Since the sub-current can be reduced in this way, heat generation of the semiconductor device of the present invention can be reduced, latch-up can be avoided, and an external flywheel diode with a short reverse recovery time must be provided. Disappears.

Further, according to the present invention, a combination of the impurity concentration of the first semiconductor layer, which is an N ⁻ well, and the impurity concentration of the second semiconductor layer, which is P or P ⁺ having a higher impurity concentration than that, is combined. Thus, the breakdown voltage of the PN junction can be easily controlled by forming the semiconductor substrate, and the breakdown voltage can be easily increased.

According to the present invention, N-channel and P-channel lateral double-diffused MOS transistors can be realized, and a normal P-channel MOS transistor can also be realized.

[0029]

1 is a sectional view of an N-channel lateral double-diffused MOS transistor 180 according to an embodiment of the present invention.
FIG. 2 is a simplified plan view of the MOS transistor 180. A cross section taken along the section line X1-X2-X3 in FIG. 2 is shown in FIG. The P-type silicon semiconductor substrate 100 has an N-channel lateral double-diffused MOS transistor 180.
Is configured. On this P-type semiconductor substrate 100, an N ^- well 101 in which the P-type semiconductor substrate 100 is partially used as an N-type diffusion layer is formed. In this well 101, a P-type diffusion layer 102 and an N-type diffusion layer 105 are formed. P
In the type diffusion layer 102, the source region 1 which is an N ⁺ diffusion layer is formed.
03 is formed, and the P ⁺ diffusion layer 104 for the back gate contact is formed. In the N type diffusion layer 105, a drain region 106 which is an N ⁺ diffusion layer is formed. The gate electrode 107 made of polysilicon has at least the P-type diffusion layer 102 via the gate oxide film 107g.
It is provided on the surface. A metal layer 108 of aluminum or the like is formed in the source region 103 to serve as a source electrode. A metal layer 109 of aluminum or the like is formed on the drain electrode 106 to serve as a drain electrode. The P ⁺ diffusion layer 104 and the metal layer 108 are electrically connected by the source / back gate contact 112, and the drain region 106 and the metal layer 109 are connected to the drain contact 1.
It is electrically connected by 11. According to the present invention, the metal layer 108 electrically connected to the source region 103 is
A metal barrier layer is formed by making direct contact with the N-type diffusion layer 105 including the drain region 106, and a Schottky barrier diode SBD is formed.

The Schottky barrier diode SBD
As shown in FIG.
82 through the metal layer 108 of the source region 1
03, and the cathode 183 is the N-type diffusion layer 1
05 is connected. Thus, the Schottky barrier diode SBD has a structure connected in parallel to the N-channel lateral double-diffused MOS transistor 180. Furthermore, an N-channel lateral double-diffused MOS transistor 180
A parasitic PN junction type diode 184 is connected in parallel with this.

FIG. 3 shows the N-channel lateral type 2 shown in FIG.
M having the same configuration as the heavy diffusion MOS transistor 180
A motor drive circuit for driving a motor M using the OS transistor 180a and using N-channel lateral double diffusion MOS transistors 185, 185a in which the Schottky barrier diode SBD is not formed is shown. The MOS transistors 180 and 185 are connected to the totem pole,
Further, the MOS transistors 180a and 185a are similarly totem-pole connected and connected to the DC power supply VM. M
Portions of the OS transistors 180a and 185a that correspond to the MOS transistors 180 and 185 are indicated by the same numbers with a subscript a. MOS transistor 18
0, 185a is turned on to drive the motor M, and the MOS transistors 180a, 185 are cut off at this time. When a reverse current flows through the motor M, the MOS transistor 180a, 185 is turned off.
Transistors 180a and 185a are turned on, and MOS transistors 180 and 185a are turned off.

FIG. 4 is a sectional view showing a specific structure of the MOS transistors 180 and 185 in the motor drive circuit shown in FIG. Although the Schottky barrier diode SBD is not formed in the MOS transistor 185 in this embodiment, as another embodiment, the MOS transistors 185 and 185a have the same structure as the MOS transistors 180 and 180a having the structure shown in FIG. It may be. A P ⁻ diffusion layer 199 is formed between the MOS transistor 180 and the MOS transistor 185.

During operation of the motor drive circuit, for example, MOS
At the time when the transistors 180 and 185a are turned off from the conductive state, the parasitic PNP transistor in the MOS transistor 180 becomes conductive and operates, but most reverse current flows through the Schottky barrier diode SBD rather than through the parasitic PN junction type diode. ,
Sub-current to the P-type semiconductor substrate 100 due to the parasitic PNP transistor is reduced. In addition, the minority carrier electrons are less accumulated by the parasitic PN junction diode, and the reverse recovery time is shortened.

As described above, according to this embodiment, in the N-channel lateral double-diffused MOS transistor 180, the metal layer 108 electrically connected to the source region 103 and the N-type diffusion layer 105 including the drain region 106 are also included. Shutkey barrier diode SBD by being electrically connected
Is formed, it is possible to reduce the sub-current flowing to the semiconductor substrate due to the conduction of the parasitic PN junction diode and the parasitic PNP transistor.
Heat generation of the transistor 180 can be suppressed. Therefore, it becomes easy to take measures against heat, and it becomes possible to downsize the device and use an inexpensive package in which the allowable loss PD is not so high. Moreover, since the sub-current is reduced, the occurrence of latch-up can be suppressed. Furthermore, since the Schottky barrier diode SBD is capable of high-speed switching, an external flywheel diode is unnecessary.

FIG. 5 is a sectional view of a P-channel lateral double-diffused MOS transistor 190 according to another embodiment of the present invention, and FIG. 6 is a simplified plan view of the embodiment of the MOS transistor 190. Section plane line X4-X5-X in FIG.
The cross section as seen from 6 is shown in FIG. In this embodiment, the P-channel lateral double-diffused MOS transistor 190 is formed on the P-type semiconductor substrate 120. This semiconductor substrate 12
An N ⁻ well 121 is formed on 0. In the well 121, the N-type diffusion layer 122 and the P-type diffusion layer 12 are provided.
5 is formed. A source region 123, which is a P ⁺ diffusion layer, is formed in the base region 122, and an N ⁺ diffusion layer 124 for back gate contact is also formed. P
A drain region 126, which is a P ⁺ diffusion layer, is formed in the type diffusion layer 125.

Gate electrode 127 made of polysilicon
Is provided on the surface of the N-type diffusion layer 121 including at least the base region 122 via the gate oxide film 127g.
A source / back gate contact 132 is formed in the source region 123 and the N ⁺ diffusion layer 124, and the metal layer 128 is electrically connected to the source / back gate contact 132 to serve as a source electrode. Further, a drain contact 131 is formed in the drain region 126,
The metal layer 129 is electrically connected to the drain contact 131 to serve as a drain electrode.

According to the present invention, the metal layer 129 serving as the drain electrode is directly contacted with the N-type diffusion layer 122 including the source region 123, and the Schottky barrier diode SBD is formed.
Is formed. Schottky barrier diode SBD
The metal layer 129 side is the anode, and the N-type diffusion layer 12
The second side is the cathode.

FIG. 7 uses a MOS transistor 190a having the same structure as the P-channel lateral double-diffused MOS transistor 190 shown in FIGS. 5 and 6, and uses the N-channel lateral 2 as shown in FIG. A drive circuit of a motor M using a heavy diffusion MOS transistor 195 and a MOS transistor 195a having the same configuration is shown. Corresponding portions of the MOS transistors 190 and 195 in the MOS transistors 190a and 195a are shown with a subscript a.

FIG. 8 is a sectional view showing a specific structure of the MOS transistors 190 and 195 in the drive circuit shown in FIG. A P ⁻ diffusion layer 198 is formed between the MOS transistor 190 and the MOS transistor 195. Although the MOS transistor 195 is an N-channel lateral double diffusion MOS transistor in which no Schottky barrier diode is formed, the N-channel MOS transistor 195 including the Schottky barrier diode SBD shown in FIG.
The channel lateral double diffusion MOS transistor 195 may be used.

As described above, also in the P-channel lateral double-diffused MOS transistor 190 of this embodiment, the N-type diffusion layer 122 including the metal layer 129 and the source region 123 is formed.
Since the Schottky barrier diode SBD is formed by and, it is possible to obtain the same effect as that of the first embodiment described above.

FIG. 9 shows a normal P which is another embodiment of the present invention.
FIG. 11 is a cross-sectional view of the channel MOS transistor 310, and FIG. 10 is a simplified plan view of the MOS transistor 310. P-channel MO shown in FIGS. 9 and 10.
The S transistor 310 can be used instead of the MOS transistors 190 and 190a of the drive circuit shown in FIG.
10 is an N-channel lateral double-diffused MOS shown in FIG.
It is used together with the transistors 195 and 195a to form a drive circuit for the motor M. Such FIG. 9 and FIG.
P channel MOS transistor 310 and N shown in FIG.
The combined structure with the channel lateral double diffused MOS transistor 195 is shown in FIG. FIG. 9 is a sectional view taken along the section line X7-X8-X9 in FIG. Referring to these drawings, an N ⁻ well 141 is formed on a P-type silicon semiconductor substrate 140, and the N ⁻ well 14 is formed.
In 1, together with the source region 142 is a P ⁺ diffusion layer is formed, it is formed a drain region 144 is a P ⁺ diffusion layer, further N ⁺ diffusion layer 143 for the back gate contact is formed. A gate electrode 145 made of polysilicon is formed on the surface of the N ^- well 141 via a gate oxide film 145a. Source regions 142 and N
^A source / back gate contact 148 is formed in the ⁺ diffusion layer 143, and a gold layer 146 of aluminum or the like is provided to serve as a source electrode. In addition, the drain region 14
4, a drain contact 149 is formed and a metal layer 147 such as aluminum is provided to serve as a drain electrode.

According to the present invention, the metal layer 147 electrically connected to the drain region 144 is directly contacted with the N ^- well 141 in the source region to form the Schottky barrier diode SBD. The Schottky barrier diode SBD is a P-channel MOS transistor 31.
0 side by side, the metal layer 147 side serves as an anode, and the N ⁻ well 141 side corresponds to a cathode.

As described above, also in the P-channel MOS transistor 310 in this embodiment, since the Schottky barrier diode SBD is formed by the metal layer 147 and the N ^- well 141, the same effect as in the first embodiment described above. Can be obtained.

FIG. 12 is a sectional view of a P-channel MOS transistor 290 according to another embodiment of the present invention, and FIG. 13 is a simplified plan view of the MOS transistor 290. FIG. 12 is a sectional view taken along the section line X11-X14 in FIG. P channel MOS transistor 290 shown in FIGS. 12 and 13 is equivalent to MOS transistor 19 in the motor drive circuit shown in FIG.
It is used instead of 0,190a. A configuration in which the P-channel MOS transistor 290 shown in FIGS. 12 and 13 having one totem pole structure in FIG. 7 and the N-channel lateral double-diffused MOS transistor 195 are connected is specifically shown in FIG. Has been done.

An N ^- well 161 is formed on the P-type silicon semiconductor substrate 160 of FIG. In the N ^- well 161, a source region 162 which is a P ⁺ diffusion layer is formed, and an N for a back gate contact is formed.
^{A +} diffusion layer 163 is formed, a metal layer 166 is connected to the source region 162 and the N ⁺ diffusion layer 163 to form a source electrode, and the metal layer 166 forms a back gate contact with the N ⁺ diffusion layer 163. A drain region 164, which is a P ⁺ diffusion layer, is also formed in the N ⁻ well 161, and a metal layer 167 is connected thereto to serve as a drain electrode. A gate electrode 165 made of polysilicon is formed on the surface of the N ^- well 161 via a gate oxide film 165a.

As described above, also in the P-channel MOS transistor 290 in this embodiment, since the Schottky barrier diode SBD is formed by the metal layer 166 and the N ^- well 161, the same effect as in the above-mentioned first embodiment is obtained. Can be obtained.

[0047]

As described above, according to the present invention, the Schottky barrier diode can be built in parallel to the MOS transistor. Therefore, before the parasitic PN junction type diode and the parasitic PNP transistor are turned on, the Schottky barrier diode is turned on. Since the barrier diode becomes conductive, the sub-current to the semiconductor substrate can be reduced, so that the heat generation of the semiconductor device of the present invention can be reduced, the latch-up can be avoided, and the latch-up design is easy. Since it is possible to realize an integrated circuit with low power consumption and generate less heat, it is possible to mount the semiconductor device in a small and low-priced package, simplify thermal design, and achieve high-speed switching. It will be possible. Furthermore, an external diode having a short reverse recovery time becomes unnecessary.

Further, according to the present invention, the combination of the concentration of doped impurities of the first semiconductor layer, which is a well formed on the semiconductor substrate, and the second semiconductor layer formed therein is set to a desired value. It is easy to select and control the withstand voltage of the PN junction, so that an excellent effect that a high withstand voltage can be easily achieved is also achieved.

[Brief description of drawings]

FIG. 1 is a sectional view of an N-channel lateral double-diffused MOS transistor 180 which is an embodiment of the present invention.

FIG. 2 is an N-channel lateral double-diffused MOS shown in FIG.
6 is a simplified plan view of a transistor 180. FIG.

FIG. 3 is an N-channel lateral double-diffused MOS transistor 1
It is an equivalent circuit diagram of a motor drive circuit using 80, 180a and N channel lateral double diffusion MOS transistors 185, 185a.

FIG. 4 is a cross-sectional view showing a specific configuration of N-channel lateral double-diffused MOS transistors 180 and 185 in the motor drive circuit shown in FIG.

FIG. 5 is a sectional view of a P-channel lateral double-diffused MOS transistor 190 according to another embodiment of the present invention.

FIG. 6 is a P-channel lateral double-diffused MOS shown in FIG.
4 is a simplified plan view of a transistor 190. FIG.

FIG. 7 is a P-channel lateral double-diffused MOS transistor 1
90 is an equivalent circuit diagram of a motor drive circuit using 90, 190a and N-channel lateral double diffusion MOS transistors 195, 195a. FIG.

8 is an MO constituting the motor drive circuit shown in FIG. 7.
3 is a cross-sectional view showing a specific configuration of S transistors 190 and 195. FIG.

FIG. 9 is a normal P channel M according to another embodiment of the present invention.
6 is a cross-sectional view of an OS transistor 310. FIG.

10 is a simplified plan view of P-channel MOS transistor 310 shown in FIG.

11 is a sectional view showing a specific configuration of a motor drive circuit using a P-channel MOS transistor 310 and an N-channel lateral double-diffused MOS transistor 195. FIG.

FIG. 12 is a P channel MOS according to another embodiment of the present invention.
FIG. 9 is a cross-sectional view of a transistor 290.

13 is a simplified plan view of P-channel MOS transistor 290 shown in FIG.

FIG. 14 is a sectional view showing a specific configuration of a motor drive circuit using a P-channel MOS transistor 290 and an N-channel lateral double-diffused MOS transistor 195.

FIG. 15 is an N-channel lateral double-diffused MO according to the prior art.
9 is a cross-sectional view of an S transistor 195.

16 is an N-channel lateral double diffusion M shown in FIG.
It is an equivalent circuit diagram of a motor drive circuit using an OS transistor 195.

17 is a cross-sectional view showing a specific configuration of part of the motor drive circuit shown in FIG.

FIG. 18 is a P-channel lateral double diffusion M in the prior art.
3 is a cross-sectional view of an OS transistor 410. FIG.

FIG. 19 is a P-channel lateral double diffusion M shown in FIG.
FIG. 16 is an equivalent circuit diagram of a motor drive circuit using an OS transistor and an N-channel lateral double-diffused MOS transistor shown in FIG. 15.

20 is a cross-sectional view showing a specific configuration of part of the motor drive circuit shown in FIG.

FIG. 21 is a sectional view showing the structure of still another conventional P-channel MOS transistor 350.

22 is a sectional view showing a specific configuration of part of a motor drive circuit using the P-channel MOS transistor 350 shown in FIG. 21 and the N-channel lateral double-diffused MOS transistor 195 shown in FIG. is there.

[Explanation of symbols]

100 P-type semiconductor substrate 101 N ^- well 102 P-type diffusion layer 103 Source region 104 P ⁺ diffusion layer 105 N-type diffusion layer 106 Drain region 107 Gate oxide film 108, 109 Metal layer 111 Drain contact 112 Source / back gate contact 180 N Channel lateral double diffused MOS transistor 190 P channel lateral double diffused MOS transistor 310 P channel MOS transistor SBD Schottky barrier diode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 29/78 301 C

Claims (4)

[Claims] 1. A second semiconductor layer, which is one of a drain region and a source region of a conductivity type different from that of the first semiconductor layer of a MOS transistor, is formed in a first semiconductor layer which is a well formed on a semiconductor substrate. A semiconductor device, wherein the formed metal layer electrically connected to the second semiconductor layer is connected to the first semiconductor layer to form a Schottky barrier diode in parallel with the MOS transistor. 2. An N-type first formed on a P-type semiconductor substrate
A channel region of the P-type second semiconductor layer is formed in the semiconductor layer, and a source region of the N-type first semiconductor layer formed in the channel region and the N-type first semiconductor layer are formed. Was N
Forming a N-channel lateral double-diffused MOS transistor having a drain region of the first semiconductor layer and a gate electrode provided on the channel region through a gate oxide film, the metal being electrically connected to the source region The layer being connected to the N-type first semiconductor layer at the drain region,
A semiconductor device having a Schottky barrier diode formed in parallel with an OS transistor. 3. An N-type first formed on a P-type semiconductor substrate
In the semiconductor layer, the same conductivity type and N-type impurity concentration
A channel region lower than the semiconductor layer is formed, and a source region of the P-type second semiconductor layer formed in the channel region and a drain of the P-type second semiconductor layer formed in the N-type first semiconductor layer Forming a P-channel lateral double-diffused MOS transistor having a region and a gate electrode provided on the channel region via a gate oxide film, and the metal layer electrically connected to the drain region is N-type in the source region. By being connected to the first semiconductor layer, M
A semiconductor device having a Schottky barrier diode formed in parallel with an OS transistor. 4. An N type first formed on a P type semiconductor substrate.
A source region of the P-type second semiconductor layer provided in the semiconductor layer, a drain region of the P-type second semiconductor layer, and a gate provided on a channel region extending over the source region and the drain region via a gate oxide film. P-channel MO with electrodes
A semiconductor characterized in that a Schottky barrier diode is formed in parallel with the MOS transistor by forming an S transistor and connecting a metal layer electrically connected to the drain region to the N-type first semiconductor layer. apparatus.