JPH06151755A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To provide a stacked DRAM of memory cell structure high in resistance to soft errors, wherein an ONO film as a capacitor insulating film is enhanced in reliability. CONSTITUTION:In a stacked DRAM memory cell, a charge storage node is of three-layered structure composed of an arsenic-doped polycrystalline silicon layer 10a as a lower layer, a phosphorus-doped polycrystalline layer 10b as an upper layer, and an insulating film 11 interposed between the polycrystalline silicon layers 10a and 10b. The polycrystalline silicon layers 10a and 10b are electrically connected together through the intermediary of a phosphorus-doped polycrystalline silicon side wall 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
For example, it relates to the structure of a stack type DRAM memory cell.

[0002]

2. Description of the Related Art A conventional stacked DRAM memory cell generally has a structure shown in FIG. In FIG.
1 is a P-type silicon substrate, 2 is an element isolation insulating film, 3 is a transfer gate electrode, 4 is a charge storage node, 5 is a capacitive insulating film, 6 is a plate electrode, 7 and 17 are interlayer insulating films, 8
Is a bit line, and 9 is a source / drain diffusion layer.

A polycrystalline silicon layer is usually used as a material for the charge storage node 4, and in order to make ohmic contact with the drain diffusion layer 9 of the transfer gate transistor, an impurity of the same conductivity type as the drain diffusion layer 9 is used. Is doped. Here, since the drain diffusion layer 9 is generally N-type, the case will be described as an example.

The most severe requirement for the characteristics of DRAM is that the reliability of the capacitance insulating film 5 formed on the charge storage node 4 is sufficient. Therefore, in order to improve the reliability of the capacitance insulating film 5, the charge storage node 4 is doped with phosphorus, the grain size (crystal grain size) of the charge storage node 4 is increased to smooth the surface, and then the capacitance insulation film 5 is formed. 5
(Normally, ONO film) is formed.

However, the phosphorus doped in the charge storage node 4 is diffused into the drain diffusion layer 9 by the heat treatment at the time of forming the capacitance insulating film 5 or after that, and the junction depth of the drain diffusion layer 9 is increased. Resulting in.

On the other hand, since the drain diffusion layer 9 functions as a node of the memory cell, it is advantageous that the junction depth is smaller because the trapping cross-section area of α-rays is reduced as a measure against soft error. Therefore, recently, arsenic instead of phosphorus has been used as a doping impurity of the charge storage node 4.

[0007]

Conventionally, the charge storage node 4 was doped with arsenic as a countermeasure against the soft error as described above. In this case, however, the capacitance insulation formed on the charge storage node 4 is prevented. The film quality of the film 5 deteriorates, and TDDB (Time
There was a problem that the Dependent Dielectric Breakdown) characteristic was deteriorated and the reliability was remarkably reduced as compared with the case of doping with phosphorus.

Therefore, an object of the present invention is to provide a semiconductor memory device having a memory cell structure having a highly reliable capacitive insulating film and having soft error resistance.

[0009]

In order to solve the above problems, the present invention provides a transistor having a second conductivity type diffusion layer on a first conductivity type semiconductor substrate and one of the second conductivity type diffusion layer. In a semiconductor memory device having a memory cell composed of a charge storage node connected to the charge storage node and a plate electrode formed on the charge storage node via a capacitive insulating film, the charge storage node is a first-type second conductivity type. A polycrystalline silicon layer doped with a type impurity, an insulating film, and a polycrystalline silicon layer doped with an impurity of the second type second conductivity type are sequentially stacked, and a second conductivity type is formed on a sidewall portion of the charge storage node. It has a sidewall made of a polycrystalline silicon layer doped with impurities.

[0010]

In the present invention, since the capacitive insulating film is formed on the polycrystalline silicon layer doped with phosphorus as the second type second conductivity type impurity, for example, it is possible to provide a highly reliable and good capacitive insulating film. Since the drain diffusion layer which is the second conductivity type diffusion layer is in contact with the polycrystalline silicon layer doped with, for example, arsenic as the first type second conductivity type impurity,
The junction depth can be kept shallow even if arsenic diffuses into the substrate by heat treatment or the like.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a stack type DRAM memory cell will be described below with reference to FIGS.
FIG. 1 shows the structure of this embodiment, which is shown in FIG.
FIG. 2C and FIG. 2 show the manufacturing process. In addition, in the embodiment of FIGS. 1 to 3, the same reference numerals are given to the components corresponding to those of the conventional example shown in FIG.

First, as shown in FIG. 2A, a transfer gate electrode 3 made of a polycrystalline silicon layer is formed on a P-type silicon substrate 1, and an N-type source / drain diffusion layer 9 is formed.

Next, as shown in FIG. 2B, a polycrystalline silicon layer 10a, which is a lower layer portion of the charge storage node, is deposited on the entire surface by a CVD method to a thickness of about 1500 to 2000Å, and this polycrystalline silicon layer 10a is deposited. The layer 10a is doped with arsenic by an ion implantation method at an energy of about 75 kev and a dose amount of about 5 × 10 ¹⁵ cm ⁻² , and then heat treatment is performed.

Next, as shown in FIG. 2C, dry O is deposited on the arsenic-doped charge storage node polycrystalline silicon layer 10a.
₂ Thermal oxidation is performed in an atmosphere to form an insulating film 11 having a film thickness of about 100 to 200Å, and a polycrystalline silicon layer serving as an upper layer portion of a charge storage node is deposited on the insulating film 11 by a CVD method, This is doped with phosphorus to form a phosphorus-doped charge storage node polycrystalline layer 10b.

Next, after patterning the photoresist film 12, the photoresist film 12 is used as a mask to form the phosphorus-doped charge storage node polycrystalline silicon layer 10b, the insulating film 11, and the arsenic-doped charge storage node polycrystalline silicon layer 10.
Anisotropic dry etching is performed on a and patterning is sequentially performed in a self-aligned manner. The insulating film 11 is for regionally separating the arsenic-doped charge storage node polycrystalline silicon layer 10a and the phosphorus-doped charge storage node polycrystalline silicon layer 10b.

Next, as shown in FIG. 3A, after the photoresist film 12 is removed, 2000 to 3000 Å is formed on the entire surface.
CVD of a phosphorus-doped polycrystalline silicon layer 13 of about thickness
3B, anisotropic dry etching is performed, and as shown in FIG. 3B, the sidewall 13 is formed.
To form a phosphorus-doped charge storage node polycrystalline silicon layer 10b and an arsenic-doped charge storage node polycrystalline silicon layer 1
0a is electrically connected.

Next, as shown in FIG. 3C, a capacitive insulating film 14 such as an ONO film and a plate electrode 15 made of a polycrystalline silicon layer are sequentially formed. Then, as shown in FIG. 1, the interlayer insulating film 16 is deposited by the atmospheric pressure CVD method, and the bit contact 1 is formed on the interlayer insulating film 16 on the source diffusion layer 9.
Bit line 8 by opening 6a and embedding aluminum wiring
To form.

[0018]

As described above, according to the present invention,
Since the capacitor insulating film is formed on the polycrystalline silicon layer doped with the second-type second-conductivity-type impurity, for example, phosphorus, a high-quality capacitor insulating film having high reliability can be provided, while the second-conductivity-type diffusion layer is provided. Since the drain diffusion layer, which is a contact layer, is contacted with a polycrystalline silicon layer doped with, for example, arsenic, which is a first-type second conductivity type impurity, even if arsenic in the polycrystalline silicon layer diffuses to the substrate side, a shallow junction is formed. The memory cell structure can be formed and is resistant to soft errors. Further, the present invention is effective not only for the stack type DRAM memory cell but also for the stack trench type DRAM memory cell.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a stack type DRAM memory cell according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of the memory cell of FIG.

FIG. 3 is a cross-sectional view showing a manufacturing process of the memory cell of FIG.

FIG. 4 is a sectional view showing a configuration of a conventional stack type DRAM memory cell.

[Explanation of symbols]

 1 Silicon Substrate 9 Source / Drain Diffusion Layer 10a Arsenic-Doped Charge Storage Node Polycrystalline Silicon Layer 10b Phosphorus-Doped Charge Storage Node Polycrystalline Silicon Layer 11 Insulating Film 13 Sidewall 14 Capacitive Insulating Film 15 Plate Electrode

Claims (1)

[Claims] 1. A transistor having a second conductivity type diffusion layer on a first conductivity type semiconductor substrate, a charge storage node connected to one of the second conductivity type diffusion layers, and a capacitive insulating film on the charge storage node. In a semiconductor memory device having a memory cell composed of a plate electrode formed via a conductive layer, the charge storage node is a polycrystalline silicon layer doped with an impurity of the first type second conductivity type, an insulating film and a second type. A polycrystalline silicon layer doped with a second conductivity type impurity is sequentially stacked, and a sidewall made of a polycrystalline silicon layer doped with a second conductivity type impurity is provided on a side wall portion of the charge storage node. A semiconductor memory device characterized by: