JPH06151475A - Charge transfer device and its manufacture - Google Patents

Abstract

PURPOSE:To increase the charge capacity of a charge transfer device by preventing the occurrence of a charge transferring defect. CONSTITUTION:In the title device 10, a first insulating layer 12 is formed on the entire surface of a semiconductor substrate 11 and first-layer gate electrodes 13 are formed on the surface of the layer 12, and then, the surfaces of the electrodes 13 are covered with a second insulating layer 14. Then second-layer gate electrodes 15 having hat-like cross sections are formed on the sides of the layer 14 and surface of the layer 12 and impurity diffusion areas 16 in which an impurity is diffused are formed below the electrodes 15 in the surface section of the substrate 11 so that each area 16 can have such an impurity concentration gradient that the concentration becomes lower in the charge transferring direction. In addition, the adjacent first-layer gate electrodes 13 and second-layer gate electrodes 15 are connected to each other through first or second wiring 17 or 18 and the two kinds of wiring 17 and 18 are alternately arranged.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge transfer device formed on a semiconductor substrate and a method for manufacturing the same.

[0002]

2. Description of the Related Art The structure of a conventional charge transfer device and a method of manufacturing the charge transfer device will be described below with reference to the drawings.
In the following, the charge carriers are described as electrons, but when the charge carriers are holes, the P-type and N-type of the semiconductor may be reversed.

FIG. 3A shows the structure of a conventional charge transfer device 50. In FIG. 3A, the first insulating layer 52 is formed over the entire surface of the semiconductor substrate 51, and the first-layer gate electrode 53 is formed on the surface of the first insulating layer 52. The second insulating layer 54 covers the surface of the gate electrode 53 of the second insulating layer 54, and a second-layer gate electrode 55 having a hat-shaped cross section is formed on the side surface of the second insulating layer 54 and the surface of the first insulating layer 52.
Is formed, and an impurity diffusion region 56 in which P-type impurities are diffused is formed below the second-layer gate electrode 55 in the surface portion of the semiconductor substrate 51. Further, the first-layer gate electrode 53 and the second-layer gate electrode 55 which are adjacent to each other are connected by a first wiring 57 or a second wiring 58,
Two types of first wiring 57 and second wiring 58 are arranged alternately.

FIG. 4 shows a method of manufacturing the above-mentioned conventional charge transfer device 50.

First, as shown in FIG. 4A, after forming a first insulating layer 52 over the entire surface of a semiconductor substrate 51, a first layer gate is formed on the first insulating layer 52. Electrode 53
To form.

Next, as shown in FIG. 4B, a P-type impurity is injected into the surface portion of the semiconductor substrate 51 from the direction of the arrow, that is, from above by using the gate electrode 53 of the first layer as a mask. An impurity diffusion region 56 in which P-type impurities are diffused is formed on the surface of 51.

Subsequently, as shown in FIG. 4C, a second insulating layer 54 is formed on the surface of the first-layer gate electrode 53,
Further, the side portion of the second insulating layer 54 and the first insulating layer 5
A second-layer gate electrode 55 is formed on the surface of No. 2. Then, the first-layer gate electrode 53 and the second-layer gate electrode 55 that are adjacent to each other are set as one set, and each set of the first-layer gate electrode 53
And the gate electrode 55 of the second layer by the first wiring 57 or the second wiring 58, the first wiring 57 and the second wiring 5
8 are connected so that they are alternately arranged.

The charge transfer operation in the conventional charge transfer device 50 will be described below with reference to the drawings.

FIGS. 3B and 3C are schematic diagrams showing the potential of the charge transfer channel in the charge transfer device 50. FIG. 3B shows a case where a Low voltage is applied to the first wiring 57. 2 is a case where a High voltage is applied to the second wiring 58, and FIG.
This is a case where a high voltage is applied and a low voltage is applied to the second wiring 58.

As shown in FIG. 3B, the charge transfer device 5
At 0, a low voltage is applied to the first wiring 57 and the second
When a high voltage is applied to the wiring 58 of the semiconductor substrate 5,
Since the potential is higher than that in the region in which the P-type impurity is not diffused in the No. 1 region, the gate electrode 53 on the first layer and the gate electrode 55 on the second layer, which are connected by the first wiring 57, are formed below Comparing the potentials of the charge transfer channels, the potential P ₃₁ of the charge transfer channel below the gate electrode 53 of the first layer becomes lower than the potential P ₃₂ of the charge transfer channel below the gate electrode 55 of the second layer. Similarly, comparing the potentials of the charge transfer channels on the lower side of the first-layer gate electrode 53 and the second-layer gate electrode 55, which are connected by the first wiring 58, shows that The potential P ₄₁ of the charge transfer channel is lower than the potential P ₄₂ of the charge transfer channel below the gate electrode 55 of the second layer.

Since a low voltage is applied to the first wiring 57 and a high voltage is applied to the second wiring 58,
First layer gate electrode 5 connected by first wiring 57
3 below the gate electrode 55 of the second layer and the potential P ₃ of the charge transfer channel below the gate electrode 55 of the _third layer and below the gate electrode 53 of the first layer and the gate electrode 55 of the second layer connected by the second wiring 58. Charge transfer channel potential P ₄
Will be lower.

Therefore, the potential of the charge transfer channel decreases stepwise from right to left, and the potential P ₄₁ of the charge transfer channel under the first-layer gate electrode 53 connected to the second wiring 58 becomes the lowest. , The charge Q ₂ exists in the charge transfer channel under the gate electrode 53 of the first layer.

Next, as shown in FIG. 3C, a high voltage is applied to the first wiring 57 and Lo is applied to the second wiring 58.
When a voltage of w is applied, the charges existing in the charge transfer channel under the gate electrode 53 of the first layer connected to the second wiring 58 are lowered in a stepwise manner from the right to the left by the potential of the first wiring. The charges are transferred to the charge transfer channel below the first-layer gate electrode 53 connected to 57.

[0014]

However, in the above-described conventional charge transfer device 50, as shown in FIG. 3C, it is difficult to transfer charges smoothly in the flat potential portion of the charge transfer channel. Therefore, the residual charge Q _R remains in the flat portion without being transferred, which causes a defect of charge transfer. This is a serious problem especially when trying to drive the charge transfer device at a high frequency. Furthermore, since only the charge transfer channel under the gate electrode 53 of the first layer contributes to the charge transfer capacity, there is a drawback that the charge transfer capacity is small.

The present invention has been made in view of the above, and it is an object of the present invention to provide a charge transfer device capable of preventing a charge transfer failure and increasing a charge capacity, and a manufacturing method thereof. It is intended.

[0016]

In order to achieve the above object, the invention of claim 1 provides a charge transfer device in which the potential of a charge transfer channel under a gate electrode has a gradient in a charge transfer direction. .

Specifically, the means for solving the problems according to the invention of claim 1 is a charge provided with a gate electrode formed on a semiconductor substrate and a charge transfer channel formed below the gate electrode on the semiconductor substrate. Targeting a transfer device, the charge transfer channel is formed to have a gradient such that when a voltage is applied to the gate electrode, the potential of the charge transfer channel decreases toward the front in the charge transfer direction. It is a thing.

According to a second aspect of the present invention, in a method of manufacturing a charge transfer device, a resist film is formed on a semiconductor substrate with a gradient in a charge transfer direction, and impurities are injected into the semiconductor substrate through the resist film. Thus, an impurity diffusion region having a gradient in the charge transfer direction is formed on the semiconductor substrate.

Specifically, the means for solving the problems according to the invention of claim 2 is a method for manufacturing a charge transfer device, comprising a gate electrode on a semiconductor substrate and a charge transfer channel below the gate electrode on the semiconductor substrate. A step of forming a resist film having a gradient such that the film thickness becomes thicker toward the front in the charge transfer direction on the part where the charge transfer channel is formed in the semiconductor substrate, and the semiconductor in which the resist film is formed. Implanting impurities through the resist film into the substrate to form an impurity diffusion region on the lower side of the resist film in the semiconductor substrate having a gradient such that the impurity concentration decreases toward the front in the charge transfer direction. The configuration is as follows.

[0020]

According to the structure of the invention of claim 1, in the charge transfer device formed on a semiconductor substrate, when a voltage is applied to the gate electrode, the potential of the charge transfer channel below the gate electrode is forward in the charge transfer direction. It will be inclined so that it becomes lower toward the bottom. Therefore, at the time of transferring charges, the charges are transferred at high speed and completely due to the action of the potential gradient.

Further, when the gate electrode has a two-layer structure, if the potential of the charge transfer channel under the gate electrode of the second layer is made to have a gradient decreasing toward the front in the charge transfer direction, charge accumulation At some times, not only the charge transfer channel under the gate electrode of the first layer but also the charge transfer channel under the gate electrode of the second layer can accumulate charges, so that the charge capacity can be increased.

According to the second aspect of the present invention, in the method of manufacturing the charge transfer device formed on the semiconductor substrate, the semiconductor substrate has a gradient such that the film thickness becomes thicker toward the front in the charge transfer direction. By forming a resist film and injecting impurities into the semiconductor substrate through the resist film, it is possible to form an impurity diffusion region having a gradient such that the impurity concentration decreases forward in the charge transfer direction in the semiconductor substrate. Therefore, when the gate electrode is formed above the impurity diffusion region in the semiconductor substrate after removing the resist film from the semiconductor substrate and a voltage is applied to the gate electrode, the potential of the charge transfer channel under the gate electrode has a gradient in impurity concentration. Due to the impurity diffusion region having the above, it becomes inclined toward the front in the charge transfer direction. Thus, the charge transfer device according to the invention of claim 1 can be realized.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In the following, the charge carriers are described as electrons, but when the charge carriers are holes, the P-type and N-type of the semiconductor may be reversed.

First, the structure of the charge transfer device according to the above embodiment will be described with reference to FIG.

FIG. 1A shows the configuration of the charge transfer device 10 according to the above embodiment. In FIG. 1 (a),
The first insulating layer 12 is formed over the entire surface of the semiconductor substrate 11, the first-layer gate electrode 13 is formed on the surface of the first insulating layer 12, and the surface of the first-layer gate electrode 13 is formed. The second insulating layer 14 is covered, and the gate electrode 15 of the second layer having a hat-shaped cross section is formed on the side portion of the second insulating layer 14 and the surface of the first insulating layer 12, and the surface portion of the semiconductor substrate 11 is formed. An impurity diffusion region 16 in which P-type impurities are diffused is formed in a region of the second layer below the gate electrode 15. The impurity concentration of the impurity diffusion region 16 has a gradient such that it decreases toward the front in the charge transfer direction, that is, toward the left side in FIG. It has a slope that becomes shallower toward the left side of. The adjacent first-layer gate electrode 13 and second-layer gate electrode 15 are connected by a first wiring 17 or a second wiring 18, and two types of first wiring 17 and second wiring 17 are connected. The wiring 18 is alternately arranged.

Next, a method of manufacturing the charge transfer device 10 will be described with reference to FIG.

FIG. 2 shows each step of the method of manufacturing the charge transfer device 10.

First, as shown in FIG. 2A, after forming the first insulating layer 12 over the entire surface of the semiconductor substrate 11, the first gate layer is formed on the first insulating layer 12. The electrode 13 is formed.

After that, as shown in FIG. 2B, a resist 20 serving as a mask for implanting impurities is patterned on the first insulating layer 12. At this time, the resist 2
Patterning is performed so that the left end portion of 0 hangs on the right side portion of the first-layer gate electrode 13 and a gap is left between the resist 20 and the first-layer gate electrode 13 on the right of the resist 20.

Then, as shown in FIG. 2C, the patterned resist is heated to flow, and the gate electrode 1 of the first layer is formed on the first insulating layer 12.
A resist film 21 having a gradient such that the film thickness increases toward the left side is formed on the right side of 3 adjacent to the gate electrode 13 of the first layer.

Then, as shown in FIG. 2D, the first layer gate electrode 13 and the resist film 21 are used as a mask.
A P-type impurity is injected into the surface portion of the semiconductor substrate 11 from above as indicated by an arrow. At this time, the amount by which the resist film 21 blocks the introduction of P-type impurities into the surface portion of the semiconductor substrate 11 increases as the thickness of the resist film 21 increases. Therefore, the amount of P-type impurities implanted into the surface portion of the semiconductor substrate 11 has a gradient that decreases toward the left side. Therefore, the semiconductor substrate 1
In the portion below the resist film 21 in the surface portion of 1,
Impurity diffusion region 16 having a gradient such that the concentration of P-type impurities decreases toward the left is formed. Moreover,
The impurity diffusion region 16 is formed so as to have a gradient such that the depth thereof similarly becomes shallower toward the left side.

Next, the charge transfer operation in the charge transfer device 10 will be described with reference to FIGS. 1 (b) and 1 (c).

FIGS. 1B and 1C are schematic diagrams showing the potential of the charge transfer channel in the charge transfer device 10, and FIG. 1B shows the first wiring 17 applied with a low voltage. 2 is a case where a high voltage is applied to the second wiring 18, and FIG.
This is a case where a high voltage is applied and a low voltage is applied to the second wiring 18.

As shown in FIG. 1B, the charge transfer device 1
At 0, a low voltage is applied to the first wiring 17
When a high voltage is applied to the wiring 18 of the
Gate electrode 13 of the first layer and the gate electrode of the first layer connected by the second wiring 18 more than the potential P ₁ of the charge transfer channel below the gate electrode 13 of the first layer and the gate electrode 15 of the second layer 13 and the gate electrode 1 of the second layer
The potential P ₂ of the charge transfer channel below the 5th gate electrode becomes lower. Here, the second-layer gate electrode 1
Since the impurity concentration of the impurity diffusion region 16 on the lower side of 5 has a concentration gradient that decreases toward the left side,
The potentials P ₁₁ and P ₂₁ of the charge transfer channel below the gate electrode 15 of the layer are inclined so as to decrease toward the left side.

Therefore, not only the charge transfer channel below the first-layer gate electrode 13 connected to the second wiring 18 but also below the second-layer gate electrode 15 also connected to the second wiring 18 are formed. The charge Q ₁ is also accumulated in the charge transfer channel.

Next, as shown in FIG. 1C, a high voltage is applied to the first wiring 17 and Lo is applied to the second wiring 18.
When a voltage of w is applied, the first-layer gate electrode 13 and the second-layer gate electrode 15 connected by the second wiring 18 are connected.
The charge Q ₁ existing in the lower charge transfer channel is transferred to the lower charge transfer channel of the first-layer gate electrode 13 and the second-layer gate electrode 15 connected by the first wiring 17 adjacent to the left. To be done.

As described above, in the charge transfer device according to the present embodiment, the impurity diffusion region under the gate electrode of the second layer has a concentration gradient such that it becomes lower toward the front in the charge transfer direction. When a voltage is applied to the gate electrodes of the two layers, the potential of the charge transfer channel below the gate electrodes of the second layer has a gradient such that it decreases toward the front in the charge transfer direction. Due to the potential having a gradient in the charge transfer channel under the gate electrode of the second layer, the charge can be transferred at high speed and completely during charge transfer, and at the same time, the charge under the gate electrode of the first layer during charge accumulation. Since charges are accumulated not only in the transfer channel but also in the charge transfer channel below the gate electrode of the second layer, a large charge transfer capacity can be secured.

Further, according to the method of manufacturing the charge transfer device of this embodiment, the resist film having a gradient such that the film thickness becomes thicker toward the front side in the charge transfer direction is formed on the semiconductor substrate, and the surface of the semiconductor substrate is formed. By injecting an impurity into the portion through the resist film, an impurity diffusion region having a gradient such that the impurity concentration decreases toward the front in the charge transfer direction can be formed in the surface portion of the semiconductor substrate.

In this embodiment, the gate electrode is 2
Although the case where the gate electrode has a layered structure has been described, the gate electrode has three layers.
Even if more than one layer is present, the potential of the charge transfer channel under the gate electrode is provided with a gradient such that the potential becomes lower toward the front in the charge transfer direction, so that charge transfer can be performed at high speed and completely. The transfer capacity can be increased.

[0040]

As described above, according to the charge transfer device of the first aspect of the present invention, the potential of the charge transfer channel below the gate electrode has a gradient such that it decreases toward the front in the charge transfer direction. Therefore, charge transfer is performed at high speed and completely. Further, when the gate electrode has a two-layer structure, if the potential of the charge transfer channel under the gate electrode of the second layer is inclined so as to decrease toward the front in the charge transfer direction, the gate electrode of the second layer Since the charges can be accumulated in the lower charge transfer channel, the charge capacity can be increased.

Therefore, it is possible to prevent a charge transfer failure and to provide a charge transfer device capable of increasing the charge capacity.

Further, according to the method of manufacturing the charge transfer device in accordance with the second aspect of the present invention, the impurity diffusion region having a gradient such that the impurity concentration decreases toward the front in the charge transfer direction can be formed in the semiconductor substrate. . With such an impurity diffusion region having a gradient in the impurity concentration, the potential of the charge transfer channel can be inclined so as to decrease toward the front in the charge transfer direction. Therefore,
The charge transfer device according to the invention of claim 1 can be realized.

[Brief description of drawings]

1A is a cross-sectional view showing a charge transfer device according to an embodiment of the present invention, and FIGS. 1B and 1C are schematic views showing the potential of a charge transfer channel in the charge transfer device. .

FIG. 2 is a cross-sectional view showing the semiconductor substrate after each step of the method for manufacturing the charge transfer device.

3A is a cross-sectional view showing a conventional charge transfer device, and FIGS. 3B and 3C are schematic diagrams showing the potential of a charge transfer channel in the conventional charge transfer device.

FIG. 4 is a cross-sectional view showing the semiconductor substrate after each step of the above-described conventional method for manufacturing a charge transfer device.

[Explanation of symbols]

 10 Charge Transfer Device 11 Semiconductor Substrate 12 First Insulating Layer 13 First Layer Gate Electrode 14 Second Insulating Layer 15 Second Layer Gate Electrode 16 Impurity Diffusion Region 17 First Wiring 18 Second Wiring 21 Resist Film

Claims (2)

[Claims] 1. A charge transfer device comprising a gate electrode formed on a semiconductor substrate and a charge transfer channel formed below the gate electrode on the semiconductor substrate, wherein the charge transfer channel is A charge transfer device, characterized in that the potential of the charge transfer channel is formed so as to decrease toward the front in the charge transfer direction when a voltage is applied to the gate electrode. 2. A method of manufacturing a charge transfer device comprising a gate electrode on a semiconductor substrate and a charge transfer channel below the gate electrode on the semiconductor substrate, wherein the charge transfer channel on the semiconductor substrate is formed. A step of forming a resist film having a gradient such that the film thickness becomes thicker toward the front in the charge transfer direction on the upper side of the portion, and by implanting impurities through the resist film into the semiconductor substrate on which the resist film is formed, And a step of forming an impurity diffusion region having a gradient such that the impurity concentration decreases toward the front in the charge transfer direction on the lower side of the resist film on the substrate. .