JPH05218425A - Field effect semiconductor device and manufacturing method thereof - Google Patents

Abstract

PURPOSE:To enable the title field effect semiconductor device to be rapidly actuated even at high power supply voltage by a method wherein an active region is composed of the first conductivity type active region and the second conductivity type regions opposing to each other having the first active region for restraining the deterioration in the breakdown voltage between drain and source. CONSTITUTION:A substrate 11 and a source electrode 21 are grounded while the space between a gate electrode 17 and a drain electrode is imposed with a voltage. When a drain voltage VD is boosted, an electron.hole coupling is to be started by an avalanche phenomenon near a drain junction. At this time, the electrons theta among the couple run into a drain region 19 while holes (+) gather at the bottom of a p type active layer 15 to be later implanted in an n type active layer 13. On the other hand, the electrons are to be inversely implanted from the n type active layer 13 but the amount of the inversely implanted electrons shall be notably reduced due to the lower impurity of the concentration of the n type active layer 13 than that of the p type active layer 15. Accordingly, the deterioration in the breakdown voltage between source and drain due to the parasitic bipolar effect can be effectively restrained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect semiconductor device which operates at high speed and a high breakdown voltage, and a method for manufacturing the same.

[0002]

2. Description of the Related Art FIG. 11 is a sectional view showing the structure of a conventional semiconductor device of this type. In the figure, 1 is a silicon substrate, 2 is an insulating film for electrically insulating the active layer 3 of the first conductivity type and the silicon substrate 1, 4 is a gate insulating film, 5 is a gate electrode, and 6 is a second. A conductivity type source region, 7 is a second conductivity type drain region, 8 is an insulating film for electrically insulating between wirings, 9 is a source electrode, and 10 is a drain electrode.

In the semiconductor device configured as described above, the impurity concentration of the active layer 3 is designed so that the depletion layer that can spread from the gate electrode 5 is thicker than the thickness t _S1 of the active layer 3, The entire region of the active layer 3 is depleted when the semiconductor device operates.

The reason for such a configuration is that the gate insulating film 4 is formed by reducing the effective electric field strength in the active layer 3.
Since it is possible to suppress the mobility deterioration of the inversion layer carrier immediately below and increase the drain current due to this, and to increase the drain current by increasing the inversion layer carrier corresponding to the decrease in the charge amount of the depletion layer in the active layer 3. Is.

Further, in the semiconductor device having such a structure, since the inside of the active layer 3 is depleted by the gate electric field, entry of the drain electric field from the drain junction into the active layer 3 can be suppressed, and the threshold voltage is short. The channel effect can be suppressed.
Therefore, this type of semiconductor device can be expected to achieve both high integration and high speed operation of the semiconductor device due to the miniaturization of dimensions, and its future potential has been drawing attention in recent years.

[0006]

However, it has recently been clarified that in this type of semiconductor device, the drain-source breakdown voltage is lower than the normally expected value. FIG. 12 shows an example of drain voltage / drain current characteristics of this type of n-channel semiconductor device having a gate length of 0.5 μm. In the conventional semiconductor device, the gate length is 0.5
In the case of μm, the drain current continues as shown by the broken line, and the drain-source breakdown voltage is about 5 to 6V. On the other hand, in this type of semiconductor device, it bends as shown by the solid line, and only a withstand voltage of about 3 V is obtained.

The cause is considered to be the parasitic bipolar effect derived from the structure. This will be described with reference to FIG. FIG. 11 shows an example of an n-channel type semiconductor device. In this type of semiconductor device, usually, the silicon substrate 1 and the source electrode 9 are grounded, and the gate electrode 5 and the drain electrode 1 are grounded.
A positive voltage is applied between 0 and it to operate. When the drain voltage V _D increases, electron-hole pairs due to the weak avalanche phenomenon start to occur near the drain junction. In the figure, a circle − indicates an electron, a circle + indicates a hole, and a circle − and a circle + surrounded by a dotted line indicate an electron-hole pair.
Of these, the electrons flow into the drain region 7 as they are, but the holes move to the vicinity of the interface between the active layer 3 and the lower insulating film 2 having the lowest potential in the active layer when viewed from the holes.
After holes are collected here, they are forward-injected into the source junction by the drain electric field. Correspondingly, a large amount of electrons are back-injected from the source region 6 into the active layer 3.

The amount is [amount of holes injected in the forward direction] × [impurity concentration of source] /
[Impurity concentration of active layer] ... (1) A part of the back-injected electrons flows into the drain junction while inducing a new avalanche phenomenon near the drain junction. Since this is a positive feedback phenomenon, the drain current rapidly increases, resulting in a decrease in drain-source breakdown voltage. As described above, this type of semiconductor device has not been put into practical use yet because it has some of the great features but at the same time has the problems described above.

Therefore, the present invention drastically improves the reduction in the breakdown voltage between the drain and the source, which has been a problem in the conventional semiconductor device described above, and the semiconductor device which can operate at high speed under a high power supply voltage. It is intended to provide a manufacturing method.

[0010]

In order to achieve such an object, a field effect semiconductor device according to the present invention has one active region of the first conductivity type and an active region of the first conductivity type interposed therebetween. The active layer is composed of the opposing second conductivity type active regions.

[0011]

In the field effect semiconductor device of the present invention, of the electron-hole pairs generated near the drain junction,
Carriers of the second conductivity type are injected into the active layer of the first conductivity type, but the impurity concentration of the active layer of the first conductivity type is usually lower than that of the source region of the first conductivity type by about four orders of magnitude. The amount of carriers of the first conductivity type is significantly suppressed, and the gate electric field binds the carriers of the first conductivity type directly below the gate insulating film in the active layer of the first conductivity type, so that the carriers of the first conductivity type are naturally supplied. Is limited, the parasitic bipolar effect is sufficiently suppressed, and the operating characteristics can be improved.

[0012]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a sectional view of an n-channel type semiconductor device showing a configuration according to an embodiment of a field effect type semiconductor device according to the present invention. In the figure, 11 is a silicon substrate, 12
Is an insulating film made of, for example, a silicon oxide film for electrically insulating the active layers 13, 14 and 15 from the silicon substrate 11, 13 is an active layer having a first conductivity type of, for example, n-type, 14
Is a p-type active layer as the second conductivity type, 15 is a p-type active layer as the second conductivity type, 16 is a gate insulating film made of, for example, a silicon oxide film, 17 is a gate electrode made of, for example, polycrystalline silicon, Reference numeral 18 denotes a source region having a first conductivity type, for example, n-type, and 19 denotes a first conductivity type, for example, n.
Shaped drain region, 20 is an insulating film made of, for example, a silicon oxide film, 21 is a source electrode made of, for example, an Al film, 2
Reference numeral 2 is a drain electrode made of Al, for example.

In such a structure, as shown in FIG. 1, the thickness t _S2 of the active layer 13 is designed to be thinner than the thickness of the depletion layer that can spread from immediately below the gate insulating film 16. On the other hand, the width d of the active layer 14 is made larger than the sum of the depletion layer width extending from the active layer 13 to the active layer 14 side and the depletion layer width extending from the source region 18 to the active layer 14 side.

In this case, the reason why the width d of the active layer 14 is designed in this way is as follows. Since the active layer 13 has a potential intermediate to the potential applied to the drain region 19 with the source region 18 as a reference, a depletion layer is generated to some extent on both sides of the active layer 14. At this time, when the two depletion layers are in contact with each other, the active layer 14 does not serve as a barrier between the active layer 13 and the source region 18, and minority carriers are easily injected into each other, so that a high operating voltage cannot be realized. Is.

In the semiconductor device thus constructed, the silicon substrate 11 and the source electrode 21 are grounded, and an appropriate positive voltage is applied between the gate electrode 17 and the drain electrode 22. When the drain voltage V _D increases, electron-hole pairs due to the weak avalanche phenomenon start to occur near the drain junction, as in the conventional semiconductor device. Also in this figure, circle − indicates an electron, circle + indicates a hole, and circle − and circle + surrounded by a dotted line indicate an electron-hole pair, respectively. Of these, the electrons flow into the drain region 19 as they are. On the other hand, holes collect at the bottom of the p-type active layer 15 and then n
The active layer 13 is implanted. On the other hand, although reverse injection of electrons occurs from the n-type active layer 13, the impurity concentration of the p-type active layer 15 is higher than the impurity concentration of the n-type active layer 13 in the normal configuration. As is clear from 1), the amount of back-injected electrons is significantly smaller than that in the case of the conventional field effect semiconductor device shown in FIG. Therefore, deterioration of the breakdown voltage between the source and the drain due to the parasitic bipolar effect can be effectively suppressed.

2 to 7 are sectional views of steps for explaining an embodiment of the method for manufacturing a field effect semiconductor device according to the present invention. In the figure, first, as shown in FIG. 2, for example, a semiconductor substrate is prepared in which, for example, silicon oxide is embedded as an insulator layer 32 in a silicon substrate 31 and a silicon layer 33 is provided on the insulator layer 32.

Next, as shown in FIG. 3, this silicon layer 33 is formed.
A silicon active layer 33 'having a predetermined size is formed on the main surface of the substrate by an anisotropic etching method, for example, a reactive ion etching method. Subsequently, after forming an oxide film (not shown) on the surface of the active layer 33 ', for example, phosphorus or arsenic is introduced by, for example, an ion implantation method to make the first conductivity type n-type. Subsequently, after removing the oxide film on the surface of the active layer 33 ', the surface of the active layer 33' is again oxidized to form the gate oxide film 34.

Next, as shown in FIG. 4, a semiconductor film for forming a gate electrode, for example, a silicon film is deposited on the gate insulating film 34, and thereafter, a predetermined size is obtained by an anisotropic etching method such as a reactive ion etching method. Then, the gate electrode 35 is formed.

Thereafter, as shown in FIG. 5, the silicon substrate 3
The p-type active layer 36 and the p-type active layer 37 are formed by introducing a p-type impurity as the second conductivity type from the main surface side of the first conductive layer by ion implantation and diffusing the ion-implanted impurities by an appropriate heat treatment. To form.

Next, as shown in FIG. 6, an n-type impurity as the first conductivity type is introduced from the main surface side of the silicon substrate 31 by, for example, an ion implantation method to form n-type source regions 38 and n.
A drain region 39 having a shape is formed. By this process, p
The shaped active layer 36 becomes a local active region 36 'sandwiched between a source region 38 and an active layer 33 ". Similarly, a local active region 37' is formed.

Finally, as shown in FIG. 7, after depositing an insulating film 40 on the main surface side of the silicon substrate 31, the source region 3 is formed.
8 and the drain region 39 are respectively formed with contact holes, and then the source electrode 41 and the drain electrode 42 are formed to complete the semiconductor device.

8 to 10 are sectional views of steps for explaining another embodiment of the method for manufacturing a field effect semiconductor device according to the present invention. This manufacturing method uses a silicon substrate which has been subjected to the steps of FIGS. 2 to 4 described above, as shown in FIG. Introduce impurities. In this step, it is not necessary to particularly diffuse the ion-implanted impurities by heat treatment, and only the activation of the impurities may be performed. In this way, the p-type active layer 36 and the p-type active layer 37 are formed.

Next, as shown in FIG. 9, after depositing an insulating film such as a silicon nitride film or a silicon oxide film on the main surface side of the silicon substrate 31, an anisotropic etching method such as a reactive ion etching method is used. Etching is performed to form an insulating film 43 'on the side wall of the gate electrode 35. After that, an n-type impurity as the first conductivity type is introduced from the main surface side of the silicon substrate 31 by, for example, an ion implantation method to obtain n.
Forming a source region 38 and an n-type drain region 39. By this step, the p-type active region 36 is sandwiched between the source region 38 and the active layer 33 ", and the local active region 3 is formed.
6 '. Similarly, a local active area 37 'is formed.

Finally, as shown in FIG. 10, an insulating film 40 is deposited on the main surface side of the silicon substrate 31, contact holes are formed on the source region 38 and the drain region 39, respectively, and then a source electrode 41 is formed. Then, the drain electrode 42 is formed to complete the semiconductor device.

[0025]

As described above, according to the present invention,
An extremely excellent effect as described below can be obtained. An active layer of the second conductivity type is provided adjacent to the source region and the drain region of the first conductivity type, and an active layer of the first conductivity type having an impurity concentration sufficiently lower than that of the source region and the drain region is provided adjacent to the active layer. Since the region is provided, the amount of reverse carriers is remarkably suppressed even if the carriers of the second conductivity type among the electron-hole pairs generated near the drain junction are injected into the active region of the first conductivity type. With the effects described above, the amount of majority carriers injected into the source junction, which triggers the occurrence of the parasitic bipolar effect, can be dramatically reduced, and the drain-source breakdown voltage can be significantly improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing the configuration of an example of a field effect semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view of a step illustrating an embodiment of a method for manufacturing a field effect semiconductor device according to the present invention.

FIG. 3 is a sectional view of a step following the step of FIG.

FIG. 4 is a sectional view of a step following the step of FIG. 3;

FIG. 5 is a sectional view of a step following the step of FIG. 4;

FIG. 6 is a sectional view of a step following the step of FIG. 5;

FIG. 7 is a sectional view of a step following the step of FIG. 6;

FIG. 8 is a cross-sectional view of a step illustrating another embodiment of the method for manufacturing a field effect semiconductor device according to the present invention.

FIG. 9 is a sectional view of a step following the step of FIG.

FIG. 10 is a sectional view of a step following the step of FIG. 9;

FIG. 11 is a cross-sectional view showing a configuration of a conventional field effect semiconductor device.

FIG. 12 is a diagram showing an example of drain voltage / drain current characteristics of an n-channel semiconductor device of this type having a gate length of 0.5 μm.

[Explanation of symbols]

 11 Silicon Substrate 12 Insulating Film 13 n-type Active Layer 14 p-type Active Layer 15 p-type Active Layer 16 Gate Insulating Film 17 Gate Electrode 18 n-type Source Region 19 n-type Drain Region 20 Insulating Film 21 Source Electrode 22 Drain Electrode 31 Silicon Substrate 32 Insulator layer 33 Silicon layer 33 'Silicon active layer 33 "Active layer 34 Gate insulating film 35 Gate electrode 36 p-type active layer 36' Active region 37 p-type active layer 38 n-type source region 39 n-type drain Region 40 Insulating film 41 Source electrode 42 Drain electrode 43 'Insulating film

Claims (2)

[Claims] 1. A first single crystal semiconductor layer of a first conductivity type, a second single crystal semiconductor layer of a second conductivity type, a third single crystal semiconductor layer of a first conductivity type, and a third single crystal semiconductor layer of a first conductivity type on an insulator layer. A second conductivity type fourth single crystal semiconductor layer and a first conductivity type fifth single crystal semiconductor layer are sequentially arranged in a plane direction, and a thickness of the second single crystal semiconductor layer is adjacent to the first single crystal semiconductor layer. Second from the bonding surface with the single crystal semiconductor layer
Of the thickness of the depletion layer generated on the side of the single crystal semiconductor layer and the thickness of the depletion layer generated on the side of the second single crystal semiconductor layer from the joint surface with the third single crystal semiconductor layer facing and adjacent to each other. A gate insulating film which is larger than the gate insulating film and which is continuously formed on at least the second single crystal semiconductor layer, the third single crystal semiconductor layer and the fourth single crystal semiconductor layer, and formed on the gate insulating film. A field effect semiconductor device comprising a gate electrode. 2. A first insulator layer is embedded in a semiconductor and has a first semiconductor layer on the first insulator layer. A semiconductor substrate having a first semiconductor layer on the first insulator layer has a first surface on the first semiconductor layer. Forming a first semiconductor region of conductivity type; forming a second insulating film on the first semiconductor region of first conductivity type; forming a gate electrode on the second insulating film; And a second semiconductor region of the second conductivity type at a position adjacent to the first semiconductor region by introducing an impurity from the main surface of the semiconductor substrate and opposed to the first semiconductor region via the first semiconductor region. And a step of forming a third semiconductor region, and a first semiconductor region adjacent to the second semiconductor region by introducing an impurity from the main surface side of the semiconductor substrate and via the second semiconductor region. Forming a fourth semiconductor region of the first conductivity type at a position facing And a step of introducing the impurities from the main surface side of the semiconductor substrate to adjoin the third semiconductor region and to face the first semiconductor region via the third semiconductor region. And a step of forming a fifth semiconductor region having a rectangular shape, and a method of manufacturing a field effect semiconductor device.