JPH0615120U - Operating frequency setting circuit - Google Patents

Abstract

(57) [Summary] [Purpose] The purpose is to operate a microprocessor with low power consumption. [Composition] An operating frequency setting circuit for setting an operating frequency serving as a reference for the operation of the apparatus, wherein the dividing circuit divides a basic clock to obtain a plurality of operating clocks, and an operating clock input from the dividing circuit. The operation clock selection circuit that outputs the operation clock selection circuit that outputs the operation clock selection circuit to the device, and outputs the operation selection signal that selects the operation clock to the operation clock selection circuit based on the setting signal and the state switching signal that the device outputs. A selection signal generation circuit that outputs an operation selection signal that changes the state of the device, and a reset circuit that resets the device based on the state switching signal are provided. An operation selection signal is output to set an operation clock that serves as a reference for the operation of the apparatus.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to an operation frequency setting circuit that sets an operation frequency that is a reference for the operation of a microprocessor or the like. More specifically, the operation clock is set according to the processing speed required by the microprocessor, and power consumption is set. This is related to the operating frequency setting circuit that aims to reduce

[0002]

[Prior art]

 The digital control circuit that uses a microprocessor sets the operating speed of the microprocessor for the required peak load, so when high-speed processing is not necessary, for example, even in the waiting state for startup, the peak load state Is being operated on.

[0003]

[Problems to be solved by the device]

 As described above, the conventional digital control circuit using the microprocessor has the drawbacks that the power consumption is large and the heat is large because the digital control circuit always operates in the state of the peak load.

[0004]

[Means for Solving the Problems]

 The present invention has been made in view of such a point. When high-speed processing is not required, the operating clock is switched to a clock with a low frequency, and the microprocessor operates with low power consumption. It is an object of the present invention to provide an operating frequency setting circuit that can be used.

[0005]

[Means for Solving the Problems]

 In order to achieve such an object, the present invention is an operating frequency setting circuit that sets an operating frequency that serves as a reference for operation of a device, and is a frequency dividing circuit that divides a basic clock to obtain a plurality of operating clocks. And an operation clock selection circuit that selects the operation clock input from this frequency divider circuit and outputs the operation clock to the device, and an operation clock selection circuit that outputs the operation clock to the operation clock selection circuit based on the setting signal and the state switching signal output by the device. And a reset circuit for resetting the device based on the status switching signal. The device is reset by a state switching signal, and an operation selection signal based on the setting signal is output from the selection signal generation circuit, It is characterized by setting the operating clock as a reference of the operation of the serial device.

[0006]

[Action]

 The microprocessor is reset by the reset signal output from the reset circuit, and the operation clock selected by the operation clock selection circuit is set by the operation selection signal of the selection signal generation circuit.

[0007]

【Example】

An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a configuration block diagram showing an embodiment of the operating frequency setting device of the present invention. In the figure, 1 is an oscillator, and 2 is a frequency divider that divides the basic clock CLK ₀ output from the oscillator 1. In this example, an operation clock CLK ₁ obtained by dividing by 2 and 8 is obtained. ing.

An operation clock selection circuit 3 selects the operation clock CLK ₁ input from the frequency dividing circuit 2 based on the operation selection signal S ₁ of the selection signal generation circuit 4 and outputs it to the microprocessor 5. The operation selection signal S ₁ of the selection signal generation circuit 4 is obtained by synchronizing the setting signal S ₂ input from the microprocessor 5 with the state switching signal S ₃ , and the operation clock selection circuit 3 and the microprocessor 5 Is output to.

Reference numeral 6 denotes an OR gate, one side of which receives the initialization signal S ₄ and the other input terminal of which the state switching signal S ₃ is inputted. OR gate 6 outputs a reset signal S ₅ the signal S ₃ switching state inputted from My Kuropurossesa 5 becomes low level to the micro plot Princesa _5, reset the micro plot Princesa 5.

FIG. 2 is a time chart for explaining the operation of the operating frequency setting device of the present invention. (A) is an initialization signal S ₄ output to the selection signal generating circuit 4, and (B) is a microprocessor 5 state switching signal S ₃ but outputting, (C) is reset signal S ₅ to the OR gate 6 outputs, (D) is set signal S ₂ output by the microprocessor 5, (E) is selected択信No. generating circuit 4 The operation selection signals S ₁ and (F) output by the operation clock are the operation clocks CLK ₁ output by the operation clock selection circuit 3.

(1) When the power is turned on, the operation selection signal S ₁ is forcibly set to the low level by the initialization signal S ₄ , and the microprocessor 5 operates in the normal processing state. (2) When the normal processing state is no longer needed (at t ₁ ), the microprocessor 5 outputs the high level setting signal S ₂ to the selection signal generating circuit 4. (3) Subsequently, at time t ₂ , the state switching signal S ₃ having a pulse width sufficient to reset the microprocessor 5 is output to the selection signal generating circuit 4 and the OR gate 6. .

(4) The OR gate 6 receives the input state switching signal S₃Reset signal S obtained based on _Five Is output to the microprocessor 5. On the other hand, the selection signal generation circuit 4 receives the input state switching signal S₃High-level operation selection signal S based on₁Is output to the microprocessor 5.

(5) The microprocessor 5 is in the reset state while the reset signal S ₅ is low level, and switches to the activation waiting state when the reset signal S ₅ rises to operate. (6) After that, the transition from the activation waiting state to the normal processing state is performed in the same process. The microprocessor 5 outputs the low-level setting signal S ₂ to the selection signal generating circuit 4 at time t ₃ , and outputs the state switching signal S ₃ to the selection signal generating circuit 4 and the OR gate 6 at time t ₄ .

In this way, the microprocessor 5 is reset by the state switching signal S ₃ having a pulse width sufficient for resetting and the operation switching is performed, so that the operation switching can be stably performed.

[0015]

[Effect of device]

 As described above in detail, the operating frequency setting device of the present invention switches the operating clock to a clock with a low frequency when high-speed processing is not required, so that the microprocessor operates with low power consumption. be able to.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing an embodiment of an operating frequency setting device of the present invention.

FIG. 2 is a time chart explaining the operation of the operating frequency setting device of the present invention.

[Explanation of symbols]

 2 Frequency divider circuit 3 Operation clock selection circuit 4 Selection signal generation circuit 6 OR gate

Claims (1)

[Scope of utility model registration request] 1. An operating frequency setting circuit for setting an operating frequency serving as a reference for the operation of a device, wherein the basic clock is frequency-divided to obtain a plurality of operating clocks. An operation clock selection circuit that selects an operation clock and outputs the operation clock to the device, and outputs an operation selection signal that selects the operation clock to the operation clock selection circuit based on a setting signal and a state switching signal output by the device. A selection signal generating circuit for outputting an operation selection signal for changing the operation state to the device; and a reset circuit for resetting the device based on the state switching signal, and resetting the device by the state switching signal. , An operation selection signal based on the setting signal is output from the selection signal generation circuit, and an operation clock serving as a reference for the operation of the device is output. The operating frequency setting circuit which is characterized in that setting the click.