JPH0614367B2 - Microprocessor - Google Patents

Description

The present invention relates to a microprocessor, in particular, at least a part of a digital control system, and a monolithic semiconductor integrated circuit micro-processor including an analog digital conversion circuit (hereinafter referred to as an A / D conversion circuit). Regarding the processor.

By using a semiconductor integrated circuit, the digital control system can reduce the size of a device constituting the semiconductor integrated circuit, and can reduce the number of connections outside the semiconductor integrated circuit.

As a control system that uses a microprocessor to perform process control, calculation control, etc., in order to perform high-quality system control, various sensor signals such as digital signals as well as analog signals with a large amount of information can be transmitted via an A / D conversion circuit. Something that is supposed to be input is considered.

In this case, in order to downsize the device and reduce the number of external connections, an input circuit that supplies the digital signal to the data bus of the microprocessor and an input circuit that supplies the digital signal after converting the analog signal into the digital signal. It is desirable to configure and as a one-chip monolithic semiconductor integrated circuit.

However, when attempting to make a monolithic semiconductor integrated circuit as described above, the number of external terminals provided in the monolithic semiconductor integrated circuit for digital signal input and analog signal input increases. Further, when the number of external terminals that can be provided in the monolithic semiconductor integrated circuit is limited due to the limited external dimensions, etc., the limitation of the external terminals limits the functions that can be realized by the control system. Become.

Therefore, it becomes difficult to use one type of monolithic semiconductor integrated circuit for a plurality of purposes.

For example, if many analog input terminals are set in a monolithic semiconductor integrated circuit, it becomes unsuitable for control that inputs many digital signals, and conversely, if many digital input terminals are set, control that inputs many analog signals. Is not suitable for. Further, it becomes difficult to switch the digital input signal to the analog input signal and change the system to control with high quality.

Therefore, one object of the present invention is to provide a digital semiconductor integrated circuit which has a small number of terminals and which constitutes at least a part of a digital control system having improved versatility.

Another object of the present invention is to provide a digital control system using the above-mentioned digital semiconductor integrated circuit.

Still other objects of the present invention will be apparent from the following description and drawings.

According to the present invention, at least a part of the analog input terminal and a part of the digital input terminal are shared, and the shared terminal is selectively used as a digital input terminal or an analog input terminal by a program.

The digital input terminal is also used as a digital output terminal if necessary. As a result, the number of external terminals can be further reduced as compared with the case where only the input terminals are provided as described above.

Hereinafter, the present invention will be described in detail together with examples.

FIG. 1 is a block diagram showing an embodiment of the present invention.

Reference numeral 1 denotes a microprocessor composed of a one-chip monolithic semiconductor integrated circuit, which is composed of circuit blocks 2 to 18 described below.

2 is an accumulator, 3 is an accumulator latch, 4 is a temporary register, 5 is an arithmetic logic unit, and these circuits 2 to 5 constitute an arithmetic unit.

The arithmetic logic unit 5 is for performing arithmetic operations such as addition and subtraction or logical judgment such as logical sum (OR), logical product (AND) and exclusive logical sum under the control of the control circuit 8. That is, the arithmetic logic unit 5 operates using the contents of the temporary register 4 and the contents of the accumulator latch 3 which is the output of the accumulator 2 as inputs. The operation result of the arithmetic logic unit 5 is sent to the accumulator via the internal data bus BUS, although it depends on the control signal based on the instruction word from the control circuit 8.

Reference numeral 6 is an instruction register, 7 is an instruction decoder and a machine cycle encoder, 8 is a timing control circuit, and these circuits 6 or 8 constitute a control unit.

The instruction register 6 is for taking out the program instruction word written in the ROM 19 or the RAM 20. The instruction read by the instruction register 6 is decoded by the instruction decoder and converted into various timing signals by the machine cycle encoder.

The timing control circuit 8 includes an external control terminal group CONT.
A bus control signal for fetching data from the external data bus DT and a strobe signal for writing data to the external data bus DT are output by timing based on the clock signal input from the.

Further, the timing control circuit 8 has an external control terminal group CONT.
Interrupt signal from, hold signal to stop the operation,
Checking a series of external signals such as reset signals, and further sending a series of signals such as a signal indicating that an interrupt is received and a signal indicating that a hold request has been received to the outside by receiving these signals Is.

Reference numeral 9 denotes a register unit, which includes a general-purpose working register, a stack pointer, a program counter, etc., which are not shown.

The general-purpose working register in the register unit 9 is
It is used not only for handling data (including double length data) but also for memory reference. The stack pointer is used to store the return address of the subroutine jump. The program counter is a register for storing the location of an instruction word to be read next, and except the jump instruction, 1 is added to the content every time one instruction is executed.

Reference numeral 18 denotes an address decoder circuit, which receives an output from the general-purpose working register of the register unit 9 and outputs a signal for controlling circuits 15 to 17 described later. By using the address decoder circuit 18, the circuits 15 to 17 can be controlled by a small number of general purpose working registers.

Reference numeral 10 is an address buffer, which is a ROM 19 or a RAM
It outputs an address signal to be supplied to 20 and the peripheral circuit 21.

Reference numeral 11 is a data buffer, which transfers data between the external data bus DT and the internal data bus BUS.

Reference numeral 12 denotes an input / output port for transmitting / receiving a signal by a digital signal to / from a control target in process control or the like, and for transmitting a signal to an internal data bus via the register 15. In this embodiment, some of the digital signal terminals (for example, P ₄ and P ₅ ) are also used as analog input terminals as described later.

Reference numeral 13 is a multiplexer, which selectively inputs a plurality of analog input signals to the A / D conversion circuit 14. The multiplexer 13 shares the digital input / output terminals P ₄ and P ₅ as a part of its inputs. That is, the terminals P _{1 to} P ₃ are input terminals dedicated to analog, and the terminals P ₄ and P ₅ are terminals commonly used for analog and digital.

The digitalized output signal of the A / D conversion circuit 14 is transmitted to the internal data bus BUS via the register 16.

Reference numeral 17 is a control register that forms a selection signal for the multiplexer, and reads the signal on the internal data bus BUS under the control of the address decoder circuit 18.

When using the shared terminals P ₄ and P ₅ as input / output terminals for digital signals, the multiplexer 13 or A
The input / output is prohibited by the D / D conversion circuit 14 (may be performed by the register 16). On the other hand, when the shared terminals P ₄ and P ₅ are used as analog input terminals, an input / output port is used. The analog signal from the above terminal is taken into the A / D conversion circuit 14 by making the corresponding output circuit 12 have high impedance.

This can be easily understood by the specific embodiment circuit shown in FIG.

Register 17 for controlling the multiplexer 13, which is constituted by a transmission gate MISFET Q ₁₆ to Q ₂₀ includes a latch circuit 17a, is constituted by a decoder circuit 17b, the above-mentioned latch circuit 17a, the transmission gate MISFET Q ₁
Through to Q _3, the signal from the internal data bus BUS is set. The transmission gates MISFETQ _{1 to} Q
₃ is selected by the address decoder circuit 18. Therefore, by selecting the specific address given to the register 17 and inputting the multiplexer selection data to the latch circuit constituting the register 17 through the internal data bus BUS, the selection operation of an arbitrary multiplexer 13 is performed. It is what is done.

The output of the register 16 to which the A / D conversion output is input is also connected to the corresponding bit line of the internal data bus BUS via the transmission gates MISFETs Q _{4 to} Q ₆ , and the register 16 By designating a given specific address, the address decoder circuit 18
The MISFETs Q _{4 to} Q ₆ are turned on by the output of the above and are taken into the internal data bus BUS.

The input / output port 12 for digital signals has terminals P ₄ to
Input buffer amplifier 12a and Pn
An output buffer amplifier 12b is provided,
A gate signal is applied to the output buffer amplifier 12b to control signal transmission.

The register 15 includes a latch circuit 15a provided corresponding to the output of each input buffer amplifier 12a from the input / output port 12, a latch circuit 15b provided corresponding to the input of each output buffer amplifier 12b, and The latch circuit 15c is provided corresponding to the gate input of the output buffer amplifier 12b. The latch 15a corresponding to the terminals, and the input 15b, etc., output, respectively transmission gates _{MISFETQ 7, Q 8 ~Q 13,} Q
_It is connected via ₁₄ to the bit line of the corresponding internal data bus BUS, is given a specific address for each, and is controlled by the output of the address decoder circuit 18.

The input of the latch circuit 15c that forms a gate signal for the output buffer amplifier 12b and the like is connected to the transmission gate MISFE.
It is also connected to the corresponding bit line of the internal data bus BUS via TQ ₉ , Q _{12 to} Q ₁₅ .

As described above, since the digitized analog input and the digital input are shared by the internal data bus BUS, the both are taken in by the address designation of the register 16 and the address designation timing of the register 15. It is to do something different.

Then, for example, when the terminals P ₄ and P ₅ are used as digital input / output terminals, a program is constructed so that the input data to the register 17 for controlling the multiplexer 13 is not selected from the above-mentioned terminals, and at the same time, the terminal P ₄ ，
Latch 15 in the register 15 corresponding to the P ₅
When addressing a, 16b, etc., a program is set up that handles digital signals.

In this case, the input / output of the digital signal including the terminals P ₄ and P ₅ is switched by setting the directionality by setting and resetting the latch circuit 15c and the like in the register 15.

For example, when the latch output is "0", the output buffer amplifier 12b and the like are set to high impedance to handle the input signal, and when the latch output is "1", the output buffer amplifier 12b and the like are operated. And handle the output signal.

Therefore, when the shared terminals P ₄ and P ₅ are used as analog input terminals, the multiplexer 13 via the register 17 selects the latch output and outputs the latch output for setting the direction as "0". The buffer amplifier has a high impedance to enable the input of an analog input signal.

In this case, the register 15 corresponding to the terminals P ₄ and P ₅
The addressing of the latch circuits 15a and 15b in FIG.

As described above, the transfer of the digital signal to and from the external circuit with respect to the register 15 for the digital signal which is not shared is performed.
This is performed by making the address designation timing different from that of the register 16.

The integrated circuit of FIG. 1 is used for controlling the engine, although not particularly limited thereto.

Therefore, for example, the engine cooling water temperature detection thermistor DET ₁ is connected between the terminal P ₁ and the ground point of the circuit, and the load resistance R ₁ is connected between the thermistor DET ₁ and the power supply terminal V _B. It By using the thermistor DET ₁ having a negative temperature coefficient, the voltage applied to the terminal P ₁ decreases as the temperature of the cooling water rises.

Similarly, the thermistor DET ₂ for measuring the intake air temperature of the engine and its load resistance R ₂ are connected to the terminal P ₂ .

The intake flow meter DET ₃ is connected to the terminal P ₃ .
This intake air flow meter is configured to have a resistance piece and a slide contact whose position changes with respect to the resistance piece according to the intake air flow rate. Therefore, this intake flow rate meter outputs a voltage according to the intake flow rate.

An engine tachometer DET ₄ is connected to the terminal P ₄ . This tachometer outputs a voltage according to the engine speed to the terminal P ₄ .

A starter switch SW is connected to the terminal P ₅ .

The crank angle sensor DET _{5 of the} engine is connected to the terminal P _6.
Are connected. This sensor DET ₅ outputs a pulse signal when the crank reaches a specific angle, for example 0 °.

The terminal P ₇ is, for example, an output terminal for warning the engine temperature. The lamp PL is driven by the buffer circuit 30 which receives the output from the terminal P ₇ and is turned on when the engine reaches an abnormal temperature.

The peripheral circuit 21 is supplied with a control signal from the external terminal group CONT, an address signal from the address bus AD, and data from the data bus DT. This peripheral circuit 21
Has a plurality of output lines l ₁ to l ₄ , and includes therein a storage circuit (not shown) which is selected by the address signal of the address bus AD and whose state is determined by the data signal of the data bus DT.

The signal on the output line l ₁ of the peripheral circuit 21 is supplied to the ignition coil 26 via the output buffer circuit 22, and the signal on the output line l ₂ is supplied via the output buffer circuit 23 to the throttle valve in the intake manifold of the engine. Is supplied to the solenoid 27 for adjusting. The signal on the output line l ₃ is supplied to the electromagnetic fuel pump 28 via the output buffer circuit 24, and the signal on the output line l ₄ is supplied to the relay 29 for driving the starter motor of the engine.

In FIG. 1, a read-only memory (ROM) 19 for engine control is configured to store, together with a program, interpolation data determined by the characteristics of the engine to be controlled.

In FIG. 1, when the key switch S ₀ is closed, the power supply voltage is supplied from the battery B to the constant voltage circuit 40, and the power supply voltage V _B is supplied from the constant voltage circuit 40 to the above circuits. Become so.

With the microprocessor 1 in the operating state,
Analog data such as engine cooling water temperature and intake air temperature obtained from the thermistors DET ₁ and DET ₂ are converted into digital data by the analog digital conversion circuit 14 in a time division manner. Each converted digital data is written in a random access memory (RAM) via a data bus.

The output from the peripheral circuit 21 activates the fuel pump 28.

When the starter switch SW is closed, the relay 29 is activated and the starter motor (not shown) starts operating.

In order to reduce the capacity of the ROM 19, the data in the ROM 19, for example regarding the ignition timing, is associated only with a particular sampled speed.

Therefore, the ignition timing data for the arbitrary engine speed from the tachometer DET ₄ is obtained by a calculation for correcting the interpolation data at the sampling speed close to the arbitrary engine speed in the ROM 19 by the arbitrary speed. To be

The actual ignition timing is calculated from the ignition reference time based on the output from the crank angle sensor DET ₅ and the ignition timing data obtained by the above calculation. Based on this, the ignition coil 26 is driven.

Interpolation data for controlling the throttle valve in the ROM 19 is referred to by the engine speed data and the engine cooling water temperature data, and a pulse control signal for controlling the throttle valve is formed by a similar calculation. By this pulse control signal, the duty ratio of the pulse current of the solenoid 27 coupled via the peripheral circuit 21 is changed. The average current of the solenoid 27 is changed by the duty ratio of the pulse current, and as a result, the throttle valve is controlled according to the duty ratio.

According to the embodiments described above, the sharing of the terminals as described above allows a small number of terminals and different requirements, in other words,
Various process controls having different numbers of analog signal inputs and digital signal inputs / outputs can be performed, and the versatility of various process controls in automobile engine control of a microprocessor can be improved. And, in order to improve the quality of process control, in other words, to perform high-density control, it is possible to change the system, such as changing the digital input to analog input, by only changing some programs. Is.

The present invention is not limited to the above embodiment, the port 12 is
The input port and the output port may be provided independently of each other. In this case, the terminals are shared between the input port and the analog input.

Further, when the terminals are shared, various modifications can be made, for example, one in which all analog inputs are shared, or one in which all digital inputs are shared.

The system configuration of the microprocessor can be modified in various ways.

Further, the system configuration for controlling various processes is generally a microprocessor, a ROM (or RAM) in which a control program is written, and an R for holding various data.
An analog / digital input / output circuit including the A / D conversion circuit, which is formed by a digital semiconductor integrated circuit of several chips such as AM, has a third circuit, for example.
ROM in which the control program is written as shown in the figure
May be provided in the digital semiconductor integrated circuit 19 constituting the above. That is, the address decoder circuit 20
And the memory array 21 in which the program command word is written
An input / output port 12, a register 15, a multiplexer 13, an A / D conversion circuit 14, and registers 16 and 17 similar to the above are provided in the digital semiconductor integrated circuit 19 constituted by The same operation can be performed by connecting the address bus to the microprocessor via the external data bus and the address bus.

The analog / digital input / output circuit including the A / D conversion circuit may be provided in a digital semiconductor integrated circuit forming the RAM in a digital control system including the RAM, a microprocessor, an R
The same applies to the case where the entire system of OM and RAM is configured by a one-chip digital semiconductor integrated circuit.

[Brief description of drawings]

FIGS. 1 and 3 are block diagrams showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an embodiment of a main part of the present invention. 1 ... Microprocessor, 2 ... Accumulator, 3
... Accumulator latch, 4 ... Temporary register, 5 ...
... Arithmetic logic unit, 6 ... Instruction register, 7 ... Instruction decoder and machine cycle encoder, 8 ... Timing control circuit, 9 ... Register section, 10 ... Address buffer, 11 ... Data buffer, 12 ... Output port, 12a ... Input buffer amplifier, 12b ... Output buffer amplifier, 13 ... Multiplexer, 14 ... A /
D conversion circuit, 15 ... Register, 15a-15c ... Latch circuit, 16 ... Register, 17 ... Control register, 17a ... Latch circuit, 17b ... Decoder circuit, 18 ... Address decoder circuit, 19 ... ROM,
20 ... Address decoder, 21 ... Memory array.

 ─────────────────────────────────────────────────── ───Continuation of front page (56) Reference JP-A-52-55447 (JP, A) (1) SAE Technical Paper Series SAE-790342, 1979 (USA) A. Nedbal "A Single Chip Microcomputer with System Systems Features" PP. 1-9 (2) S2200 / S2200A S2400 / S2400A S2210 Single-Chip, Mitsubishi, Pre-America, Prec.

Claims (3)

[Claims] 1. A microprocessor configured as a one-chip monolithic semiconductor integrated circuit, comprising: a multiplexer that selectively performs a switch operation by a first register to select a plurality of analog inputs in a time division manner; An analog digital conversion circuit that receives an analog signal, an internal bus, and information selected from the internal bus by the selection operation by the output of the address decoder to temporarily store the information, and select the multiplexer according to the information acquired from the internal bus. 1 register and receiving the output information digitalized to the analog signal by the analog digital conversion circuit, temporarily storing the output information, and transmitting the information to the internal bus by a selection operation by the output of the address decoder. Second cash register And a digital signal port having at least a plurality of input circuits for digital signals, and a signal applied to the port is temporarily stored and the information is output to the internal bus by a selection operation by the output of the address decoder. A third register capable of transmitting, a plurality of analog input terminals coupled to the multiplexer, an external terminal commonly connected to a digital input terminal coupled to the port, a general-purpose working register, a stack pointer, and Including a program counter, depending on the instruction, ROM, RAM,
A register unit that outputs address information for selecting the first register, the second register, and the third register to an address bus, and the address information supplied via the address bus is decoded to select the first to third registers. A microprocessor comprising: the address decoder to be operated; 2. The microprocessor according to claim 1, wherein the first register comprises a latch circuit. 3. The microprocessor according to claim 2, wherein the third register comprises a latch circuit.