JPS63271565A - Microprocessor composed of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To preclude malfunction in analog signal processing by making wiring for analog signal supply not cross wiring for digital signal supply. CONSTITUTION:The analog signal line and digital signal line are formed in areas divided by an array of bonding electrodes P1-P6 to be connected to an external terminal as a border. The wiring shown by a solid line is formed of a 2nd aluminum layer together with the bonding electrodes and the wiring shown by a dashed line is composed of a 1st conductive polysilicon layer together with gate electrodes of MISFETs Q16...Q20 as a multiplexer. Further, a part shown by dotted lines are diffusion areas as the source and drain area of the MISFETs. Further, measure marks are contact parts and connect the diffusion areas and 2nd aluminum layer. The analog signal line and digital signal line are formed on a semiconductor chip 1 without crossing each other, so malfunction in analog signal processing is precluded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprocessor constructed from a semiconductor integrated circuit.

For example, even in semiconductor integrated circuit devices constituting digital control circuits, processing analog signals with a large amount of information is useful for highly accurate process control.

In such a semiconductor integrated circuit device, in order to improve the integration density, the first, second, or third layer of metal wiring formed by known multilayer wiring technology is
The internal circuits are connected to each other.

Therefore, in a semiconductor integrated circuit device including a circuit for processing digital signals and a circuit for processing analog signals, for example, as shown in FIG.
In, the first conductive polysilicon layer Po1y-8i formed on the semiconductor substrate Sub is used as an analog signal line, and the glabella insulating film Sin! A second aluminum layer AL that intersects with this via a line is sometimes used as a digital signal line. In this case, the above interlayer insulation! Since 1xS i O, is relatively thin, a relatively large capacitance occurs between both wirings.

In particular, analog signal lines are analog/digital (A/D
) When connected to an electronic circuit with a high input impedance, such as a converter (2ζ), the capacitive coupling has a large effect on the digital signal amplitude and affects the analog signal, causing malfunctions in the analog signal processing operation. ,ru. That is, when the level of the digital signal changes, this level change is transmitted to the analog signal line via the capacitor, changing the level of the analog and log signals. This causes the A/D converter to malfunction.

In addition, as described in the specification of the earlier application (Tokurei Sho 55-18986) proposed prior to this invention, the applicant of the present application has proposed that a common external terminal be used as an analog input terminal and a digital input/output terminal. When selectively used as a signal line, the analog signal line and the digital signal line must be crossed by multilayer wiring, which inevitably causes the above problem.

An object of the present invention is to provide a microprocessor that can be implemented as a semiconductor integrated circuit and prevents malfunctions in analog signal processing.

Another object of the present invention is to provide a microprocessor that can be implemented as a semiconductor integrated circuit in which analog input terminals and digital input/output terminals can be shared and malfunctions in analog signal processing can be prevented.

Still other objects of the invention will become apparent from the following description and drawings.

The present invention will be described in detail below along with examples.

FIG. 2 is a block diagram of a microprocessor and its peripheral devices which can be implemented as a semiconductor integrated circuit suitable for constructing a digital control circuit to which the present invention is applied.

In the figure, l is a microprocessor constructed from a one-chip monolithic semiconductor integrated circuit, and is comprised of circuit blocks 2 to 18, which will be described below. Each of these circuit blocks is a MISFET formed on a semiconductor substrate using known semiconductor integrated circuit technology.
(insulated gate field effect transistor).

Reference numeral 2 is an accumulator, 3 is an achievable register, 4 is a temporary register, and 5 is an arithmetic logic unit. These circuits 2 to 5 constitute an arithmetic unit.

The arithmetic logic unit 5 performs arithmetic operations such as addition and subtraction, or logical judgments such as Mll (or), logical product (AND), and exclusive OR, under the control of the control circuit 8. That is, the arithmetic logic unit 5 operates on inputs of the contents of the temporary register 4 and the contents of the accumulator latch 3, which is the output of the mulrator 2. The arithmetic result of the arithmetic logic unit 5, which varies depending on the control signal based on the instruction word from the control circuit 8, is sent to the achiemulator via the internal data path Bus.

6 is an instruction register, 7 is an instruction decoder and machine cycle encoder, and 8 is a timing control circuit. These circuits 6 to 8 constitute a control section.

The instruction register 6 is used to retrieve program instruction words written in the ROM 19 or RAM 20. The instruction read by the instruction register 6 is decoded by an instruction decoder and converted into various timing signals by a machine cycle encoder. The timing control circuit 8 is connected to an external control terminal group C0NT.
The timing is determined based on input signals from the external data path DT, and a bus control signal for taking in data from the external data path DT and a strobe signal for writing data to the external data path DT are output.

Further, the timing control circuit 8 has an external control terminal group C0NT.
Interrupt signals from , hold signals to stop operation,
A device that examines a series of external signals such as reset signals, and upon receiving these signals, sends a signal indicating that an interrupt will be received and a signal ring series of signals indicating that a hold request has been accepted to the outside. It is.

Reference numeral 9 denotes a register section, which includes a general-purpose working register, a stack pointer, a program counter, etc., although not shown.

The general-purpose working register in the register section 9 is as follows:
In addition to handling data (including double-length data), it is also used when referencing memory. The stack pointer is used to store the return address of a subroutine jump. The program counter is a register that stores the location of the instruction word to be read next, and its contents are incremented by 1 each time an instruction other than a jump instruction is executed.

Reference numeral 18 denotes an address decoder circuit, which receives the output of the general-purpose working register of the register section 9 and outputs a signal for controlling circuits 15 to 17, which will be explained later.

The use of this address decoder circuit 18 allows the circuits 15 to 17 to be controlled by a small number of general-purpose working registers.

10 is an address buffer, ROMI 9°RA
It outputs an address signal for supplying M20 and the peripheral circuit 211C.

Reference numeral 11 denotes a data puff, which transmits and receives data between the external data path DT and the internal data path BUS.

Reference numeral 12 denotes a five-person output port for exchanging digital signals with a controlled object in process control, etc., and transmits signals to an internal data path via a register 15. In this embodiment, some of the digital signal terminals (for example, P4, Ps) are
As will be explained later, it is also used as an analog input terminal.

A multiplexer 13 selectively inputs a plurality of analog input signals to the A/D conversion circuit 14. This multiplexer 13 has, as a part of its input,
The digital input/output terminals P, , P, are shared. In other words, the terminals P1 to P are dedicated analog input terminals, and the terminal P4=Ps is a common terminal for analog and digital.

The digitized output signal of the upper A/D conversion circuit 14 is transmitted to the internal data path BUS via the register 16.

Although not particularly limited, the A/D conversion circuit 14 is a sequential comparison type A/D conversion circuit.

In a sequential comparison type A/D conversion circuit, an input analog signal is applied to an operational amplifier. For this reason, the above A/
The input impedance of the D conversion circuit 14 is relatively high.

A control register 17 forms a selection signal for the multiplexer, and reads the signal of the internal data path BUS under the control of the address decoder circuit 18.

When using the above shared terminals P, , P as Otaman terminals for digital signals, the multiplexer 13 or A
This is done by inhibiting input or output by the /D conversion circuit 14 (which may also be done by the register 16).On the other hand, when the shared terminals p4 and p are used as analog input terminals, the human output port 12 By setting the corresponding circuit to high impedance, the analog signal from the terminal is input to the A/D conversion circuit 14.

This will be easily understood by referring to a specific example circuit shown in FIG.

transmission) M I S F E T Qss-Qss
A register 1 that controls a multiplexer 13 consisting of
7 is composed of a latch circuit 17a and a decoder circuit 17b, and the latch circuit 17aK is a transmission group) M
Internal data path BUS via ISFETQt~Q,
The signal from is set. Transmission above) MISFE
TQ, to Q, are selected by the address decoder circuit 18. Therefore, by specifying a specific address given to the register 17 and inputting the multiplexer selection data to the latch circuit forming the register 17 via the internal gate bus BUS, any multiplexer 13 can be selected. An action is performed.

Furthermore, the output of the register 16 into which the A/D conversion output is input is also connected to the corresponding bit line of the internal data path BUS via the transmission MISFETs Qa to Q. address decoder circuit 18 by specifying a specific address given by
This output turns on the MISFETs Q4 to Q6 and inputs the data into the internal data path BUS.

The input/output board 12 for digital signals has each terminal P4 to
For Pn, a manual buffer amplifier 12a, and
An output buffer amplifier 12b is provided,
A gate signal is applied to the output buffer amplifier 12b to control signal transmission.

The register 15 includes a latch circuit 15a provided corresponding to the output of each manual buffer amplifier 12a from the input/output board 12, a latch circuit 15b provided corresponding to the input of each output buffer amplifier 12b, and a latch circuit 15b provided corresponding to the input of each output buffer amplifier 12b. and a latch circuit 15c provided corresponding to the gate input of the output buffer amplifier 12b. The inputs and outputs of the latch circuits 15a, 15b, etc. corresponding to each terminal are respectively connected to the transmission gate MISFETQy-Qa.
- Corresponding internal data path BU via Qta-Qa4
It is connected to the S bit line, each given a specific address, and controlled by the output of the address decoder circuit 18.

In addition, the input of the latch circuit 15c that forms the gate signal of the output buffer amplifier 12b etc. is a transmission gate (MISFE).
TQ* *Q1! .about.QCs are similarly connected to the bit lines of the corresponding internal data path BUS.

As mentioned above, since the digitized analog input and the digital input are shared by the internal data path BUS, the capture of both depends on the address specification of the register 16 and the address specification timing of the register 15. This is done by making the values different.

For example, when terminals P, , P are used as digital input/output terminals, a program is created so that input data to the register 17 that controls the multiplexer 13 does not select signals from the terminals, and terminals P4...
Latch circuit 15a in register 15 corresponding to P.
, 15b, etc., a program is designed to handle digital signals.

In this case, the input/output switching of the digital signals including the terminals P, , and pH is performed by setting the directionality by setting and resetting the latch circuit 15c in the register 15.

For example, when the latch output is set to °O'', the output buffer amplifier 12b etc. are set to high impedance and the input signal is handled, and when the latch output is set to 11'', the output buffer amplifier 12b etc. are operated at 8. In this case, the output signal will be handled as follows.

Therefore, when the shared terminals Pa and Ps are used as analog manual terminals, the selection is made by the multiplexer 13 via the register 17, and the latch output for setting the directionality is set to ``0'' to the output buffer. This makes it possible to input analog input signals by making the amplifier a no-impedance amplifier.

In this case, the terminal P4. Register 15 corresponding to P
Address designation of the latch circuits 15a, 15b, etc. is not performed.

As described above, the transfer of digital signals to and from the external circuit to and from the register 15 for digital signals that are not shared is performed as follows.
This is done by making the addressing timing different from that of the register 16.

The integrated circuit shown in FIG. 2 is used for engine control, although it is not particularly limited. For that purpose, for example, a thermistor DET1 for detecting engine coolant temperature is connected between the single terminal and the ground point of the circuit. A load resistor R is connected between the thermistor DET and the power supply terminal V.

By using a thermistor DET with a negative temperature coefficient, the voltage applied to the terminal P1 decreases as the temperature of the cooling water increases.

Similarly, a thermistor DET for measuring the intake air temperature of the engine and its load resistance R8 are connected to the terminal P.

An intake flow meter DET is connected to the terminal P.

This intake flow rate meter is configured to have a resistor piece and a sliding contact point for the resistor piece whose position changes depending on the intake flow rate. Therefore, this intake flow meter outputs a voltage according to the intake flow rate.

An engine tachometer DET4 is connected to the terminal P4. This tachometer outputs a voltage corresponding to the rotational speed of the engine to the terminal P.

A starter switch SW is connected to the terminal P.

The engine crank angle sensor DET is connected to the terminal P.
is connected. This sensor DET outputs a bias signal when the crank reaches a specific angle, for example 01.

Terminal P is used as an output terminal for, for example, an engine temperature warning. The lamp PL is connected to the above terminal P.

The lamp is driven by a buffer circuit 30 that receives the output of the lamp, and is turned on when the engine temperature reaches an abnormal temperature.

The peripheral circuit 21 is supplied with control signals from the external terminal group C0NT, address signals from the address bus AD, and data from the data path DT.

This peripheral circuit 21 includes a plurality of output lines J1 to ! .

Each memory circuit (not shown) is selected by an address signal on an address bus AD and whose state is determined by a data signal on a data path DT.

The signal on the output line J of the peripheral circuit 21 is supplied to the ignition coil 26 via the output buffer circuit 22, and the signal on the output line J is supplied via the output buffer circuit 23 to the throttle valve in the intake manifold of the engine. It is supplied to a solenoid 27 for regulating the valve. Also, the output line! , is supplied to the electromagnetic fuel pump 28 via the output buffer circuit 24. The signal No. 4 is supplied to a relay 29 for driving the engine cell Tanabata.

In FIG. 2, a read-only memory (ROM) 19 for engine control is configured to store programs as well as interpolated data determined by the characteristics of the engine to be controlled.

In FIG. 2, when the ghee switch S0 is closed, the power supply voltage is supplied from the patch IJB to the constant voltage circuit 40, and the power supply voltage VB is supplied from this constant voltage circuit 40 to each of the above-mentioned circuits. It becomes like this.

By the microprocessor 1 becoming operational,
Thermistor DETs = DET! Analog data such as engine coolant temperature and intake air temperature obtained from the above are converted into digital data in a time-sharing manner by an analog-to-digital conversion circuit 14.

Each converted digital data is written to random access memory (RAM) via a data path.

The output from the peripheral circuit 21 causes the fuel pump 28 to be activated.

When the starter switch SW is closed, the IJL
/-29 is in the operating state and gtt, the starter motor (not shown) starts operating.

In order to reduce the capacity of the ROM 19, the data in this ROM 19, for example relating to the ignition timing, are associated only with specific sampled rotational speeds.

Therefore, the ignition timing data for an arbitrary engine speed from the tachometer DET is obtained by a calculation that corrects the interpolated data at a sampling speed close to the arbitrary engine speed in the ROM 19 by the arbitrary engine speed. Desired.

The actual ignition timing is calculated from the ignition reference time based on the output from the crank angle sensor DET and the ignition timing data obtained by the above calculation. Based on this, the ignition coil 26 is driven.

Interpolated data for controlling the throttle valve in the ROM 19 is referred to based on the engine rotational speed data and the engine coolant temperature data, and a pulse control signal for controlling the throttle valve is formed by similar calculations. This pulse control signal changes the duty ratio of the pulse current of the solenoid 27 coupled via the peripheral circuit 21. The average current of the RUGUID 27 is changed depending on the duty ratio of the pulse current, and as a result, the throttle valve is controlled according to the duty ratio.

In the case where analog input terminals and digital input/output terminals are shared, as in the semiconductor integrated circuit device constituting the microprocessor etc. described above, the conventional wiring layout method As is clear from the circuit diagram, there is a portion where the analog signal line and the digital signal line intersect (overlap). Therefore, the capacitance as described above is generated between the analog signal line and the digital signal line, resulting in malfunction in analog signal processing as described above. That is, for example, when the A/D conversion circuit 14 is converting an analog voltage corresponding to the engine rotation speed output from the tachometer DET4 into a digital signal, the starter switch SW
If the state of
is transmitted to the analog signal line connected to the For this reason,
The A/D conversion circuit 14 converts a voltage higher or lower in level than the analog voltage into a digital signal. In other words, a malfunction occurs in analog signal processing in the A/D conversion circuit 14.

Note that the level of the digital signal changes in a short time, for example from 5 volts to O port, or vice versa, from 0 volts to 5 volts. In other words, the level changes relatively significantly in a short period of time. Therefore, A/D
The level change transmitted to the conversion circuit 14 will be relatively large.

Therefore, in this embodiment, as shown in the layout diagram of FIG. 4, analog signal lines and digital signal lines are divided into areas separated by the arrangement of bonding electrodes P1 to P6 connected to external terminals. It is formed. Although not particularly limited in FIG. 4, the wiring shown by solid lines is composed of the second layer of aluminum together with the bonding electrode, and the wiring shown by dashed dotted lines is for MISFETQ+ as a multiplexer. Or Q.

It is composed of a first conductive polysilicon layer together with a gate electrode. Also, the part indicated by the dotted line is the MISFE
These are diffusion regions as source and drain regions of T. Furthermore, the contact portion is connected to the diffusion region and the second aluminum layer through the contact portion.

In this embodiment, bonding electrodes P, ~P, are arranged around the periphery of the semiconductor chip 1, and analog signal lines made of aluminum wiring are arranged in the area between this arrangement and the edge of the semiconductor chip 1. LA is formed and A/D
It is guided to the input terminal of the conversion circuit 14. In addition, the analog signal IIi! LA is M I as a multiplexer
S F E T Connected to one of the diffusion regions of Qla to Qxo.

On the other hand, in the inner area of the semiconductor chip 1 with respect to the arrangement of the bonding electrodes P, to P6, there is a digital signal line L formed of an aluminum layer and a conductive polysilicon layer.
D is formed. Among these, the digital signal line LD composed of an aluminum layer has M'l5FETQ+e to Q as a multiplexer. and the input/output port 12. Alternatively, the digital signal line may be formed integrally with the bonding electrodes P or P using an aluminum layer, such as the bonding electrode P6.

Furthermore, the above M I S F E T Q so to Q. A digital signal line LD made of a conductive polysilicon layer formed integrally with the gate electrode is connected to the output terminal of the control register 17.

It should be noted that the mutual wiring of the above-mentioned circuits is performed in the areas indicated by the dots in the figure.

In the embodiment described above, the analog signal line and the digital signal line can be formed on the semiconductor chip 1 without crossing each other, so that malfunctions in analog signal processing as described above can be prevented.

As shown in Fig. 2 or 3, when analog input terminals and digital input/output terminals are shared, the number of terminals can be reduced and the requirements differ, in other words, the number of analog signal inputs can be increased. , it becomes possible to control various processes with different numbers of digital signal inputs and outputs, and in order to perform high-density control in automobile engineering using microprocessors, it is possible to perform system changes such as changing digital inputs to analog inputs. This can be done by simply changing some programs.

The invention is not limited to the above embodiments.

The analog signal line and the digital signal line may use a diffusion layer in addition to the aluminum layer and the conductive polysilicon layer, and the combination thereof can be changed in various ways.

Further, it is not necessary that both the analog signal line and the digital signal line are connected to the bonding electrode, and the analog signal line and the digital signal line connected to the analog signal processing circuit whose input impedance is high are connected to the bonding electrode. The present invention can be widely applied to semiconductor integrated circuits having the following characteristics.

Further, the analog signal line and the digital signal line may be connected to the bonding electrode independently, or may be partially or completely shared. In this case,
It is desirable to form each in an area divided by the arrangement of the bonding electrodes in order to simplify or increase the density of the wiring layout. Further, the bonding electrodes do not need to be arranged around the semiconductor chip, and may be formed anywhere inside the semiconductor chip as the size of the semiconductor chip increases.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a known example of multilayer wiring, and FIG.
FIG. 3 is a block diagram showing an embodiment of a semiconductor integrated circuit device to which the present invention is applied, FIG. 3 is a circuit diagram of the main part thereof, and FIG. 4 is a layout diagram showing an embodiment of the present invention. 1...Microprocessor (semiconductor chip), 2...
・Accumulator, 3... Accumulator latch, 4 Temporary register, 5... Arithmetic logic unit, 6... Instruction register, 7... Instruction decoder and machine cycle encoder, 8... Timing control circuit, 9. ...Register section, 10...Address buffer, 11...Data buffer, 12...I/O port, 12a...Input buffer amplifier, 12b...Output buffer amplifier,
13... Multiplexer, 14... A/D conversion circuit, 15... Register, 15a to 15c... Latch circuit, 16... Register, 17... Control register, 17a... Latch circuit , 17b...decoder circuit, 18...address decoder circuit, 19...R
OM. 20...RAM, 21...peripheral circuit, 22-25.
...Output huffer 00 path, 26...Ignition coil, 27...Renoid, 28...Electromagnetic fuel pump, 29...Relay, 40...Constant voltage circuit. Figure 1, Figure 2 1Ii+ Figure 3

Claims (1)

[Claims] 1. A first wiring to which a digital signal is supplied;
a first circuit coupled to the wiring; a second wiring to which an analog signal is supplied; a second circuit that processes the analog signal supplied via the second wiring; 1. A microprocessor constructed of a semiconductor integrated circuit, comprising selection means for selecting two circuits, and wherein the second wiring is prevented from intersecting with a wiring for supplying digital signals. 2. A plurality of selection means are provided between the second wiring and the plurality of contacts, each of which is controlled in operation by a digital control signal and selectively supplies the signals of the plurality of contacts to the second wiring, The second wiring extends to one side of the array of the plurality of contacts, and a plurality of control wirings for digital control signals for the plurality of selection means extend to the other side of the array. A microprocessor constructed of the semiconductor integrated circuit according to claim 1. 3. A microprocessor configured with a semiconductor integrated circuit according to claim 2, wherein the plurality of connection points are electrodes for external connection of the semiconductor integrated circuit. 4. The semiconductor integrated circuit according to claim 3, wherein the second wiring extends over a region located on the peripheral edge side of the semiconductor chip with respect to the arrangement of the electrodes. microprocessor. 5. A microprocessor constructed of a semiconductor integrated circuit according to any one of claims 2 to 4, wherein the selection means comprises a transmission gate MISFET that receives a digital control signal at its gate. . 6. The second circuit is provided between an analog/digital conversion circuit that uses the analog signal supplied via the second wiring as an input signal to be converted, and the analog/digital conversion circuit and an internal data path. Claims 3 to 5, characterized in that
A microprocessor configured with the semiconductor integrated circuit according to item 1. 7. The semiconductor according to any one of claims 3 to 6, wherein the electrode can be used commonly for digital signals and for signal input to the second circuit. A microprocessor made up of integrated circuits.