JPH03240145A - Memory using method for vehicle electronic controller - Google Patents

Abstract

PURPOSE:To attain the effective use of memories and to decrease the number of memories installed and the dark current of a battery by storing in sequence each data into the memories without generating idle bits. CONSTITUTION:The 6-bit data on a RAM (n) is stored in an 8-bit BRAM which is backed up by a battery (n: memory address of RAM). In this case, 6(n-1)/8 is calculated and the data read out of the RAM (n) and sent to a main register is shifted to the higher rank side by 2 bits and then saved to a secondary register as long as said calculation produces a remainder 0. Then the 2nd-7th bits of the main register are cleared and the contents of the RAM (n) are shifted to the 2nd-7th bits after an OR logic is secured between the main and secondary registers. Then the contents of the RAM (n) are written into the BRAM. Thus the 6-bit data are continuously stored into the BRAM without generating idle bit. As a result, the memory capacity is reduced and the installing space is also reduced. Furthermore the dark current of the battery can be suppressed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method of using memory in a vehicle electronic control device.
In particular, it relates to memory usage methods that aim to make effective use of memory space.

[Prior art and its section M] In recent years, vehicles are equipped with various electronic control devices including engine control devices.
Many ICs such as a microcomputer, memory, and input/output interface are integrated onto a single board. Of these, memory usually occupies the largest space, and as control becomes more sophisticated in recent years, an increase in memory space due to an increase in the amount of data used has become a problem.

Furthermore, in vehicles and the like, important data such as failure diagnosis data is stored in a battery-backed memory, but as the number of memory chips increases, there is also the problem that the dark current of the battery increases.

On the other hand, in memory, one byte (8 bits) is usually a word, but there are many pieces of data that are less than 8 bits in length, and in the past, each piece of data with a small number of bits occupied one word of memory. ing.

The present invention has been made in view of this background, and provides a method of using memory in a vehicle electronic control device that can significantly reduce the number of installed memories and battery dark current by effectively using memory. .

[Means for Solving the Problems] The present invention is described in detail as a method of using a memory of an electronic control device in which the number of word bits of the memory and the number of word bits of data are different, and the number of word bits of the memory is different from the number of word bits of the data. The data is shifted by a predetermined number of bits in each processing procedure selected according to the identification number of each data. The data read from the memory address determined by the identification number, with the bits corresponding to the shifted data cleared, is logically summed with the shifted data, and then this logical sum data is calculated. By storing the data at the above memory address again, each data is sequentially and continuously stored without creating any empty bits in the memory.

[Operation] According to the above method, data is stored sequentially and consecutively in the memory without creating empty bits, so that data whose number of word bits or the number of remaining bits is smaller than the number of word bits in the memory are stored in the memory. The memory capacity is significantly reduced, the installation space is reduced, and the battery dark current is also suppressed.

[Example] The engraving drawing shows an example of a vehicle electronic control device to which the method of the present invention is applied. The electronic control unit is backed up by a microcomputer (CPU) 11, a read-only memory (ROM>12 for storing control programs), a random access memory (RAM) 13 for storing data, and a battery 2 for storing important data. It consists of a random access memory (BRAM) 14, an input port 15, an output port 16, etc., and each general element chip is supplied with operating power from a power supply circuit 18 connected to a battery 2 via a key switch 3. And in BRAM14,
Operating power is supplied from a power supply circuit 17 directly connected to the battery 2.

Detection signals are input to the input boat 15 from an air-fuel ratio sensor 4a, a rotation speed sensor 4b, a cylinder discrimination sensor 4C, a throttle opening sensor 4d, etc. provided in the engine system. Further, an output signal is issued from the output port 16 to the fuel injection valve 4e and the like.

In such an electronic control unit, the number of word bits of various data handled by the CPU II is 6 bits, and the RAM
13. The method of the present invention will be described below for the case where the word bit number of the BRAM 14 is 8 bits.

In FIG. 2, a RAM (1
) to RAM (4) respectively contain 6-bit data [A], [B], [C], [D] from the Oth bit to the 5th bit.
] is memorized. These 6-bit data [A] to [
If D] is stored continuously in a BRAM with a word bit count of 8 bits without creating any empty bits, the memory count of BRAM(1) to BRAM(3) can be 3 bytes as shown in the figure.

The processing procedure for realizing this is shown in FIG. The diagram shows RAM (
This explains the case where 6-bit data of n> is stored in an 8-bit BRAM, and in step 101, 6(n
-1)/8= to obtain the remainder 91. Depending on whether this remainder 1 is O52, 4, or 6, four types of processing procedures, steps 102 to 106, steps 107 to 111, steps 112 to 116, and steps 117 to 121, are selected and executed. In the figure, R1 and R2 are main registers in the computer, R1\R2- are sub-registers, and R1 and R1- are on the upper side.

For example, if n of RAM(n) is 1.5.9, . . . , the remainder 1 is O, and steps 102 and subsequent steps are executed. In step 102, the RAM (
The data read from n> to the main register R1 is shifted 2 bits to the left (upper side) and saved to the sub register R1-.

In step 103, the BRAM (
k+1) is read to main register R1. This BR
AM is BRAM for each n=1.5.9...
(1), BRAM (4>, BRAM (7)...

Next, the second to seventh bits of the main register R1 are cleared (Step 104), and the OR logic of the main register R1 and the sub-register R1- is performed (Step 105>. As a result, the contents of RAM(n) are changed to the above-mentioned values. The data is transferred to the second to seventh bits, and is written to BRAM (k+1>) to complete the process (step 106).

If n is 2,6,10... in step 101, the remainder 1 becomes 6, and steps 107 and subsequent steps are executed.

In step 107, the RAM read into the main register R1
Shift the data of (n) by 4 bits to the right (toward main register R2), and shift the data of main register R1 to the 0th bit and 1st bit,
The data moved to the fourth to seventh bits of the main register R2 are saved to the sub registers R1+ and R2-.

Next, BRAM (k+1>,
The contents of BRAM (k+2) are stored in main register R1.
, R2. This BRAM is R2, 6, 10...
・(BRAM(1), BRAM(
2)), (BRAM (4), BRAM (5)), (
This is a pair of BRAM (7) and BRAM (8〉〉).

Next, the 0th bit and 1st bit of the main register R1,
and clear the 4th to 7th bits of the main register R2. Step 109>, OR the main register R1 and the sub register R1- and the main register R2 and the sub register R2-.
Take logic (step 11O).

As a result, the contents of RAM (n>) are moved to the 0th and 1st bits of main register R1 and the 4th to 7th bits of main register R2.Then, the contents of these main registers are transferred to BRAM(k+1)BRAM. (k+2>) and the process ends (step 111).

In this way, four types of processing procedures are selected depending on the value of n in RAM(n), that is, the memory address in RAM, and the BRA
Six bits of data are stored continuously in M without any empty bits.

Next, the case of reading data from BRAM to RAM (n>) will be explained with reference to FIG.

In step 201, the remainder 1 is calculated according to the value of n,
Depending on this surplus value, four types of procedures are selected: steps 202 and below, steps 204 and below, steps 206 and below, and steps 208 and below.

That is, if the remainder 1 is 0, BRAM(k+1)
Step 202 to read data to the main register>
, 2 bits to the right (step 203), the unnecessary sixth and seventh bits are cleared and written to RAM(n) (steps 209 and 210).

As a result, 6-bit data is obtained in the 0th bit to the 5th bit of the RAM (n).

Also, if the remainder 1 is 6, BRAM (k+1>
, BRAM (step 204 of reading data from k+2> to main registers R1 and R2 respectively), the whole is 4
The bits are shifted to the left (step 205) and the target data is obtained from the 0th bit to the 5th bit of the main register R1.Then, the 6th bit and the 7th bit are cleared, and the RAM is
(n) (steps 209 and 210).

Hereinafter, in each case where the remainder is 4.2, the desired data can be obtained in the RAM (n>) through steps 206, 207 to 208, and steps 209, 210.

According to the above embodiment, for example, the data in the RAM (101) is stored in the BRAM (76), so 25 bytes of BRAM can be saved compared to the conventional method, and this effect increases as the number of data increases. The larger the difference between the number of word bits of the memory and the number of word bits of the processing data, the larger the difference.

In this way, it is possible to reduce the installation space of the BRAM, and the dark current of the backup battery is also reduced.

In addition, in the above embodiment, control data transfer between the - time storage RAM and the power-backed BRAM was explained, but if the method of the present invention is used to store data in the RAM when the BRAM is not used, the RAM The installation space can be significantly reduced.

Further, in the above embodiment, the case where the number of data bits is smaller than the number of word bits of the memory has been described, but the method of the present invention can also be applied when the number of data bits is larger and there is a surplus number of bits. .

[Effects] As described above, according to the memory usage method of the present invention, since the memory area can be used without wasting the memory area, the memory installation space can be reduced, and the battery capacity for memory backup can also be reduced. It can be suitably used in electronic control devices.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of an electronic control device to which the method of the present invention is applied, FIG. 2 is a conceptual diagram showing the state of memory usage in the present invention, and FIGS. 3 and 4 are diagrams showing the method of the present invention. This is an example of a flowchart of a program to be executed. ■...Electronic control unit 11...Microcomputer (CPU) 13...
Random access memory (RAM) 14... Backup random access memory (BRAM) 17.18... Power supply circuit 2... Key switch 3... Battery Figure 1 Figure 2 BRAM (1) SRAM (2) BRAM (3) 17 14 13 12 11

Claims (1)

[Claims] A method of using a memory of an electronic control device in which the number of word bits of the memory and the number of word bits of the data are different, the method having a type of processing procedure equal to the ratio of the number of word bits of the memory to the number of word bits of the data, and each data The data is shifted by a predetermined number of bits in each processing procedure selected according to the identification number of the data, and the data read from the memory address determined by the identification number in each processing procedure is shifted. After clearing the bits corresponding to the above-mentioned data and the above-mentioned shifted data, the logical sum data is stored in the above-mentioned memory address again, thereby storing each data in the above-mentioned memory. A method for using memory in a vehicle electronic control device, characterized in that memory is stored continuously without creating empty bits.