JPS6346464B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital control system, and particularly to a digital control system using a monolithic semiconductor integrated circuit including an analog-to-digital conversion circuit (hereinafter referred to as an A/D conversion circuit).

By using semiconductor integrated circuits in digital control systems, it becomes possible to miniaturize the devices constituting the systems, and it also becomes possible to reduce the number of connections outside the semiconductor integrated circuits.

Process control using microprocessor,
In order to perform high-quality system control as a control system that performs calculation control, etc., a system that inputs analog signals with a large amount of information via an A/D conversion circuit as well as digital signals as various sensor signals is considered. ing.

In this case, in order to downsize the device and reduce the number of external connections, an input circuit that supplies the above-mentioned digital signal to the data bus of the microprocessor, and an input circuit that converts the analog signal into a digital signal and supplies it to the data bus of the microprocessor. It is desirable that the circuit be configured as a one-chip monolithic semiconductor integrated circuit.

However, when attempting to form a monolithic semiconductor integrated circuit as described above, the number of external terminals provided on the monolithic semiconductor integrated circuit for digital signal input and analog signal input increases. Furthermore, if the number of external terminals that can be provided on a monolithic semiconductor integrated circuit is limited due to limited external dimensions, etc., the functions that can be realized by the control system are restricted due to the limitation of external terminals. Become.

Therefore, it becomes difficult to use one type of monolithic semiconductor integrated circuit for multiple purposes.

For example, if a monolithic semiconductor integrated circuit has many analog input terminals, it becomes unsuitable for control with many digital signals input.
On the other hand, if a large number of digital input terminals are provided, it becomes unsuitable for control that requires many analog signals as input. Furthermore, it becomes difficult to change the system to high-quality control by switching from a digital input signal to an analog input signal.

SUMMARY OF THE INVENTION Accordingly, one object of the present invention is to provide a digital semiconductor integrated circuit that constitutes at least a portion of a digital control system with a reduced number of terminals and increased versatility.

Another object of the present invention is to provide a digital control system using the digital semiconductor integrated circuit described above.

Further objects of the invention will become apparent from the following description and drawings.

According to the present invention, at least a portion of the analog input terminal and a portion of the digital input terminal are shared, and the shared terminal is selectively used as a digital input terminal or an analog input terminal by a program.

The digital input terminal is also used as a digital output terminal if necessary. As a result, the number of external terminals can be further reduced compared to the case where only input terminals are used as described above.

Hereinafter, this invention will be explained in detail together with examples.

FIG. 1 is a block diagram showing one embodiment of the present invention.

Reference numeral 1 denotes a microprocessor made up of a one-chip monolithic semiconductor integrated circuit, and is made up of circuit blocks 2 to 18, which will be described below.

2 is an accumulator, 3 is an accumulator latch, 4 is a temporary register, and 5 is an arithmetic logic unit. These circuits 2 to 5 constitute an arithmetic section.

The arithmetic logic unit 5 performs arithmetic operations such as addition and subtraction, or logical judgments such as logical sum (OR), logical product (AND), and exclusive logical sum, under the control of the control circuit 8. That is, the arithmetic logic unit 5 reads the contents of the temporary register 4 and
The calculation is performed using the output of the accumulator 2 and the contents of the accumulator latch 3 as input. The arithmetic result of the arithmetic logic unit 5, which varies depending on the control signal based on the instruction word from the control circuit 8, is sent to the accumulator via the internal data bus BUS.

6 is an instruction register, 7 is an instruction decoder and machine cycle encoder, and 8 is a timing control circuit. These circuits 6 to 8 constitute a control section.

The above instruction register 6 is ROM19 or RAM2
This is for extracting the program instruction word written in 0. The instructions read out by the instruction register 6 are decoded by an instruction decoder and converted into various timing signals by a machine cycle encoder.

The timing control circuit 8 has a group of external control terminals.
It measures the timing based on the clock signal input from CONT and outputs a bus control signal to take in data from the external data bus DT and a strobe signal to write data to the external data bus DT.

In addition, the timing control circuit 8 is a group of external control terminals.
Examine a series of external signals such as interrupt signals from CONT, hold signals that stop operation, and reset signals, and then, in response to these signals,
It sends out a series of signals such as a signal indicating that an interrupt has been received and a signal indicating that a hold request has been accepted.

Reference numeral 9 denotes a register section, which includes a general-purpose working register, a stack pointer, a program counter, etc., although not shown.

The general-purpose working register in the register section 9 is used not only to handle data (including double-length data) but also to refer to memory. The stack pointer is used to store the return address of a subroutine jump. The program counter is a register that stores the location of the instruction word to be read next, and its contents are incremented by 1 every time one instruction is executed, except for jump instructions.

Reference numeral 18 denotes an address decoder circuit, which receives the output of the general-purpose working register of the register section 9 and outputs a signal for controlling circuits 15 to 17, which will be described later. This address decoder circuit 1
8 allows the circuits 15 to 17 to be controlled by a small number of general-purpose working registers.

10 is an address buffer, and ROM1
9, for outputting address signals to be supplied to the RAM 20 and peripheral circuits 21.

Reference numeral 11 denotes a data buffer, which transmits and receives data between the external data bus DT and the internal data bus BUS.

Reference numeral 12 denotes an input/output port for transmitting and receiving digital signals with a controlled object in process control, etc., and transmits signals to an internal data bus via a register 15. In this embodiment, some of the digital signal terminals (for example, P ₄ and P ₅ ) are also used as analog input terminals, as will be explained later.

A multiplexer 13 selectively inputs a plurality of analog input signals to the A/D conversion circuit 14. This multiplexer 13 has the digital input/output terminals as part of its inputs.
P ₄ and P ₅ are shared. That is, the terminal
P ₁ to _{P 3} are analog-only input terminals, and terminals P ₄ ,
_P5 is a common terminal for analog and digital.

The digitized output signal of the A/D conversion circuit 14 is transferred to an internal data bus via a register 16.
This is what is transmitted to the BUS.

17 is a control register that forms a selection signal for the multiplexer, and is controlled by the address decoder circuit 18 to control the internal data bus.
It reads BUS signals.

When using the shared terminals P ₄ and P ₅ as digital signal input/output terminals, input or output should be prohibited by the multiplexer 13 or the A/D conversion circuit 14 (the register 16 may also be used). On the other hand, when the shared terminals P ₄ and P ₅ are used as analog input terminals, the corresponding output circuit of the input/output port 12 is set to high impedance, so that the analog signal from the terminal is input to the A/D. This is taken into the conversion circuit 14.

This can be easily understood by referring to a specific example circuit shown in FIG.

The register 17 that controls the multiplexer 13 made up of transmission gates MISFETQ ₁₆ to _{Q 20} is made up of a latch circuit _17a and a decoder circuit _17b . , internal data bus
The signal from BUS is set. The above transmission gates MISFETQ ₁ to _{Q 3} are address decoder circuit 1
8 is selected. Therefore, by specifying a specific address given to the register 17 and inputting the multiplexer selection data to the latch circuit forming the register 17 via the internal data bus BUS, the selection operation of any multiplexer 13 can be performed. is to be carried out.

Also, register 1 to which the A/D conversion output is input.
The output of 6 is also connected to the corresponding bit line of the internal data bus BUS via transmission gates _MISFETQ4 to _Q6 , and by specifying a specific address given to the register 16, The above is the output of the address decoder circuit 18.
Internal data bus with MISFETQ ₄ to Q ₆ on
This is to be imported into the BUS.

The input/output port 12 for digital signals is provided with an input buffer amplifier 12a and an output buffer amplifier 12b for each terminal _P4 to _P0 , respectively.
A gate signal is applied to b to control signal transmission.

The register 15 includes a latch circuit 15a provided corresponding to the output of each input buffer amplifier 12a from the input/output port 12, a latch circuit 15b provided corresponding to the input of each output buffer amplifier 12b, and each output buffer amplifier. 12b, and a latch circuit 15c provided corresponding to the gate input of gate 12b. The inputs and outputs of the latch circuits 15a, 15b, etc. corresponding to each terminal are connected to the bit line of the corresponding internal data bus BUS via transmission gates _MISFETQ7 , _Q8 to _Q13 , _Q14 , respectively. A specific address is given to each of them and controlled by the output of the address decoder circuit 18.

Furthermore, the input of the latch circuit 15c that forms the gate signal of the output buffer amplifier 12b etc. is similarly connected to the corresponding bit line of the internal data bus BUS via the transmission gates _MISFETQ9 , _Q12 to _Q15 . .

As mentioned above, digitized analog inputs and digital inputs are connected to the internal data bus BUS.
Therefore, the import of both requires address specification of register 16 and register 1.
This is done by making the addressing timing different from that of No. 5.

For example, when terminals P ₄ and P ₅ are used as digital input/output terminals, a program is created so that input data to the register 17 that controls the multiplexer 13 does not select signals from the terminals, and terminals P _{4 and 5} are used as digital input/output terminals. , _P5 , etc., in the register 15, a program is designed to handle digital signals.

In this case, the input/output switching of the digital signals including the terminals P ₄ and P ₅ is performed by setting the directionality by setting and resetting the latch circuit 15c in the register 15.

For example, if the latch output is set to “0”,
It is assumed that the output buffer amplifier 12b and the like are set to high impedance to handle the input signal, and when the latch output is set to "1", the output buffer amplifier 12b and the like are operated to handle the output signal.

Therefore, when the shared terminals P ₄ and P ₅ are used as analog input terminals, the selection is made by the multiplexer 13 via the register 17, and the latch output for setting the directionality is set to "0". This makes it possible to input analog input signals by setting the output buffer amplifier to high impedance.

In this case, addressing of the latch circuits 15a, 15b, etc. in the register 15 corresponding to the terminals _P4 , _P5 is not performed.

Register 15 for digital signals that are not shared
Transferring digital signals to and from external circuits is as follows:
As mentioned above, this is done by differentiating the address designation timing from the register 16.

The integrated circuit of FIG. 1 is used for, but not limited to, engine control.

For this purpose, for example, connect a thermistor for engine coolant temperature detection between terminal _P1 and the ground point of the circuit.
DET ₁ is connected, and a load resistor R ₁ is connected between this thermistor DET ₁ and the power supply terminal V _B. By using a negative temperature coefficient as the thermistor DET ₁ , the voltage applied to the terminal P ₁ is
It decreases as the temperature of the cooling water increases.

Similarly, a thermistor DET ₂ for measuring the intake air temperature of the engine and its load resistance R ₂ are connected to the terminal P ₂ .

An intake flow meter DET ₃ is connected to the terminal P ₃ . This intake flow rate meter is configured to have a resistor piece and a sliding contact point for the resistor piece whose position changes depending on the intake flow rate. Therefore, this intake flow meter outputs a voltage according to the intake flow rate.

The engine tachometer DET ₄ is connected to the terminal P ₄ . This tachometer outputs a voltage corresponding to the rotational speed of the engine to the terminal _P4 .

A starter switch SW is connected to terminal _P5 .

Terminal P ₆ is the engine crank angle sensor
DET ₅ is connected. This sensor DET ₅ outputs a pulse signal when the crank reaches a certain angle, for example 0°.

Terminal _P7 is used as an output terminal for, for example, an engine temperature warning. The lamp PL is driven by the buffer circuit 30 which receives the output from the terminal _P7 , and is turned on when the engine temperature reaches an abnormal temperature.

The peripheral circuit 21 is supplied with control signals from the external terminal group CONT, address signals from the address bus AD, and data from the data bus DT.
This peripheral circuit 21 has a plurality of output lines _l1 to _l4 , each of which has a memory circuit (not shown) selected by the address signal of the address AD and whose state is determined by the data signal of the data bus DT. (not included).

The signal on the output line _l1 of the peripheral circuit 21 is transmitted to the ignition coil 2 via an output buffer circuit 22.
6, and the signal on output line _l2 is supplied to solenoid 2 for regulating the throttle valve in the intake manifold of the engine via an output buffer circuit 23.
7. Further, the signal on the output line _l3 is supplied to an electromagnetic fuel pump 28 via the output buffer circuit 24, and the signal on the output line _l4 is supplied to a relay 29 for driving the starter motor of the engine.

In FIG. 1, a read-only memory (ROM) 19 for engine control is configured to store programs as well as interpolated data determined by the characteristics of the engine to be controlled.

In FIG. 1, when key switch _S0 is closed, power supply voltage is supplied from battery B to constant voltage circuit 40, and power supply voltage _VB is supplied from this constant voltage circuit 40 to each of the above-mentioned circuits. It becomes like this.

When the microprocessor 1 becomes operational, analog data such as engine coolant temperature and intake air temperature obtained from the thermistors DET ₁ and DET ₂ are converted into digital data in a time-sharing manner by the analog-to-digital conversion circuit 14. converted into data. Each converted digital data is transferred to random access memory (RAM) via a data bus.
will be written to.

The output from the peripheral circuit 21 causes the fuel pump 28 to be activated.

By closing the starter switch SW, the relay 29 is brought into operation, and the starting motor (not shown) starts operating.

In order to reduce the capacity of ROM19, this
For example, data regarding ignition timing in the ROM 19 is associated only with a specific sampled rotation speed.

Therefore, the ignition timing data for any engine speed from the tachometer DET ₄ is stored in ROM1.
The interpolated data at a sampling rotation speed close to the above-mentioned arbitrary engine rotation speed within 9 is calculated by correcting the interpolation data by the above-mentioned arbitrary rotation speed.

The actual ignition timing is calculated from the ignition reference time based on the output from the crank angle sensor DET ₅ and the ignition timing data obtained by the above calculation. Based on this, the ignition coil 26
is driven.

Interpolated data for controlling the throttle valve in the ROM 19 is referred to based on the engine rotational speed data and the engine coolant temperature data, and a pulse control signal for controlling the throttle valve is formed by similar calculations. The duty ratio of the pulse current of the solenoid 27 coupled via the peripheral circuit 21 is changed by this pulse control signal. The average current of the solenoid 27 is changed depending on the duty ratio of the pulse current, and as a result, the throttle valve is controlled according to the duty ratio.

According to the embodiment described above, by sharing the terminals as described above, it is possible to perform various process controls with different requirements, in other words, with different numbers of analog signal inputs and digital signal inputs/outputs, with a small number of terminals. Therefore, it is possible to improve the versatility of various process controls for microprocessors such as automobile engine control. In order to improve the quality of process control, in other words, to perform high-density control, system changes such as changing digital input to analog input can be made by simply changing a part of the program. It is.

The present invention is not limited to the embodiment described above, and the port 12 may be provided with an input port and an output port independently. In this case, the terminal is shared between the input port and the analog input.

Further, when terminals are shared, various changes can be made, such as, for example, all analog inputs being shared, or all digital inputs being shared.

In addition, the system configuration of the microprocessor is
It can be modified in various ways.

Furthermore, the system configuration that performs various process controls is generally composed of several chips of digital semiconductor integrated circuits, such as a microprocessor, ROM (or RAM) in which control programs are written, and RAM for holding various data. For this reason, the analog/digital input/output circuit including the A/D conversion circuit is provided, for example, in a digital semiconductor integrated circuit 19 constituting a ROM in which a control program is written, as shown in FIG. It's okay. That is, a digital semiconductor integrated circuit 19 composed of an address decoder circuit 20 and a memory array 21 in which program command words are written has an input/output port 12 similar to that described above,
A register 15, a multiplexer 13, an A/D conversion circuit 14, and registers 16 and 17 are provided, and the data bus and address bus of this digital semiconductor integrated circuit 19 are connected to the microprocessor via an external data bus and address bus. By doing so, similar operations can be performed.

Further, in a digital control system including a RAM, the analog/digital input/output circuit including the A/D conversion circuit may be provided in a digital semiconductor integrated circuit constituting the RAM, and may be provided in a microprocessor, ROM, The same applies when the entire RAM system is constructed from a single-chip digital semiconductor integrated circuit.

[Brief explanation of drawings]

1 and 3 are block diagrams showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an embodiment of the main part of the invention. DESCRIPTION OF SYMBOLS 1... Microprocessor, 2... Accumulator, 3... Accumulator latch, 4... Temporary register, 5... Arithmetic logic unit, 6... Instruction register, 7... Instruction decoder and machine cycle encoder, 8 ...Timing control circuit, 9...
...Register section, 10...Address buffer, 11
...Data buffer, 12...Input/output port, 1
2a...Input buffer amplifier, 12b...Output buffer amplifier, 13...Multiplexer, 14...
...A/D conversion circuit, 15...Register, 15a~
15c...Latch circuit, 16...Register, 17
...Control register, 17a...Latch circuit, 17b...Decoder circuit, 18...Address decoder circuit, 19...ROM, 20...Address decoder, 21...Memory array.

Claims (1)

[Claims] 1. A controlled device whose operation is controlled based on a digital control signal and outputs a digital signal and an analog signal depending on the operating state, and a controlled device that receives the digital signal and analog signal from the controlled device. A digital control system comprising a control circuit device that outputs the digital control signal, the control circuit device including a digital circuit, an analog-to-digital conversion circuit, a digital input terminal, and an analog input terminal, and at least one of the digital input terminals. A digital control system comprising a monolithic semiconductor integrated circuit that shares at least a portion of an analog input terminal and selectively uses the shared terminal as a digital input terminal or an analog input terminal. .