JP3186150B2 - Data transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer method using a plurality of central processing units (hereinafter referred to as "CPU"), and more particularly to a method for transferring data in a memory area of a CPU to a memory of another CPU. The present invention relates to a data transfer method for transferring data to a certain part in an area.

[0002]

2. Description of the Related Art Conventionally, as disclosed in Japanese Patent Application Laid-Open No. 2-153248, in an electronic control unit for an internal combustion engine, data of a multibyte length is transferred at once between a plurality of CPUs or between a CPU and a memory. A direct memory access channel means (hereinafter referred to as "DMA") for directly writing to a receiving memory without using a program is disclosed.

[0003]

However, in the data transfer method, since data is transferred without depending on the program of the CPU, the data is transferred from the transmission side memory to the reception side memory. During reading, the CPU may read data stored in the memory (reception side memory). That is, for example, of the data whose entire data is N bytes, up to the first n bytes are data updated by the transfer of the current data, and
-For data for which n bytes have not yet been updated, there is a problem that the CPU reads this data as one piece of data.

Therefore, in order to solve such a problem, data indicating the start and end of DMA transfer is written into addresses before and after the data to be transferred, and the CPU reads the data. A method has been proposed in which a CPU does not read data stored in a memory while data transfer by DMA is being executed.

However, in the case where a large amount of data is transferred at a time using the DMA, the above-described method requires a CPU during the period when the data transfer by the DMA is being executed.
Cannot read the data stored in the memory at all, which causes a problem that the arithmetic processing in the CPU is kept waiting for a long time. SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and an object of the present invention is to provide a multi-byte data using a DMA without waiting for a long time in a CPU. The point is to ensure the transfer.

[0006]

Means for Solving the Problems A data transfer apparatus according to the present invention for achieving the above object, a data transfer instrumentation for transferring data between a plurality of central processing unit having a memory
In location, among all the data to be transferred, the receiving side the
Data length that can be written to the central processing unit memory at one time
Before and after the first data exceeding the threshold, identification data indicating the start and end of the data is set, and the central processing on the receiving side is set.
The central processing unit on the receiving side.
Whether the first data is being written to the memory
Is determined based on the identification data, and the first data
If it is determined that the data is being written,
Reading the first data being written to the memory
Characterized in that it prohibited.

[0007]

When data is transferred between a plurality of CPUs having a memory , data having a byte length exceeding the byte length that can be written to the receiving memory at one time out of all the transfer data is set to the beginning of the data. At the end, write the identification data indicating the beginning and end of the transfer data. Thereby, it is determined whether or not one piece of data is data including a non-updated part in the middle of rewriting, reading of data including a non-updated part in the middle of rewriting is prohibited, and only the data of the end of the update is read. Forward.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. An embodiment in which the present invention is applied to an electronic control unit for an internal combustion engine will be described below. As shown in FIG. 2, a first CPU 1 that controls fuel supply to the internal combustion engine and a second CPU 2 that controls ignition timing of an air-fuel mixture supplied to the combustion chamber include an electronic control unit (ECU) 3. It is provided in.

The first CPU 1 includes the first CPU 1
A read-only memory (hereinafter referred to as RO) for storing various arithmetic programs executed by the ECU and a fuel injection amount (various tables used for calculating the valve opening time of the fuel injection valve) and the like.
M) 4 and a random access memory (hereinafter, referred to as RAM) 5 for temporarily storing the operation result.

The second CPU 2 is provided with a ROM 6 and a RAM 7 having the same functions as the ROM 4 and the RAM 5 built in the first CPU 1. A first cylinder discrimination signal that outputs a first cylinder discrimination signal (G1) at a predetermined angular position before a top dead center of a compression process of a specific cylinder every time the camshaft of the internal combustion engine rotates 360 ° on the input side of the ECU 3. Sensor 1
0 and 3 with respect to the crankshaft for the cylinder discrimination signal.
A second cylinder discrimination sensor 11 that outputs a second cylinder discrimination signal (G2) at a position shifted by 60 ° (360 ° CA), and outputs a one-pulse signal (NE) every time the crankshaft rotates 30 °. Rotation sensor 12 is connected.
The first cylinder discrimination signal (G1) and the second cylinder discrimination signal (G
2) and the rotation speed signal (NE), as shown in FIG.
After being input to the waveform shaping circuit 15 inside the ECU 3, it is input to the first CPU 1 and the second CPU 2.

As other inputs to the ECU 3, an idle switch 16 for outputting a signal (IDL) indicating that the throttle valve is fully closed, and a signal (NSW) indicating that the shift position of the automatic transmission is neutral. And a starter switch 18 that outputs a signal (STA) indicating that the starter is energized are connected, and the levels are exchanged through an input circuit 20 inside the ECU 3 to exchange the level with the first CPU 1. Second
Are input to both CPU2.

Further, as inputs to the ECU 3, an air flow meter 22 for converting the intake air amount of the internal combustion engine into a voltage and outputting the voltage, a water temperature sensor 23 for outputting the cooling water temperature of the internal combustion engine as a resistance value, and a resistance value for the intake air temperature of the internal combustion engine , A throttle sensor 25 that outputs the throttle opening as a resistance value, and a battery 26 for monitoring the power supply voltage.

Among these inputs, a water temperature signal, an intake air temperature signal, and a battery signal are input to the first AD converter 27, and the data is transferred only to the first CPU 1.
A first A / D converter 27 and a second A / D converter 28 provide an intake air amount signal (AFM) and a throttle opening signal.
To the first CPU 1 from the first AD converter 27.
The data is transferred from the second AD converter 28 to the second CPU 2.

As a communication means between the first CPU 1 and the second CPU 2, the CPU 1 and the CPU 2 are connected by the following five lines. That is, from CPU1 to CPU2
SOUT for outputting data to CPU 2
SIN for transmitting data to PU1, CLK for transmitting a synchronization signal for synchronizing data from CPU1 to CPU2, CTS for transmitting a signal indicating that CPU2 is in a receivable state, receivable state for CPU1 Are lines of the RTS for sending a signal indicating that

When the first CPU 1 is in a state in which data can be transmitted by a program and the second CPU 2 is notified by the CTS to the first CPU 1 that the second CPU 2 can receive data, the first CPU 1 outputs The contents of the memory starting from a predetermined RAM address in the first CPU 1 are stored in the SOU by a predetermined data length.
Through T, it is output in synchronization with CLK. 2nd C
PU2 converts this data into a predetermined second
Is written to the RAM area in the CPU 2.

Here, the output from the RAM to the SOUT in the first CPU 1 and the RA in the second CPU 2
Writing to M is performed by hardware by a DMA controller provided in each CPU without intervention of a program in each CPU. From the second CPU 2 to the first CPU
Data transfer from the first CPU 1 to the second CPU
This is performed by the same means as in the case of 2.

FIGS. 3 and 4 show flowcharts of processing on the transmitting side and processing on the receiving side. FIG. 5 shows the state of the transfer area in the memory. Now, it is assumed that the byte length at which data can be written to a predetermined RAM address at a time on the receiving side of the DMA is 2 bytes, and the byte length of the data D which requires an accuracy exceeding that is 3 (= n) bytes. in this case,
The data D 'is composed of upper one byte (d1') and lower two bytes (d2 ', d3') or upper two bytes (d1 ').
', D2') and the lower one byte (d3 ') when read with a shift in write timing, there is a possibility that a value different from true data may be obtained. Therefore, in this embodiment, the DMA
As described above, data indicating that data is being written only before and after data (data D ') requiring an accuracy exceeding the byte length that can be written at a time among the data transferred as described above. C1 'and data C2' are provided. As a result, data different from the true data due to the shift of the data write timing as described above is transmitted to the CPU.
1. It is possible to prevent the CPU 2 from reading. On the other hand, unlike the above-mentioned data, high-precision data is not required. In the case of data that can be written at once, such a problem does not occur, so that data indicating that writing is in progress. No data is provided. Due to this , during this time the CPU
1 and the CPU 2 can freely read the data in each RAM, and the time required for the arithmetic processing can be greatly reduced. Here, data requiring an accuracy exceeding the byte length that can be written at one time is, for example, data indicating a detection result of an intake air amount and a throttle opening, and the like.
The required precision (byte length) of these data is determined in advance.

Next, processing on the transmitting side and processing on the receiving side when transferring the data D 'as described above will be described. In the processing on the transmission side, as shown in FIG. 3, always C ₁
← 0 (= K ₁ ), C ₂ ← 0 (= K ₂ ) (step 100). However, K ₁ and K ₂ are arbitrary constants. Here, if the transfer is performed, the C
A _{1 '= 0, C 2'} = 0. In the processing on the receiving side, FIG.
As shown in step 240, at step 240, C ₁ ′ ← 1 (= K
₁ ′) and C ₂ ′ ← 1 (= K ₂ ′).
_{1 ', d 1' d 2} ', d 3', C 2 ' when is not performed forwarding to _{the, C 1' ≠ 0 (=} K 1), C 2 '≠ 0
(= K ₂ ). K ₁ ′ and K ₂ ′ are K ₁ ′ ≠ K ₁ ,
K ₂ ′ ≠ K _{2 is} an arbitrary constant.

When using the data D 'on the receiving side, first read d ₁ ', d ₂ ', d ₃ ' (step 2).
00), C ₁ ′ is compared with 0 (= K ₁ ) (step 2)
10). Here, if it is determined that C ₁ ′ ≠ 0 (= K ₁ ) (step 210), since writing to d ₁ ′ to d ₃ ′ has not yet been performed, D ′ read at this time is used as it is. May be. If it is determined that C ₁ ′ = 0 (= K ₁ ) (step 210), since writing to d ₁ ′ to d ₃ ′ has already started, next, C ₂ ′ and 0 (= K 1)
₂ ) (step 220), and C ₂ ′ ≠ 0 (= K
_{If 2} ) is determined, writing is still in progress and C ₂ ′
Wait until = 0 (= K ₂ ). C ₂ '= 0 (= K ₂ )
If it is determined that, since the completion of writing to d ₁ '~d _3', then to load the d ₁ '~d _3' (step 230), and use that value. Further, C
₁ ', C _{2' For, C 1 '← 1 (≠} K 1'), C
₂ ′ ← 1 (≠ K ₂ ′) (step 240).
This is to enable the above processing when reading d ₁ ′, d ₂ ′ and d ₃ ′ next time.

In the above embodiment, the data C₁ , C_Two The day
RAM was at a different address from that of D₁ , C
_Two Is sufficient for each one bit.
₁ , C _Two As 1-bit data, d₁ , D_Three 
Can be part of In the case of the above embodiment,
Specifically, the CPU 1 outputs the fuel of each cylinder of the internal combustion engine.
# 1, # 2, # 3 for controlling the fuel injection valve 30
# 4 and other VS for controlling the state of the internal combustion engine
A signal for controlling V31 is output. 2nd C
PU2 ignites the ignition plug 32 of each cylinder of the internal combustion engine
An ignition signal is output for the
To control the VSV 34 and the like
A signal is output.

In the above embodiment, two CPUs are used. However, the present invention can be applied to the case where three or more CPUs are used. In this case, the signals input to the plurality of CPUs do not need to be input to all the CPUs being used, and the signals may be input only to some of the CPUs that need the input.

[0022]

As described above, according to the data transfer method of the present invention, when data is transferred between a plurality of CPUs or between a CPU and a memory, arithmetic processing in the CPU does not have to wait for a long time. There is an effect that data over a multibyte length can be reliably transferred by using DMA.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a data transfer method according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a data transfer method according to an embodiment of the present invention.

FIG. 3 is a flowchart illustrating processing on a transmission side according to an embodiment of the present invention.

FIG. 4 is a flowchart illustrating processing on the receiving side according to the embodiment of the present invention.

FIG. 5 is a diagram illustrating a data transfer method according to an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st CPU (central processing unit) 2 2nd CPU (central processing unit) 4 ROM (memory) 5 RAM (memory) 6 ROM (memory) 7 RAM (memory) 40 Communication means

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 12 / 00,13 / 16 G06F 13 / 28,15 / 16

Claims (1)

(57) [Claims] In a data transfer apparatus for transferring data between a plurality of central processing units having a memory, the central processing unit on the receiving side of all data transferred.
The first that exceeds the data length that can be written to the memory of the device at one time
Identification data indicating the beginning and end of data before and after the data
And the central processing unit on the receiving side is provided in front of the receiving side.
The first data is written in the memory of the central processing unit.
It is determined whether or not data is being written based on the identification data.
And it is determined that the first data is being written.
If it is determined, the data is being written to the memory
Data transfer device for inhibiting reading of the first data
Place.