JP2518336B2 - Serial communication controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention relates to a serial communication control device, and more particularly to a serial communication control device that operates by being connected to a bus connecting a central processing unit and storage means at any time. Regarding

[Prior Art] In recent years, with the rapid development and popularization of electronic technology, and in particular with the downsizing and price reduction of processing devices such as microcomputers, etc., processing is concentrated on large-scale and high-performance central processing units. In place of the centralized system, research, development, and use of a distributed system in which a plurality of processing devices are prepared according to functions and arrangements of control targets and necessary processing is distributed are underway. Such a distributed system can perform local processing at high speed, variety that can configure an optimal control system for differences in controlled objects, reliability that some failures do not spread to the entire system, Although it is extremely excellent in terms of flexibility with respect to addition / change of, it requires a communication system for connecting a plurality of processing devices and a communication control device for processing mutual communication.

Therefore, various communication control devices for controlling the communication between the processing devices have been conventionally proposed, one of which is a serial communication control device for performing the communication between the processing devices by serial communication (1-bit communication). .

However, in general, such a serial communication controller is a central processing unit (CP) that constitutes a microcomputer.
U) controls the sending and receiving of data, which puts an excessive burden on the software (user program) prepared by the user. As a result, multiple central processing units are connected by serial communication and data is shared with each other. However, when a distributed control system such as the one described above is configured, there is a problem that the control responsiveness to the control target by the central processing unit decreases.

Therefore, for example, the present applicant avoids problems such as an excessive burden on the user program, which is a general drawback of such a serial communication control device, an increase in overhead, and a decrease in responsiveness of the main control accompanying this. For this reason, a serial communication control device has been proposed that sends and receives data separately from the user program (Japanese Patent Laid-Open No. 62-274851
issue).

[Problems to be Solved by the Invention] The serial communication control device is connected to a bus that mediates the exchange of data between the central processing unit and a storage means (RAM) that can read and write data at any time. , Occupy the output register for storing the transmission data to be transmitted to the outside, the input register for storing the reception data received from the outside, and the bus at the time of communication execution,
Communication control means for executing data transfer between the RAM and each of the above registers.

In such a serial communication control device, most communication operations are realized by the communication control means,
There is an excellent thing that the high-speed communication can be realized without reducing the load of the user program and spoiling the responsiveness of the main control, but at least when the bus is occupied by the communication control means (that is, RAM and output register and During the data transfer with the input register), the central processing unit cannot execute the arithmetic processing for the main control and the like, so that further improvement has been desired.

Therefore, the present invention can extremely effectively reduce an excessive load of a user program and a decrease in responsiveness of main control, and provide a serial communication control device suitable for configuring a distributed control system. Has an aim.

Configuration of the Invention The configuration of the present invention that achieves the above object will be described below.

[Means for Solving the Problems] A serial communication control device of the present invention is connected to a bus that mediates the exchange of addresses and data with respect to an occasional storage device capable of reading and writing data at any time by a central processing unit, and other communication. A serial communication control device for transmitting and receiving data to and from a control device, the transmission data storage means for storing a plurality of data to be transmitted, and a transmission request for detecting a data transmission request from the other communication control device. Detection means, data transmission means for transmitting the data stored in the transmission data storage means one by one each time the transmission request is detected by the transmission request detection means, and the transmission request detection means for transmitting the data. If no data is stored in the transmission data storage means when the request is detected, the bus is occupied and the data is stored in the storage means at any time. A plurality of data to be transmitted are read out, the data are stored in the transmission data storage means, the transmission data preparation means for operating the data transmission means, and the data reception capability for the other communication control device. Receivable notification means for notifying, reception data accumulating means for accumulating a plurality of units of data transmitted from the other communication control device in response to the receivable notification by the receivable notification means, and the received data Reception data transfer means for occupying the bus and transferring the data in the reception data storage means to the storage means at any time when the storage means stores the plurality of data. To do.

[Operation] The serial communication control device of the present invention having the above configuration is
Although data is transmitted / received to / from other communication control devices, the following actions are performed when transmitting / receiving data.

[I] During data transmission When a data transmission request is output from another external communication control device, the request signal is detected by the transmission request detecting means. Then, each time the transmission request is detected by the transmission request detecting means, the data transmitting means transmits the data stored in the transmission data storing means for storing a plurality of data to be transmitted one by one. But
If no data is stored in the transmission data storage means when the transmission request is detected, the transmission data preparation means occupies the bus connecting the central processing unit and the storage means at any time and should be transmitted from the storage means at any time. Read multiple data,
By storing the plurality of data in the transmission data storage means,
Activate the data transmission means.

Therefore, when a data transmission request is first output from another communication control device, first, the bus is occupied by the transmission data preparation means, and a plurality of data to be transmitted from the storage means to the transmission data storage means is stored. As they are transferred
One of the data is transmitted by the data transmitting means. Then, thereafter, each time a data transmission request is output from another communication control device, the data transmission unit transmits the data already stored in the transmission data storage unit one by one, and the data is stored in the transmission data storage unit. When the data transmission request is output from another communication control device after the data is empty, the transmission data preparation means is activated again and a plurality of data is transferred from the storage means to the transmission data storage means at any time. At the same time, one of the data is transmitted by the data transmitting means.

As described above, in the serial communication control device of the present invention, at the time of data transmission, each time a data transmission request is output from another communication control device, the data is transmitted one by one and the data is stored in the transmission data storage means. The bus is occupied only at a rate of once per the number of transmissions according to the number of data that can be stored, and the data to be transmitted is transferred from the storage means to the transmission data storage means at any time.

[II] At the time of receiving data When the receivability notification means notifies the other communication control device that the data can be received, another communication is performed in response to the receivability notification by the receivability notification means. Data is transmitted from the controller. Therefore, the reception data storage means stores the data from another communication control device in a unit of a plurality of units, and when the reception data storage unit stores the plurality of data, the reception data transfer unit,
Occupying a bus connecting the central processing unit and the storage means at any time,
The data in the received data storage means is transferred to the storage means at any time.

As described above, in the serial communication control device of the present invention, at the time of receiving data, the data transmitted from another communication control device is accumulated in the reception data accumulating means in a plurality of units, and every time a plurality of data is accumulated. Whenever a plurality of data is received, the bus is occupied and the received data is transferred from the received data storage means to the storage means at any time.

As described above, in the serial communication control device of the present invention, at the time of data transmission, each time a data transmission request is received from another communication control device, the data is transmitted one by one, and the data is transmitted at a plurality of times. Occupy the bus only at the rate of times, transfer the data to be transmitted from the storage means to the transmission data storage means at any time, and when receiving the data,
Each time a plurality of data transmitted from another communication control device are received, the bus is occupied and the received data is transferred from the received data storage means to the storage means at any time.

Therefore, according to the serial communication control device of the present invention, when communicating with another communication control device, the central processing unit does not burden the user program to be executed and occupies the bus. The period (that is, the data transfer period between the storage unit, the transmission data storage unit, and the reception data storage unit) can be made extremely small, so that the central processing unit cannot execute arithmetic processing for main control. Can be extremely small. Therefore,
It is possible to extremely effectively reduce the deterioration of the response of the main control by the central processing unit.

Furthermore, according to the serial communication control device of the present invention, when receiving data, the data transmitted from another communication control device in response to the receivable notification is sequentially received. At the time of transmission, the plurality of data stored in the transmission data storage means are not simply transmitted in sequence but are transmitted one by one each time a transmission request is received from another communication control device. Therefore, the other communication control device that is a communication partner can send and receive data at any timing, and the processing load on the other communication control device can be reduced.

That is, when a configuration is adopted in which, when a data transmission request is received from another communication control device, the bus is occupied and a plurality of data to be transmitted is transferred from the storage means to the transmission data storage means at any time. Would simply send its data in sequence. However, with this configuration, the other communication control device that is a communication partner must continuously receive a plurality of data, and, for example, the other communication control device is controlled by the central processing unit (CPU). If the data transmission / reception is controlled, the central processing unit on the side of the other communication control device cannot sufficiently execute the original control process for controlling the predetermined control target.

On the other hand, according to the serial communication control device of the present invention, the data is transmitted one by one each time a data transmission request is received from another communication control device, and therefore it is a communication partner. The other communication control device can surely receive the data one by one by outputting the transmission request at an arbitrary timing that is convenient for itself (for example, a timing at which the original control processing need not be performed). As a result, the execution of the process for controlling the controlled object is not hindered.

As described above, according to the serial communication control device of the present invention, the central processing unit including the serial communication control device and the central processing unit on the other communication control device side share data to control the control target, When such a distributed control system is configured, not only the central processing unit having the serial communication control device, but also the processing load on the central processing units of other communication control devices can be reduced. As a result, it becomes possible to construct a distributed control system with extremely excellent control response.

The bus of the central processing unit may be occupied by a method such as cycle stealing or a method of direct memory access (DMA) by bus request control.

[Embodiment] In order to further clarify the configuration and operation of the present invention described above, a preferred embodiment of the serial communication control device of the present invention will be described below. FIG. 1 shows an internal configuration of a serial communication control device 3 as an embodiment incorporated in an electronic control device (hereinafter referred to as an engine ECU) 1 for controlling an internal combustion engine, and a general-purpose communication control connected thereto. FIG. 3 is a block diagram shown together with a transmission electronic control unit (hereinafter referred to as a transmission ECU) 5 having a function.

As shown in the figure, the serial communication control device 3 is an engine.
Connected to the internal bus 10 of the ECU1, CPU11 as a well-known central processing unit connected to the internal bus 10, ROM12, RAM14 as storage means at any time, a pulse input port 16 for inputting a pulse signal from the outside, An engine ECU 1 is configured with an A / D conversion input port 17 for converting an analog signal into a digital signal and inputting the output signal, an output port 19 for outputting a drive signal to an external actuator, and the like.

Inside the serial communication control device 3, a DMA controller 2 that occupies the internal bus 10 and controls data exchange
0, DMA input address register 22 and DMA output address register 23 for holding data input / output address by DMA controller 20, DMA input data counter 24 and DMA for counting the number of data input / output by DMA transfer
The output data counter 25 and DMA buffer registers 28 and 29 for temporarily holding data input / output to / from the transmission ECU 5 are provided so as to be connected to the internal bus 10. In addition, the serial communication control device 3 has a DMA
Signals RQ for serial communication directly connected to the controller 20
Serial communication controller 31 that handles T or RQR via buffers 30a and 30b, reception S / P conversion register 33 that inputs serial signal SIN that is data via buffer 30c and converts it to parallel data, output of this register 33 , A transmission data register 36 for storing transmission data, a transmission P / S conversion register 37 for converting the data in the register 36 into a serial signal and outputting the serial signal via the buffer 30d, and serial communication. A clock circuit 39 and the like for generating a clock for use is provided. The DMA controller 20 is connected to the above-mentioned CPU 11, RAM 14 or their counters or registers 24, 25, 33, 34, 36, 37, and direct memory access from the DMA input data counter 24 and the DMA output data counter 25. , Which signals that the data transfer by
From the reception data register 34 and the transmission data register 36, a signal notifying that communication data has been set is input, and further, from the clock circuit 39, a conversion clock signal is input. This clock signal is sent to the receiving S / P conversion register 33 and the transmitting P / S conversion register.
It is also entered in 37. Also, DMA controller 20 to C
PU11 receives a stop request signal signal that requests CPU11 to stop and occupy the internal bus.
A read / write signal R / for controlling whether reading or writing is output.

The transmission ECU 5 connected to the serial communication control device 3 of the engine ECU 1 via four signal lines,
It has a general-purpose serial communication function. As shown in FIG. 1, a well-known CPU 51, ROM 52, RAM 54, input port 56, output port 59, etc., which are mutually connected via an internal bus 50, are provided inside thereof. Further, in order to realize general-purpose serial communication, a serial signal SIN that is data is input via a buffer 60c and converted into parallel data, a reception S / P conversion register 63, reception data that holds the output of this register 63. Register 64, reception S / P conversion register 63
A reception controller 65 that controls the transmission data, a transmission data register 66 that holds transmission data, a transmission P / S conversion register 67 that converts the data in this register 66 into a serial signal and outputs it via the buffer 60d, and a transmission P / S conversion register 67
A transmission controller 68 and the like for controlling the are provided. The transmission controller 68 is configured so that the signal RQR from the serial communication controller 31 of the engine ECU 1 is input via the buffer 60a. Also, from the output port 59,
The signal RQT is output to the serial communication controller 31 via the buffer 60b.

Engine ECU1 and transmission ECU5 described above
Is connected to various sensors and actuators provided in the internal combustion engine 71 and the automatic transmission 75. These relationships will be briefly described below with reference to FIG. 2 which is a schematic configuration diagram of the internal combustion engine 71 and the automatic transmission 75.

(A) Internal combustion engine 71 and engine ECU1 The following sensors provided in the internal combustion engine 71, that is, an air flow meter 76 that detects the amount of intake air, an intake air temperature sensor 77 that detects the temperature of intake air, and the opening of the throttle valve 78 Etc., a throttle sensor 79 for detecting the like, an oxygen concentration sensor 80 for detecting the oxygen concentration contained in the exhaust gas after combustion, an exhaust temperature sensor 81 for detecting the exhaust temperature, a cooling water temperature sensor 82 for detecting the cooling water temperature of the internal combustion engine 71, etc. Is connected to the A / D conversion input port 17 of the engine ECU 1 and is provided in the distributor 83 to detect the rotation speed of the internal combustion engine 1.
The 4, cylinder discrimination sensor 85 and the like are connected to the pulse input port 16. On the other hand, the fuel injection valve 8 provided in the internal combustion engine 71
6, actuators such as the idle speed control valve 87 that adjusts the idle air amount, the igniter 89 that generates the high voltage supplied to the spark plug 88, and the engine ECU1
Connected to the output port 19 of.

Therefore, the engine ECU 1 can execute fuel injection control, ignition timing control, idle speed control, etc. based on the operating state of the internal combustion engine 71 by inputting signals from these sensor groups. Also,
By the serial communication described later, transmission EC
It is possible to transmit data such as the throttle opening degree to U5 or receive data such as the gear shift state of the automatic transmission 75.

(B) Automatic transmission 75 and transmission ECU5 Automatic transmission 75 connected to the crankshaft 90 of the internal combustion engine 71
Is provided with a vehicle speed sensor 93 that detects a vehicle speed V based on the number of revolutions of the output shaft 91 and a shift position sensor 95 that detects a shift position of the automatic transmission 75, and the gear ratio of the automatic transmission 75 is 1 It is connected to the input port 56 of the transmission ECU 5 together with the overdrive cut switch 96a for prohibiting the selection of so-called overdrive which is less than the above and the pattern select switch 96b for selecting the shift pattern. On the other hand, the two shift solenoid valves 97, 98 and the lock-up solenoid valve 99 for shifting (upshift, downshift) provided in the automatic transmission 75 are connected to the output port 59 of the transmission ECU 5. There is.

Therefore, the transmission ECU 5 can execute the control of the gear ratio of the automatic transmission 75 by inputting the signals from these sensor groups. Further, the transmission ECU 5 can transmit data such as the current gear ratio and vehicle speed to the engine ECU 1 or receive data such as the throttle opening degree from the engine ECU 1 by serial communication described later.

Next, serial communication performed between the engine ECU 1 and the transmission ECU 5 will be described. The structure of data used in serial communication is, as shown in FIG. 3, a general-purpose one including a start bit 1, a data bit 8, a parity bit 1 and a stop bit 1, and distinguishes between an address and data or a command and data. It does not include other additional information.

Recently, control when data is transmitted from the engine ECU 1 side will be described. Prior to the data transmission, the CPU 1 of the engine ECU 1 executes the output process shown in FIG.
First, the value of the output completion flag that is set to value 1 is checked when all the data to be transmitted in one transmission process has been transmitted (step 100). Assuming that has started, this routine is finished as it is. On the other hand, if the output completion flag is set, the value 1 is set in the output permission flag (step 110). Here, the output permission flag is for masking the data transmission until the serial communication control device 3 is powered on and the initialization process is completed, and a DMA data transmission process routine described later. , It is used to prohibit the transmission of data until the output completion flag is set to the value 1 for the first time.

Subsequently, the DMA output address register 23 is set (step 120) and the DMA output data counter 25 is set (step 120).
130) and These processes are to set the start address of the RAM 14 in which the data to be transmitted is stored and the number of words to be transferred from that address. After performing the above processing,
In order to start data transmission, the output completion flag is reset (set to value 0) (step 140), and this routine ends.

By executing the processing of steps 110 to 140 described above, the serial communication control device 3 becomes in a state in which it can transmit data, and by receiving the data transmission request signal RQT from the transmission ECU 5, Start sending. Therefore, the processing performed to receive data transmission inside the transmission ECU 5 will be described first with reference to FIG.

This data reception processing routine is repeatedly executed by the CUP 51 together with other control routines for controlling the automatic transmission 7. First, it is judged whether or not the input completion flag is set to the value 1 (step 200), and when the input of one time is completed and the value of this flag is 1, the input address Is set (step 202), the input data counter is set (step 204), and the input completion flag is reset (step 206), and the process proceeds to the next step 210. Here, the input address means the start address of the RAM 54 that stores the data to be received in the next communication control, the input data counter means the number of data to be received, and the latter is also used for checking errors in communication. To be

In step 210 and subsequent steps, a process of outputting a data transmission request signal to the serial communication control device 3 of the engine ECU 1 is performed. That is, one output P00 of the output port 59 is held at the low level for a certain period of time (steps 210, 212, 21).
Four). This state is shown by timing ti (i = 1, 2 ...) In the timing chart of FIG. Then, it is judged whether the reception data register (RDR) 64 is empty (step 22).
0), and waits until data is transmitted from the serial communication control device 3 and set in the register 64.

When data is set in the receive data register 64,
In step 230 and thereafter, the process of storing data in the RAM 54 is performed. That is, the contents of the reception data register 64 are read (step 230), this data is stored in the input address set in step 202 (step 232), the input address is incremented by 1 (step 234), and further the input data counter The value is decremented by 1 (step 236).

Then, it is judged whether or not the input data counter has reached 0 (step 240), and "NEXT" is kept until the number of data set in advance in step 204 is received.
To end the present routine once. On the other hand, if the set number of data is input, the value of the counter becomes 0. In this case, therefore, the value 1 is set in the input completion flag (step 250), and this routine ends.

Next, the DMA controller 20 of the serial communication control device 3
The processing in will be described. The DMA controller 20 also has a processor for sequentially executing arithmetic and logic operations therein, and after executing initialization processing after power-on, executes the DMA data transmission processing routine shown in FIG. When this routine is started, it is first determined whether or not the output permission flag has a value of 1 (step 300). The value is 0 until the output permission flag is set by the output processing by the CPU 11 described above (step 110). Therefore, when this routine is executed for the first time, the determination is “NO”, the output completion flag is set to the value 1 (step 305), and the DMA output data counter 25 is set to the value 0 (step 310). Furthermore, the contents of the DMA buffer register 29 and the transmission data register (TDR) 36 are cleared (step 3
Perform processing such as 15).

When the output permission flag is set (= 1) by the output processing by the CPU 11 shown in FIG. 4, it is next judged whether or not the output completion flag is set (step 32).
0), the value of this flag is 1 when all data transmission is completed.
If it is set to, the process returns to step 300 and waits until the CPU 11 instructs the transmission of the next data.

After the output completion flag is set to the value 0 in step 140 shown in FIG. 4, the process proceeds from step 320 to step 325, and whether or not the DMA output data counter 25 is 0, that is, all It is determined whether or not the data transmission is completed. Since the DMA output data counter 25 is not 0 during the data transmission, the transmission EC is continuously transmitted via the serial communication controller 31.
It is determined whether or not an edge in which the data transmission request signal RQT from U5 falls to low level is detected (step 330). The data transmission request signal RQT, as described above (timing t1 in FIG. 6), is transmitted by the transmission EC.
It is output when U5 requests transmission of data.

When the falling edge of the data transmission request signal RQT is detected, the DMA controller 20 determines whether or not it is the timing to transfer the second byte in the communication performed in word units (step 335). The determination of this timing is performed by detecting whether or not the second byte data is stored in the transmission data register (TDR) 36 by the process of step 375 described later, and if the data is stored, It is determined that it is time to transfer the second byte. First, when transmitting the first byte, a signal requesting interruption of the execution is output to the CPU 11 (step 340). Upon receiving the signal, the CPU 11 finishes the instruction currently being executed, and then
Release internal bus 10 and stop. Therefore, it is detected that the instruction being executed by the CPU 11 is completed (step 345), and the DMA controller 20 uses the released internal bus 10 to execute the following processing.

That is, the value of the DMA output address register 23 is incremented by 1 (step 350), and the data of the address of the RAM 14 pointed to by this register 23 (first byte of word)
Is first loaded into the DMA buffer register 29 (step 355). Next, the data in the buffer register 29 is loaded into the transmission P / S conversion register (TSR) 37 via the transmission data register (TDR) 36 (step 360). As a result, the first byte of the word data is output from the buffer 30d to the transmission ECU 5 via the transmission signal line SOUT. Then, set the value of DMA output address register 23 to 1
By incrementing only (step 365), the data of the address, that is, the second byte of the word data is transferred to the DMA buffer register 29 (step 370), and the data is further stored in the transmission data register (TDR) 36 (step). 375). After the preparation for the transmission of the second byte data is completed in this way, the stop request signal to the CPU 11 is released in step 380 (see FIG. 6). The process is repeated from step 300.

Next, a data transmission request signal from the transmission ECU 5
When RQT is input (timing t2 in FIG. 6), it is assumed that the second byte of word data is transmitted (steps 330 and 335), and the data corresponding to the second byte already stored in the transmission data register (TDR) 36 is transmitted. , Transfer to the transmission P / S conversion register (TSR) 37 (step 3
85). As a result, the data corresponding to the second byte is converted into serial data and output to the transmission ECU 5. After that, set the value of DMA output data counter 25 to 1
However, it is decremented (step 390), and the processing from step 300 is repeated assuming that the transmission of the data for one word is completed.

In this way, data is sequentially transmitted in units of words, and when the number of words set in the DMA output data counter 25 is transmitted in advance, the determination in step 325 is “YES”, so that all data is transmitted. Assuming that the data has been transmitted, the value 1 is set in the output completion flag (step 39
5) Then, the process is repeated from step 300.

In the present embodiment, the DMA buffer register 29 and the transmission data register 36 correspond to the transmission data storage means, the process of step 330 corresponds to the transmission request detection means,
The processing of steps 360 and 385 corresponds to data transmission means,
The processes of steps 335 to 355 and 365 to 380 correspond to the transmission data preparation means.

As described above, in the serial communication control device 3 of the present embodiment, as shown in FIG. 6, every time the data transmission request signal RQT from the truss mission ECU 5 falls twice, the processing execution of the CPU 11 is stopped and the RAM 14 is executed. To DMA buffer register 29
Also, one word (2 bytes) of data is transferred to the transmission data register 36, and each time the data transmission request signal RQT falls, the data is transmitted one byte at a time. As a result, the CPU 11 is transferred to the DMA controller 20.
6 steps (see FIG. 7, about 2 in this embodiment)
"Μsec") It is possible to execute transmission in 1-word units simply by stopping.

Therefore, there is almost no communication control load in the user program executed by the CPU 11, and the transmission EC
Data can be output in response to a data transmission request from U5 at high speed.

Furthermore, in the serial communication control device 3 of the present embodiment, each time the data transmission request signal RQT falls, one byte of data is transmitted, so that the transmission ECU 5, which is the communication partner, can transmit at any timing. The serial data reception process can be executed. Therefore, also in the transmission ECU 5, the load of the program executed by the CPU 51 is reduced, and the data can be input at high speed. As a result, it is possible to construct a distributed control system having extremely excellent control responsiveness.

Next, a process of transmitting data from the transmission ECU 5 to the engine ECU 1 will be described. In this case, the CPU 11 of the engine ECU 1 executes the input process shown in FIG. First, the value of the input completion flag that is set to the value 1 is checked when all the data to be received in one reception process is received (step 400). If the value is not 1, the data reception process has already been performed. Assuming that has started, this routine is finished as it is. On the other hand, if the input completion flag is set, the value 1 is set in the input permission flag (step 410). Here, the input permission flag indicates that the serial communication control device 3 is powered on,
This is for masking data reception until the initialization process is completed. In the DMA data reception process routine described below, data reception is prohibited until the input completion flag is set to the value 1 for the first time. It is used to

Then, set the DMA input address register 22 (step 420) and the DMA input data counter 24 (step
430) and do. These processes set the start address of the RAM 14 in which the data to be received is stored and the number of words from the address to receive the data. After performing the above processing, the input completion flag is reset (value is set to 0) to start data reception (step 440), and this routine is ended.

By executing the processing of steps 410 to 440 described above, the serial communication control device 3 becomes in a state capable of receiving data from the transmission ECU 5. Therefore, the processing performed for the transmission of data inside the transmission ECU 5 will be described first with reference to FIG.

This data transmission processing routine is executed by the CPU 51 in addition to the data reception processing routine already described and the automatic transmission 75
Is repeatedly executed together with other control routines for controlling. First, it is judged whether or not the output completion flag is set to the value 1 (step 500), and when one output is completed and the value of this flag is 1, the output address is set. (Step 502), output data counter setting (step 504) and output completion flag resetting (step 506) are executed, and the next step 5
Go to 10. Here, the output address means the head address of the RAM 54 that stores the data to be transmitted in the next communication control, and the output data counter means the number of data to be transmitted.

In step 510 and subsequent steps, a process of checking the data reception signal RQR from the serial communication control device 3 of the engine ECU 1 is performed. That is, it is determined whether or not the data received by the transmission controller 68 is low level. The data reception signal RQR is controlled to a low level that allows the serial communication control device 3 to receive data in the DMA data reception process described later. This is shown in the timing chart of FIG. After that, it is judged whether or not the transmission data register (TDR) 66 is empty (step 520), and if it is not empty, it is determined that the 1-byte data transmission is already being executed, and the process is terminated. On the other hand, if the data register 66 is empty, the data of the output address that has already been set is read (step 525), the data is written to the transmission data register (TDR) 66 (step 530), and the transmission processing is performed. Is started (step 532). After that, the output address is incremented by 1 (step 534), and the value of the output data counter is decremented by 1 (step 536).

Subsequently, it is judged whether or not the output data counter has reached 0 (step 540), and “NEXT” is kept until the number of data set in advance in step 504 is transmitted.
To end the present routine once. On the other hand, if the set number of data is output, the counter value becomes 0. In that case, therefore, the value 1 is set in the output completion flag, and this routine is ended.

Next, the reception process in the DMA controller 20 will be described. When receiving data, the DMA controller 20 executes the initialization process and then the DM shown in FIG.
A Data reception processing routine is executed. When this routine is started, it is first determined whether the input permission flag is 1 (step 600). CPU 11 described above
The value is 0 until the input permission flag is set by the input processing (step 410). Therefore, when this routine is executed for the first time, the judgment is "NO".
And the input completion flag is set to the value 1 (step 60
5) Set the data reception signal RQR to high level via the serial communication controller 31, and set the DMA input data counter.
The value 0 is set in 24 (step 610), and the contents of the DMA buffer register 28 and the reception data register (RDR) 34 are cleared (step 615).

When the input permission flag is set by the input processing by the CPU 11 shown in FIG. 8 (= 1), the process proceeds to the judgment whether or not the input completion flag is set (step 620), and all the data is received. If completed and the value of this flag is set to 1, the process returns to step 600 and waits until the CPU 11 instructs the reception of the next data.

After the input completion flag is set to the value 0 in step 440 shown in FIG. 8, the process proceeds from step 320 to step 623, and the data reception signal RQR is set to the low level (= 0) via the serial communication controller 31. ). The data reception signal RQR is a signal indicating that the serial communication control device 3 is ready to receive data while it is held at the low level. As shown in FIG. 10, the data reception signal RQR remains at the low level until the reception is completed. Retained.
Next, it is judged whether or not the DMA input data counter 24 is 0, that is, whether or not the reception of all data is completed (step 625). Since the value of the DMA input data counter 24 is not 0 during the data reception, in this case, it is determined whether or not the data is input to the reception S / P conversion register (RSR) 33 (step 630). ).

If the data reception signal RQR is checked and if it is low level, the transmission ECU 5 transmits data at a predetermined timing according to the data transmission processing routine shown in FIG. The transmitted serial signal is buffered
The data is input to the reception S / P conversion register (RSR) 33 via 30c and converted into parallel data here.

When it is detected that data is input to the reception S / P conversion register (RSR) 33, the DMA controller 20 determines whether or not it is the timing to receive the second byte in the communication performed in word units ( Step 635). First,
When receiving the first byte, this register (RS
R) 33 data is transferred to the receive data register (RDR) 34 (step 636), and the data DMA buffer register
After saving in 28 (step 637), the process returns to step 600 to repeat the above-mentioned processing again.

Next, when data is transmitted from the transmission ECU 5, it corresponds to the second byte of the data in word units, so the determination in step 635 becomes “YES”, and the reception S /
The input data taken into the P conversion register 33 is transferred to the reception data register 34 (step 639). As a result, the data of the first byte is stored in the DMA buffer register 28,
The second byte of data is the receive data register (RDR) 34
It will be in the state of being stored respectively.

Then, a signal requesting interruption of the execution is input to the CPU 11 (step 640). Upon receiving the signal, the CPU 11 releases the internal bus 10 and stops after finishing the instruction currently being executed. So CPU11
Detected that the executing instruction of
5), utilizing the released internal bus 10 DMA controller
20 executes the following processing.

That is, the value of the DMA input address register 22 is incremented by 1 (step 650), and the data of the DMA buffer register 28 (first byte of word data) is first loaded into the address of the RAM 14 pointed to by this register 22 (step 655). ). Next, the data in the reception data register (RDR) 34, that is, the second byte of the word data is loaded into the buffer register 28 (step 660).

Then, the value of the DMA input address register 22 is incremented by 1 (step 665), and D
Data of MA buffer register 28, that is, 2 of word data
The byte is transferred (step 670). In this way, after the reception of the data of 2 bytes is completed, the stop request signal to the CPU 11 is released in step 680 (first
(See Fig. 0), then set the value of DMA input data counter 24 to 1
Decrement only (step 690) and repeat the process from step 600. As a result, every time 1 word and 2 bytes of data is output from the transmission ECU 5, the CPU 1
Stop 1 and transfer data to RAM14.

In this way, data is sequentially received word by word, and when the number of words set in the DMA input data counter 24 is received in advance, the determination in step 625 is “YES”, so that all data is received. The value 1 is set to the input completion flag on the assumption that it has been received (step 69).
5) Set the data reception signal RQR to high level (= 1) via the serial communication controller 31 (step 69).
8) After that, the above-mentioned processing is repeated from step 600 again.

In the present embodiment, the processing of step 623 corresponds to the receivable notification means, the DMA buffer register 28 and the reception data register 34, and the processing of steps 635, 636637, and 639 correspond to the reception data storage means. , Steps 640-6
The processing of 80 corresponds to the reception data transfer means.

As described above, when the transmission ECU 5 receives the data reception signal RQR and outputs the data, the CPU 11 sends the data to the CPU 11 for the five steps of the DMA controller 20 for each step of the data reception by the serial communication control device 3 of the present embodiment. First
The data can be received only by stopping the operation (see FIG. 11, about 2 [μsec] in this embodiment). Therefore, there is almost no communication control load on the user program, and data can be received at high speed at any timing. As a result, for the transmission ECU5,
The serial data transmission process can be performed at an arbitrary timing, the load on the program can be reduced, and the data can be output at high speed.

As described above, according to the serial communication control device 3 of the present embodiment, serial communication with the transmission ECU 5 can be executed at an extremely high speed and with an extremely small load on the CPU 11. Moreover, the communication partner, CPU51
The transmission ECU 5 whose transmission and reception of data is controlled by the transmission ECU 5 can execute the serial data reception process and the transmission process at any timing, so that the transmission ECU 5 also reduces the load on the program executed by the CUP 51. Thus, it is possible to construct a distributed control system with extremely excellent control response.

The serial communication control device 3 of the present embodiment can also be connected to the serial communication control device 3 having the same configuration to realize higher speed communication. FIG. 12 is a block diagram showing a connection state in this case. The serial communication control device 3 transmits data to the serial communication control device 3 of the other party at a predetermined interval T while the data transmission request signal RQT is at a low level, and the serial communication control device 3 receives its own data acceptance signal.
Receives serial data from the other party while holding RQR low. The 13th timing chart
Shown in the figure. The signal CLK is a clock, and the serial data is output in synchronization with this clock CLK.

Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments. For example, a configuration in which a plurality of serial communication control devices are networked,
Needless to say, the present invention can be implemented in various modes without departing from the scope of the present invention.

Effects of the Invention As described in detail above, according to the serial communication control device of the present invention, there is an excellent effect that the load on the central processing unit can be minimized and high-speed serial communication can be realized. Moreover, since the other communication control device, which is a communication partner, can send and receive data at an arbitrary timing convenient for itself, the other communication control device also executes processing for controlling the controlled object. It does not hinder the operation.

Therefore, according to the serial communication control device of the present invention, it is possible to construct a distributed control system having extremely excellent control response.

[Brief description of drawings]

FIG. 1 is a block diagram showing an internal configuration of an engine ECU 1 and a transmission ECU 5 incorporating a serial communication control device 3 as an embodiment, and FIG. 2 is a schematic configuration diagram of an internal combustion engine 71 and an automatic transmission 75. FIG. 4 is an explanatory diagram for explaining the configuration of data used in serial communication, FIG. 4 is a flowchart showing an output process executed by the CPU 11 of the engine ECU 1, and FIG. 5 is a data reception process routine executed by the CPU 51 of the transmission ECU 5. A flow chart, FIG. 6 is a timing chart showing a communication state, FIG. 7 is a flow chart showing a DMA data transmission processing routine executed by the DMA controller 20 of the serial communication control device 3,
FIG. 8 is a flow chart showing an input process executed by the CPU 11 of the engine ECU 1, and FIG. 9 is a flow chart of the transmission ECU 5.
10 is a flowchart showing a data transmission processing routine executed by the CPU 51, FIG. 10 is a timing chart showing a communication state, and FIG. 11 is a flowchart showing a DMA data reception processing routine executed by the DMA controller 20 of the serial communication control device 3. FIG. 12 is a block diagram showing a connection state between the serial communication control devices 3, and FIG. 13 is a timing chart showing a communication state in that case. 1 …… Engine ECU 3 …… Serial communication control device 5 …… Transmission ECU 10 …… Internal bus 11 …… CPU 14 …… RAM 20 …… DMA controller 22 …… DMA input address register 23 …… DMA output address register 24 ...... DMA input data counter 25 …… DMA output data counter 28,29 …… DMA buffer register 31 …… Serial communication controller 33 …… Reception S / P conversion register 34 …… Reception data register 36 …… Transmission data register 37 ...... Sending P / S conversion register 51 …… CPU

Claims (1)

(57) [Claims] 1. A serial communication control device, which is connected to a bus that mediates the exchange of addresses and data with respect to an occasional storage means capable of reading and writing data at any time by a central processing unit, and which transmits and receives data to and from other communication control devices. Transmission data storage means for storing a plurality of data to be transmitted, transmission request detection means for detecting a data transmission request from the other communication control device, and the transmission request detection means for transmitting the transmission request. Data transmission means for transmitting the data stored in the transmission data storage means one by one each time when the transmission request is detected by the transmission request detection means. If no data is stored, the bus is occupied and a plurality of data to be transmitted are read out from the storage means at any time, and the data are stored in advance. Transmission data preparation means for operating the data transmission means by storing it in the transmission data storage means, receivable notification means for notifying the other communication control device that data can be received, and the receivable notification means And a reception data accumulating unit for accumulating data transmitted from the other communication control device in units of a plurality of units in response to the receivable notification by A serial communication control device comprising: a reception data transfer means for occupying the bus and transferring the data in the reception data storage means to the storage means at any time.